On 11/8/23 22:45, Peter Xu wrote:
On Mon, Nov 06, 2023 at 10:38:14PM +0100, William Roche wrote:
But it implies a lot of other changes:
- The source has to flag the error pages to indicate a poison
(new flag in the exchange protocole)
- The destination has to be able to deal wit
>> From: Antonio Caggiano
>>
>> The first time gd_egl_scanout_texture() is called, there's a possibility
>> that the GTK drawing area might not be realized yet, in which case its
>> associated GdkWindow is NULL. This means gd_egl_init() was also skipped
>> and the EGLContext and EGLSurface stored
Cédric,
I have sent an updated version of the patch that fixes the vsx_f2i_nan.c
compilation errors and ./script/checkpatch.pl errors, and the updated version
of the patch can be found at
https://patchew.org/QEMU/sn6pr05mb5837524077f6c8a2a482b41a9d...@sn6pr05mb5837.namprd05.prod.outlook.com/.
Coverty found that the shift of TARGET_PAGE_SIZE (32-bit type) might
overflow. Fix it by casting TARGET_PAGE_SIZE to a 64-bit type before
doing the shift (CID 1523902 and CID 1523908).
Reported-by: Peter Maydell
Signed-off-by: Helge Deller
diff --git a/target/hppa/mem_helper.c b/target/hppa/me
For power10, a pca9552 device is used for PCIe slot hotplug power
control by the Power Hypervisor code. The code expects that some
time after it enables power to a PCIe slot by asserting one of the
pca9552 GPIO pins 0-4, it should see a "power good" signal asserted
on one of pca9552 GPIO pins 5-9.
The QEMU I2C buses and devices use the resettable
interface for resetting while the PNV I2C controller
and parent buses and devices have not yet transitioned
to this new interface and use the old reset strategy.
This was preventing the I2C buses and devices wired
to the PNV I2C controller from bein
This series of patches includes support, tests and fixes for
adding PCA9552 and PCA9554 I2C devices to the powernv10 chip.
The PCA9552 device is used for PCIe slot hotplug power control
and monitoring, while the PCA9554 device is used for presence
detection of IBM CableCard devices. Both devices
The PNV I2C engines for power9 and power10 were being assigned a base
XSCOM address that was off by one I2C engine's address range such
that engine 0 had engine 1's address and so on. The xscom address
assignment was being based on the device tree engine numbering, which
starts at 1. Rather than
The Power Hypervisor code expects to see a pca9552 device connected
to the 3rd PNV I2C engine on port 1 at I2C address 0x63 (or left-
justified address of 0xC6). This is used by hypervisor code to
control PCIe slot power during hotplug events.
Signed-off-by: Glenn Miles
---
Based-on: <2023102418
The Power Hypervisor code expects to see a pca9554 device connected
to the 3rd PNV I2C engine on port 1 at I2C address 0x25 (or left-
justified address of 0x4A). This is used by the hypervisor code to
detect if a "Cable Card" is present.
Signed-off-by: Glenn Miles
---
hw/misc/Kconfig | 4 ++
The PNV I2C Controller was clearing the status register
after a reset without repopulating the "upper threshold
for I2C ports", "Command Complete" and the SCL/SDA input
level fields.
Fixed this for resets caused by a system reset as well
as from writing to the "Immediate Reset" register.
Signed-o
Tests the following for both P9 and P10:
- I2C master POR status
- I2C master status after immediate reset
Tests the following for P10 only:
- Config pca9552 hotplug device pins as inputs then
Read the INPUT0/1 registers to verify all pins are high
- Connected GPIO pin tests of P10 PCA
Specs are available here:
https://www.nxp.com/docs/en/data-sheet/PCA9554_9554A.pdf
This is a simple model supporting the basic registers for GPIO
mode. The device also supports an interrupt output line but the
model does not yet support this.
Signed-off-by: Glenn Miles
---
MAINTAINERS
We cannot operate on the multifd semaphores outside of the multifd
channel thread because multifd_save_cleanup() can run in parallel and
attempt to destroy the mutexes, which causes an assert.
Looking at the places where we use the semaphores aside from the
migration thread, there's only the TLS h
changes:
- dropped the Error patch
- removed p->running
- joined the TLS thread
v1:
https://lore.kernel.org/r/20231109165856.15224-1-faro...@suse.de
We're calling qemu_sem_post() in threads other than the multifd
channel and the migration thread. This is vulnerable to a race with
multifd_save_cle
We're currently leaking the resources of the TLS thread by not joining
it and also overwriting the p->thread pointer altogether.
Signed-off-by: Fabiano Rosas
---
migration/multifd.c | 10 +-
migration/multifd.h | 1 +
2 files changed, 10 insertions(+), 1 deletion(-)
diff --git a/migrat
This is being shadowed but the assignments at
multifd_channel_connect() and multifd_tls_channel_connect() .
Signed-off-by: Fabiano Rosas
---
migration/multifd.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/migration/multifd.c b/migration/multifd.c
index ec58c58082..40946
We currently only need p->running to avoid calling qemu_thread_join()
on a non existent thread if the thread has never been created. We
could turn the QemuThread into a pointer and check for NULL instead
and get rid of the p->running flag. Testing the pointer directly is
more precise and less prone
* Sam James :
>
> Helge Deller writes:
>
> > On 11/3/23 13:53, Sam James wrote:
> >> Sam James writes:
> >>> I recently hit an issue with systemd-254 which tries to use the new
> >>> prctl(PR_SET_MDWE) for systemd's MemoryDenyWriteExecute functionality.
> >
> > Is this still a problem?
>
> Yes
On 11/10/23 21:25, Helge Deller wrote:
* Sam James :
Helge Deller writes:
On 11/3/23 13:53, Sam James wrote:
Sam James writes:
I recently hit an issue with systemd-254 which tries to use the new
prctl(PR_SET_MDWE) for systemd's MemoryDenyWriteExecute functionality.
Is this still a probl
When calling trace_vmware_verify_rect_greater_than_bound() replace
"y" with "h" and y with h
Found by Linux Verification Center (linuxtesting.org) with SVACE.
Fixes: 02218aedb1 ("hw/display/vmware_vga: replace fprintf calls with trace
events")
Signed-off-by: Alexandra Diupina
---
hw/display/vm
From: Oleksandr Tyshchenko
This patch adds basic virtio-pci support for xen_arm machine.
It provides a flexible way to configure virtio-pci resources with
xenstore. We made this for several reasons:
- We don't want to clash with vPCI devices, so we need information
from Xen toolstack on which
On Thu, Nov 09, 2023 at 06:15:51PM +0100, Thomas Huth wrote:
> On 09/11/2023 17.58, Daniel P. Berrangé wrote:
> > On Thu, Nov 09, 2023 at 04:35:56PM +0100, Philippe Mathieu-Daudé wrote:
> > > On 9/11/23 16:35, Philippe Mathieu-Daudé wrote:
> > > > This Cirrus-CI based job takes ~12min, similarly to
From: Oleksandr Tyshchenko
Both state (XenbusStateClosed) and online (0) are expected by
toolstack/xl devd to completely destroy the device. But "offline"
is never being set by the backend resulting in timeout during
domain destruction, garbage in Xestore and still running Qemu
instance.
Signed-
From: Oleksandr Tyshchenko
The number of vCPUs used for the IOREQ configuration (machine->smp.cpus)
should really match the system value as for each vCPU we setup a dedicated
evtchn for the communication with Xen at the runtime. This is needed
for the IOREQ to be properly configured and work if t
From: Oleksandr Tyshchenko
Instead of forcing the owner to domid 0, use XS_PRESERVE_OWNER to save
the previous owner of the directory.
Note that for other than Dom0 domain (non toolstack domain) the
"driver_domain" property should be set in domain config file for the
toolstack to create required
Add option to preserve owner when creating an entry in Xen Store. This
may be needed in cases when Qemu is working as device model in a
domain that is Domain-0, e.g. in driver domain.
"owner" parameter for qemu_xen_xs_create() function can have special
value XS_PRESERVE_OWNER, which will make spec
From: Oleksandr Tyshchenko
The PV backend running in other than Dom0 domain (non toolstack domain)
is not allowed to destroy frontend/backend directories. The more,
it does not need to do that at all, this is purely toolstack/xl devd
business.
I do not know for what reason the backend does that
From: Oleksandr Tyshchenko
The PV backend running in other than Dom0 domain (non toolstack domain)
is not allowed to write frontend nodes. The more, the backend does not
need to do that at all, this is purely toolstack/xl devd business.
I do not know for what reason the backend does that here, t
Hello,
This patch series adds the basic support for virtio-pci for xen-arm
guests. The main changes are in "xen_arm: Add basic virtio-pci
support", while another 5 patches are adding groundwork. First 4
patches are required to run QEMU device model in a driver domain, not
only in Dom0.
Oleksandr
On Fri, Nov 10, 2023 at 6:36 PM Greg Manning wrote:
> Then hopefully when a plugin links to this, it gets the __pfnDliFailureHook2
> symbol defined and set up and everything would work. Except gcc strips
> out any unreferenced symbols from static libs when linking. So the plugin
> would have to be
On 11/10/23 11:35, Helge Deller wrote:
Coverty found that the shift of TARGET_PAGE_SIZE (32-bit type) might
overflow. Fix it by casting TARGET_PAGE_SIZE to a 64-bit type before
doing the shift (CID 1523902 and CID 1523908).
Reported-by: Peter Maydell
Signed-off-by: Helge Deller
Reviewed-by:
Two functions were reported to have dead code, remove the bogus
branches altogether, as well as a misplaced qemu_log call.
Reported-by: Peter Maydell
Signed-off-by: Davidlohr Bueso
---
hw/cxl/cxl-mailbox-utils.c | 43 +-
1 file changed, 15 insertions(+), 28 d
The old virtio-fs mailing list address is no longer in use. Switch to
the new mailing list address.
Cc: Philippe Mathieu-Daudé
Cc: Vivek Goyal
Cc: German Maglione
Cc: Hanna Czenczek
Signed-off-by: Stefan Hajnoczi
---
MAINTAINERS | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --g
In cpu_exec_step_atomic, we did not set CF_LAST_IO, which can
lead to a loop with cpu_io_recompile.
But since 18a536f1f8 ("Always require can_do_io") we no longer need
a flag to indicate when the last insn should have can_do_io set, so
remove the flag entirely.
Reported-by: Clément Chigot
Resolv
Fixes to the recent hppa64 cpu support to enable booting
the 64-bit linux kernel to user-space.
r~
Helge Deller (6):
target/hppa: Update to SeaBIOS-hppa version 11
hw/hppa: Require at least SeaBIOS-hppa version 11
target/hppa: Mask reserved PSW bits in expand_sm_imm
target/hppa: Fix cal
Fixes to the recent hppa64 cpu support to enable booting
the 64-bit linux kernel to user-space.
r~
Helge Deller (6):
target/hppa: Update to SeaBIOS-hppa version 11
hw/hppa: Require at least SeaBIOS-hppa version 11
target/hppa: Mask reserved PSW bits in expand_sm_imm
target/hppa: Fix cal
Align the language with pa2.0, separating absolute and physical.
The translation from absolute to physical depends on PSW.W, and
we prefer not to flush between changes.
Signed-off-by: Richard Henderson
---
target/hppa/cpu.h| 26 +
target/hppa/mem_helper.c | 41 +++
From: Helge Deller
The new SeaBIOS-hppa version 11 includes the necessary fixes to
support emulated PA2.0 CPUs and which allows starting 64-bit Linux
kernels in the guest.
Signed-off-by: Helge Deller
---
hw/hppa/machine.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/h
Direct privilege level to mmu_idx mapping has been
false for some time. Provide the correct value to
hppa_get_physical_address.
Fixes: fa824d99f9b ("target/hppa: Switch to use MMU indices 11-15")
Signed-off-by: Richard Henderson
---
target/hppa/op_helper.c | 5 +++--
1 file changed, 3 insertion
From: Helge Deller
The system mask is a restricted subset of the psw, with only
a couple of reserved bits. It is better to handle this up
front in the translator than require helper_swap_system_mask
to use cpu_hppa_get_psw and cpu_hppa_put_psw.
Signed-off-by: Helge Deller
[rth: Handle this in
From: Helge Deller
Apply the "32-bit PCI addressing on 40-bit Runway" as the default
iommu transformation. This allows PCI devices to dma PDC memory.
Signed-off-by: Helge Deller
Acked-by: Richard Henderson
Signed-off-by: Richard Henderson
---
hw/pci-host/astro.c | 73 ++-
During the conversion to decodetree, the 2-bit mask was lost.
Fixes: deee69a19fd ("target/hppa: Convert memory management insns")
Signed-off-by: Richard Henderson
---
target/hppa/translate.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/hppa/translate.c b/target/hppa
From: Helge Deller
Coverty found that the shift of TARGET_PAGE_SIZE (32-bit type) might
overflow. Fix it by casting TARGET_PAGE_SIZE to a 64-bit type before
doing the shift (CID 1523902 and CID 1523908).
Reported-by: Peter Maydell
Signed-off-by: Helge Deller
Message-Id:
Reviewed-by: Richard
From: Helge Deller
Need to use iasq_b and iaoq_b to determine back register of CR_IIASQ.
This fixes random faults when booting up Linux user space.
Signed-off-by: Helge Deller
Reviewed-by: Richard Henderson
Signed-off-by: Richard Henderson
---
target/hppa/int_helper.c | 2 +-
1 file changed,
This is the maximum that was ever supported, in the PA-8700 thru
PA-8900. If we support a larger address space than expected, we
trip up software that did not fill in all of the page table bits,
expecting them to be ignored.
Signed-off-by: Richard Henderson
---
target/hppa/cpu-param.h | 2 +-
Reduce the number of direct checks against MMU_PHYS_IDX.
Signed-off-by: Richard Henderson
---
target/hppa/cpu.h| 1 +
target/hppa/mem_helper.c | 4 ++--
target/hppa/translate.c | 20 +++-
3 files changed, 14 insertions(+), 11 deletions(-)
diff --git a/target/hppa/cpu.
Hi!
It looks like --disable-pie configure, which uses -fno-pie -no-pie flags
for the compiler, is broken: it does not not tell the *linker* about the
option, so the link fails (at least on debian bookworm):
/usr/bin/ld: libcommon.fa.p/hw_core_cpu-common.c.o: relocation R_X86_64_32 against `.roda
On 11/3/23 20:12, Jessica Clarke wrote:
Without this, we just dirty a single byte, and so if the caller writes
more than one byte to the host memory then we won't have invalidated any
translation blocks that start after the first byte and overlap those
writes. In particular, AArch64's DC ZVA impl
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