[PATCH v5 3/6] target/riscv: Remove misa_mxl validation

It is initialized with a simple assignment and there is little room for error. In fact, the validation is even more complex. Signed-off-by: Akihiko Odaki Acked-by: LIU Zhiwei Reviewed-by: Daniel Henrique Barboza --- target/riscv/tcg/tcg-cpu.c | 13 ++--- 1 file changed, 2 insertions(+)

[PATCH v5 2/6] hw/riscv: Use misa_mxl instead of misa_mxl_max

The effective MXL value matters when booting. Signed-off-by: Akihiko Odaki --- hw/riscv/boot.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c index 52bf8e67de..dad3f6e7b1 100644 --- a/hw/riscv/boot.c +++ b/hw/riscv/boot.c @@ -36,7 +36,7 @@

[PATCH v5 4/6] target/riscv: Move misa_mxl_max to class

misa_mxl_max is common for all instances of a RISC-V CPU class so they are better put into class. Signed-off-by: Akihiko Odaki --- target/riscv/cpu-qom.h | 1 + target/riscv/cpu.h | 3 +- target/riscv/cpu.c | 118 +++-- target/riscv/gdbstub

[PATCH v5 5/6] target/riscv: Validate misa_mxl_max only once

misa_mxl_max is now a class member and initialized only once for each class. This also moves the initialization of gdb_core_xml_file which will be referenced before realization in the future. Signed-off-by: Akihiko Odaki --- target/riscv/cpu.c | 21 + target/riscv/tcg

[PATCH v5 6/6] plugins: Remove an extra parameter

copy_call() has an unused parameter so remove it. Signed-off-by: Akihiko Odaki --- accel/tcg/plugin-gen.c | 9 +++-- 1 file changed, 3 insertions(+), 6 deletions(-) diff --git a/accel/tcg/plugin-gen.c b/accel/tcg/plugin-gen.c index 39b3c9351f..78b331b251 100644 --- a/accel/tcg/plugin-gen.c

Re: [PATCH V6 4/9] hw/acpi: Init GED framework with CPU hotplug events

Salil Mehta writes: > ACPI GED(as described in the ACPI 6.2 spec) can be used to generate ACPI > events > when OSPM/guest receives an interrupt listed in the _CRS object of GED. OSPM > then maps or demultiplexes the event by evaluating _EVT method. > > This change adds the support of CPU hotpl

Re: [PATCH v4 3/5] target/riscv: Move misa_mxl_max to class

On 2023/10/18 23:23, Daniel Henrique Barboza wrote: On 10/18/23 10:31, Akihiko Odaki wrote: On 2023/10/18 22:01, Daniel Henrique Barboza wrote: On 10/17/23 15:53, Akihiko Odaki wrote: misa_mxl_max is common for all instances of a RISC-V CPU class so they are better put into class. Signed-

[PATCH v14 01/18] gdbstub: Add num_regs member to GDBFeature

Currently the number of registers exposed to GDB is written as magic numbers in code. Derive the number of registers GDB actually see from XML files to replace the magic numbers in code later. Signed-off-by: Akihiko Odaki Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Alex Bennée --- include

[PATCH v14 00/18] plugins: Allow to read registers

Based-on: <20231019101030.128431-1-akihiko.od...@daynix.com> ("[PATCH v5 0/6] gdbstub and TCG plugin improvements") I and other people in the University of Tokyo, where I research processor design, found TCG plugins are very useful for processor design exploration. The feature we find missing is

[PATCH v14 02/18] gdbstub: Introduce gdb_find_static_feature()

This function is useful to determine the number of registers exposed to GDB from the XML name. Signed-off-by: Akihiko Odaki Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Alex Bennée Reviewed-by: Richard Henderson --- include/exec/gdbstub.h | 2 ++ gdbstub/gdbstub.c | 13 +

[PATCH v14 15/18] cpu: Call plugin hooks only when ready

The initialization and exit hooks will not affect the state of vCPU outside TCG context, but they may depend on the state of vCPU. Therefore, it's better to call plugin hooks after the vCPU state is fully initialized and before it gets uninitialized. Signed-off-by: Akihiko Odaki --- cpu-target.c

[PATCH v14 10/18] gdbstub: Simplify XML lookup

Now we know all instances of GDBFeature that is used in CPU so we can traverse them to find XML. This removes the need for a CPU-specific lookup function for dynamic XMLs. Signed-off-by: Akihiko Odaki --- include/exec/gdbstub.h | 2 + gdbstub/gdbstub.c | 119 +-

RE: [PATCH V6 4/9] hw/acpi: Init GED framework with CPU hotplug events

Hi Alex, > From: Alex Bennée > Sent: Thursday, October 19, 2023 11:16 AM > To: Salil Mehta > Cc: qemu-devel@nongnu.org; qemu-...@nongnu.org; m...@kernel.org; jean- > phili...@linaro.org; Jonathan Cameron ; > lpieral...@kernel.org; peter.mayd...@linaro.org; > richard.hender...@linaro.org; imamm..

[PATCH v14 06/18] target/riscv: Use GDBFeature for dynamic XML

In preparation for a change to use GDBFeature as a parameter of gdb_register_coprocessor(), convert the internal representation of dynamic feature from plain XML to GDBFeature. Signed-off-by: Akihiko Odaki --- target/riscv/cpu.h | 5 +-- target/riscv/cpu.c | 4 +-- target/riscv/gdbstub

[PATCH v14 04/18] target/arm: Use GDBFeature for dynamic XML

In preparation for a change to use GDBFeature as a parameter of gdb_register_coprocessor(), convert the internal representation of dynamic feature from plain XML to GDBFeature. Signed-off-by: Akihiko Odaki Acked-by: Richard Henderson --- target/arm/cpu.h | 21 +++--- target/arm/internals

[PATCH v14 12/18] hw/core/cpu: Remove gdb_get_dynamic_xml member

This function is no longer used. Signed-off-by: Akihiko Odaki --- include/hw/core/cpu.h | 4 target/arm/cpu.h | 6 -- target/ppc/cpu.h | 1 - target/arm/cpu.c | 1 - target/arm/gdbstub.c | 18 -- target/ppc/cpu_init.c | 3 --- target/ppc/gdbstub.c |

[PATCH v14 14/18] gdbstub: Expose functions to read registers

gdb_find_feature() and gdb_find_feature_register() find registers. gdb_read_register() actually reads registers. Signed-off-by: Akihiko Odaki --- include/exec/gdbstub.h | 5 + gdbstub/gdbstub.c | 31 ++- 2 files changed, 35 insertions(+), 1 deletion(-) diff

[PATCH v14 16/18] plugins: Use different helpers when reading registers

This avoids optimizations incompatible when reading registers. Signed-off-by: Akihiko Odaki --- accel/tcg/plugin-helpers.h | 3 ++- include/exec/plugin-gen.h | 4 ++-- include/hw/core/cpu.h | 4 ++-- include/qemu/plugin.h | 3 +++ plugins/plugin.h | 5 +++-- accel/tcg/p

[PATCH v14 11/18] gdbstub: Infer number of core registers from XML

GDBFeature has the num_regs member so use it where applicable to remove magic numbers. Signed-off-by: Akihiko Odaki --- include/hw/core/cpu.h | 3 ++- target/s390x/cpu.h | 2 -- gdbstub/gdbstub.c | 5 - target/arm/cpu.c| 1 - target/arm/cpu64.c | 1 - target/avr/cpu

Re: [RFC PATCH v2 3/6] migration/multifd: Decouple control flow from the SYNC packet

Fabiano Rosas wrote: > We currently use the 'sem_sync' semaphore on the sending side: > > 1) to know when the multifd_send_thread() has finished sending the >MULTIFD_FLAG_SYNC packet; > > This is unnecessary. Multifd sends packets one by one and completion > is already bound by the 'sem' s

[PATCH v14 05/18] target/ppc: Use GDBFeature for dynamic XML

In preparation for a change to use GDBFeature as a parameter of gdb_register_coprocessor(), convert the internal representation of dynamic feature from plain XML to GDBFeature. Signed-off-by: Akihiko Odaki Reviewed-by: Richard Henderson --- target/ppc/cpu-qom.h | 4 ++-- target/ppc/cpu.h

[PATCH v14 09/18] gdbstub: Change gdb_get_reg_cb and gdb_set_reg_cb

Align the parameters of gdb_get_reg_cb and gdb_set_reg_cb with the gdb_read_register and gdb_write_register members of CPUClass to allow to unify the logic to access registers of the core and coprocessors in the future. Signed-off-by: Akihiko Odaki --- include/exec/gdbstub.h | 4 +- target

[PATCH v14 03/18] gdbstub: Introduce GDBFeatureBuilder

GDBFeatureBuilder unifies the logic to generate dynamic GDBFeature. Signed-off-by: Akihiko Odaki Reviewed-by: Richard Henderson --- include/exec/gdbstub.h | 23 +++ gdbstub/gdbstub.c | 65 ++ 2 files changed, 88 insertions(+) diff --git

[PATCH v14 18/18] contrib/plugins: Allow to log registers

This demonstrates how a register can be read from a plugin. Signed-off-by: Akihiko Odaki --- docs/devel/tcg-plugins.rst | 10 +++- contrib/plugins/execlog.c | 120 +++-- 2 files changed, 97 insertions(+), 33 deletions(-) diff --git a/docs/devel/tcg-plugins.rst

[PATCH v14 17/18] plugins: Allow to read registers

It is based on GDB protocol to ensure interface stability. The timing of the vcpu init hook is also changed so that the hook will get called after GDB features are initialized. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1706 Signed-off-by: Akihiko Odaki --- include/qemu/qemu-plugin

[PATCH v14 08/18] gdbstub: Use GDBFeature for GDBRegisterState

Simplify GDBRegisterState by replacing num_regs and xml members with one member that points to GDBFeature. Signed-off-by: Akihiko Odaki Reviewed-by: Alex Bennée --- gdbstub/gdbstub.c | 14 ++ 1 file changed, 6 insertions(+), 8 deletions(-) diff --git a/gdbstub/gdbstub.c b/gdbstub/g

[PATCH v14 07/18] gdbstub: Use GDBFeature for gdb_register_coprocessor

This is a tree-wide change to introduce GDBFeature parameter to gdb_register_coprocessor(). The new parameter just replaces num_regs and xml parameters for now. GDBFeature will be utilized to simplify XML lookup in a following change. Signed-off-by: Akihiko Odaki Acked-by: Alex Bennée --- inclu

[PATCH v14 13/18] gdbstub: Add members to identify registers to GDBFeature

These members will be used to help plugins to identify registers. The added members in instances of GDBFeature dynamically generated by CPUs will be filled in later changes. Signed-off-by: Akihiko Odaki --- include/exec/gdbstub.h | 3 +++ gdbstub/gdbstub.c | 12 +--- target/riscv

Re: [RFC PATCH v2 5/6] migration/multifd: Stop setting 'quit' outside of channels

Fabiano Rosas wrote: > We shouldn't really be touching channel state from outside the > channels except for the transfer of pages. > > Move the setting of p->quit into the channel. Keep posting the 'sem' > from multifd_send_terminate_threads() so any channel waiting on the > semaphore will unblock

Re: [RFC PATCH v2 6/6] migration/multifd: Bring back the 'ready' semaphore

Fabiano Rosas wrote: > Bring back the 'ready' semaphore, but this time make it per-channel, > so that we can do true lockstep switching of MultiFDPages without > taking the channel lock. > > Drop the channel lock as it now becomes useless. The rules for > accessing the MultiFDSendParams are: > > -

[PATCH v2 08/19] target/i386: implement CMPccXADD

The main difficulty here is that a page fault when writing to the destination must not overwrite the flags. Therefore, the compute-flags helper must be called with a temporary destination instead of using gen_jcc1*. For simplicity, I am using an unconditional cmpxchg operation, that becomes a NOP

[PATCH v2 02/19] target/i386: validate VEX.W for AVX instructions

Instructions in VEX exception class 6 generally look at the value of VEX.W. Note that the manual places some instructions incorrectly in class 4, for example VPERMQ which has no non-VEX encoding and no legacy SSE analogue. AMD does a mess of its own, as documented in the comment that this patch a

[PATCH v2 01/19] target/i386: group common checks in the decoding phase

In preparation for adding more similar checks, move the VEX.L=0 check and several X86_SPECIAL_* checks to a new field, where each bit represent a common check on unused bits, or a restriction on the processor mode. Likewise, many SVM intercepts can be checked during the decoding phase, the main ex

[PATCH v2 06/19] target/i386: accept full MemOp in gen_ext_tl

Use MO_SIGN to indicate signed vs. unsigned extension, and filter out bits other than MO_SIGN and MO_SIZE. Signed-off-by: Paolo Bonzini --- target/i386/tcg/translate.c | 30 +++--- 1 file changed, 15 insertions(+), 15 deletions(-) diff --git a/target/i386/tcg/translate.c

[PATCH v2 09/19] target/i386: do not clobber A0 in POP translation

The new decoder likes to compute the address in A0 very early, so the gen_lea_v_seg in gen_pop_T0 would clobber the address of the memory operand. Instead use T0 since it is already available and will be overwritten immediately after. Signed-off-by: Paolo Bonzini --- target/i386/tcg/translate.c

[PATCH v2 05/19] tests/tcg/i386: test-avx: add test cases for SHA new instructions

--- tests/tcg/i386/test-avx.py | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/tests/tcg/i386/test-avx.py b/tests/tcg/i386/test-avx.py index 641a2ef69eb..6063fb2d11d 100755 --- a/tests/tcg/i386/test-avx.py +++ b/tests/tcg/i386/test-avx.py @@ -9,7 +9,7 @@ archs = [ "SSE"

[PATCH v2 07/19] target/i386: introduce flags writeback mechanism

ALU instructions can write to both memory and flags. If the CC_SRC* and CC_DST locations have been written already when a memory access causes a fault, the value in CC_SRC* and CC_DST might be interpreted with the wrong CC_OP (the one that is in effect before the instruction. Besides just using t

[PATCH v2 11/19] target/i386: move 00-5F opcodes to new decoder

Signed-off-by: Paolo Bonzini --- target/i386/tcg/decode-new.c.inc | 116 ++ target/i386/tcg/decode-new.h | 3 + target/i386/tcg/emit.c.inc | 203 +++ target/i386/tcg/translate.c | 2 +- 4 files changed, 323 insertions(+), 1 deletion(-

[PATCH v2 12/19] target/i386: adjust decoding of J operand

gen_jcc() has been changed to accept a relative offset since the new decoder was written. Adjust the J operand, which is meant to be used with jump instructions and gen_jcc(), to not include the program counter and to not truncate the result, as both operations are now performed by common code. T

[PATCH v2 13/19] target/i386: split eflags computation out of gen_compute_eflags

The new x86 decoder wants to compute EFLAGS before writeback, which can be an issue for some instructions such as ARPL. Extract code to compute the EFLAGS without clobbering CC_SRC, in case the ARPL memory write causes a fault. Signed-off-by: Paolo Bonzini --- target/i386/tcg/translate.c | 18 +

[PATCH v2 03/19] target/i386: implement SHA instructions

The implementation was validated with OpenSSL and with the test vectors in https://github.com/rust-lang/stdarch/blob/master/crates/core_arch/src/x86/sha.rs. The instructions provide a ~25% improvement on hashing a 64 MiB file: runtime goes down from 1.8 seconds to 1.4 seconds; instruction count on

[PATCH v2 00/19] target/i386: decoder changes for 8.2

This includes: - implementing SHA and CMPccXADD instruction extensions - introducing a new mechanism for flags writeback that avoids a tricky failure - converting the more orthogonal parts of the one-byte opcode map, as well as the CMOVcc and SETcc instructions. Tested by booting several 32

[PATCH v2 04/19] tests/tcg/i386: initialize more registers in test-avx

Some instructions use YMM0 implicitly, or use YMM9 as a read-modify-write register destination. Initialize those registers as well. Signed-off-by: Paolo Bonzini --- tests/tcg/i386/test-avx.c | 8 1 file changed, 8 insertions(+) diff --git a/tests/tcg/i386/test-avx.c b/tests/tcg/i386/t

[PATCH v2 17/19] target/i386: move remaining conditional operations to new decoder

Move long-displacement Jcc, SETcc and CMOVcc to the new decoder. While filling in the tables makes the code seem longer, the new emitters are all just one line of code. Signed-off-by: Paolo Bonzini --- target/i386/tcg/decode-new.c.inc | 56 target/i386/tcg/decode

[PATCH] hw/char/mcf_uart: Have mcf_uart_create() return DeviceState

There is no point in having mcf_uart_init() demote the DeviceState pointer and return a void one. Directly return the real typedef. mcf_uart_init() do both init + realize: rename as mcf_uart_create(). Similarly, mcf_uart_mm_init() do init / realize / mmap: rename as mcf_uart_create_mmap(). Signe

[PATCH v2 14/19] tcg: add negsetcondi

This can be useful to write a shift bit extraction that does not depend on TARGET_LONG_BITS. Signed-off-by: Paolo Bonzini --- include/tcg/tcg-op-common.h | 4 include/tcg/tcg-op.h| 2 ++ tcg/tcg-op.c| 12 3 files changed, 18 insertions(+) diff --git a

[PATCH v2 15/19] target/i386: move 60-BF opcodes to new decoder

Signed-off-by: Paolo Bonzini --- target/i386/tcg/decode-new.c.inc | 157 ++ target/i386/tcg/decode-new.h | 3 + target/i386/tcg/emit.c.inc | 355 ++- target/i386/tcg/translate.c | 38 ++-- 4 files changed, 536 insertions(+), 17 deletions(-

[PATCH v2 10/19] target/i386: reintroduce debugging mechanism

Signed-off-by: Paolo Bonzini --- target/i386/tcg/decode-new.c.inc | 3 +++ target/i386/tcg/translate.c | 27 +++ 2 files changed, 30 insertions(+) diff --git a/target/i386/tcg/decode-new.c.inc b/target/i386/tcg/decode-new.c.inc index 57a5014bc8a..2f614e2a6f0 100644

[PATCH v2 16/19] target/i386: move operand load and writeback out of gen_cmovcc1

Similar to gen_setcc1, make gen_cmovcc1 receive TCGv. This is more friendly to simultaneous implementation in the old and the new decoder. A small wart is that s->T0 of CMOV is currently the *second* argument (which would ordinarily be in T1). Therefore, the condition as to be inverted in order

[PATCH v2 18/19] target/i386: remove now converted opcodes from old decoder

Signed-off-by: Paolo Bonzini --- target/i386/tcg/translate.c | 705 +--- 1 file changed, 4 insertions(+), 701 deletions(-) diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c index 1f3cc6361c0..6e091fdb7f6 100644 --- a/target/i386/tcg/translate.

[PATCH v2 19/19] target/i386: remove gen_op

It is not used anymore by the old decoder, inline the CMP case into CMPS and SCAS. Signed-off-by: Paolo Bonzini --- target/i386/tcg/translate.c | 145 +++- 1 file changed, 12 insertions(+), 133 deletions(-) diff --git a/target/i386/tcg/translate.c b/target/i386/

Re: [PATCH v2 1/2] hw/cxl: Pass CXLComponentState to cache_mem_ops

On Wed, 18 Oct 2023 16:24:07 +0800 Li Zhijian wrote: > cache_mem_ops.{read,write}() interprets opaque as > CXLComponentState(cxl_cstate) instead of ComponentRegisters(cregs). > > Fortunately, cregs is the first member of cxl_cstate, so their values are > the same. > > Fixes: 9e58f52d3f8 ("hw/cx

Re: [PATCH v2 03/19] target/i386: implement SHA instructions

Hi Paolo, On 19/10/23 12:46, Paolo Bonzini wrote: The implementation was validated with OpenSSL and with the test vectors in https://github.com/rust-lang/stdarch/blob/master/crates/core_arch/src/x86/sha.rs. The instructions provide a ~25% improvement on hashing a 64 MiB file: runtime goes down

[PATCH v2 01/11] migration: Give one error if trying to set MULTIFD and XBZRLE

Signed-off-by: Juan Quintela --- migration/options.c | 7 +++ 1 file changed, 7 insertions(+) diff --git a/migration/options.c b/migration/options.c index 42fb818956..b8c3c3218d 100644 --- a/migration/options.c +++ b/migration/options.c @@ -618,6 +618,13 @@ bool migrate_caps_check(bool *old_

[PATCH v2 09/11] migration: Move ram_flush_compressed_data() to ram-compress.c

As we export it, rename it compress_flush_data(). Signed-off-by: Juan Quintela --- migration/ram-compress.h | 1 + migration/ram-compress.c | 9 + migration/ram.c | 17 - 3 files changed, 14 insertions(+), 13 deletions(-) diff --git a/migration/ram-compress.h

[PATCH v2 07/11] migration: Create compress_update_rates()

So we can move more compression_counters stuff to ram-compress.c. Create compression_counters struct to add the stuff that was on MigrationState. Reviewed-by: Lukas Straub Signed-off-by: Juan Quintela --- migration/ram-compress.h | 1 + migration/ram.h | 1 - migration/ram-compress.c

[PATCH v2 02/11] migration: Give one error if trying to set COMPRESSION and XBZRLE

Signed-off-by: Juan Quintela --- migration/options.c | 7 +++ 1 file changed, 7 insertions(+) diff --git a/migration/options.c b/migration/options.c index b8c3c3218d..37fa1cfe74 100644 --- a/migration/options.c +++ b/migration/options.c @@ -625,6 +625,13 @@ bool migrate_caps_check(bool *old_

[PATCH v2 08/11] migration: Export send_queued_data()

This function is only used for compression. So we rename it as compress_send_queued_data(). We put it on ram-compress.h because we are moving it later to ram-compress.c. Signed-off-by: Juan Quintela --- migration/ram-compress.h | 1 + migration/ram.c | 6 +++--- 2 files changed, 4 ins

[PATCH v2 04/11] migration: Make compress_data_with_multithreads return bool

Signed-off-by: Juan Quintela Reviewed-by: Lukas Straub --- migration/ram-compress.h | 4 ++-- migration/ram-compress.c | 17 ++--- migration/ram.c | 3 +-- 3 files changed, 13 insertions(+), 11 deletions(-) diff --git a/migration/ram-compress.h b/migration/ram-compress.h

Re: [PATCH 4/5] migration iaa-compress: Add IAA initialization and deinitialization

Yuan Liu wrote: > This patch defines the structure for IAA jobs related to data > compression and decompression, as well as the initialization and > deinitialization processes for IAA. > > Signed-off-by: Yuan Liu > Reviewed-by: Nanhai Zou You should be using orderfile. $ less .git/config ... [

Re: [PATCH v4 2/4] hw/cxl: Use switch statements for read and write of cachemem registers

On Thu, 19 Oct 2023 05:23:04 -0400 "Michael S. Tsirkin" wrote: > On Thu, Oct 19, 2023 at 10:09:24AM +0100, Jonathan Cameron wrote: > > On Wed, 18 Oct 2023 17:31:42 +0100 > > Jonathan Cameron wrote: > > > > > On Wed, 18 Oct 2023 17:22:39 +0100 > > > Jonathan Cameron wrote: > > > > > > > On

Re: [PATCH 0/5] Live Migration Acceleration with IAA Compression

Yuan Liu wrote: > Hi, > > I am writing to submit a code change aimed at enhancing live migration > acceleration by leveraging the compression capability of the Intel > In-Memory Analytics Accelerator (IAA). > > Enabling compression functionality during the live migration process can > enhance perf

[PATCH v2 10/11] migration: Merge flush_compressed_data() and compress_flush_data()

Signed-off-by: Juan Quintela --- migration/ram-compress.h | 1 - migration/ram-compress.c | 17 ++--- 2 files changed, 6 insertions(+), 12 deletions(-) diff --git a/migration/ram-compress.h b/migration/ram-compress.h index 7ba01e2882..e222887fb7 100644 --- a/migration/ram-compress.h

Re: [PATCH 2/5] qapi/migration: Introduce compress-with-iaa migration parameter

Yuan Liu wrote: > Introduce the compress-with-iaa=on/off option to enable or disable live > migration data (de)compression with the In-Memory Analytics Accelerator > (IAA). > > The data (de)compression with IAA feature is based on the migration > compression capability, which is enabled by setting

Re: [PATCH 3/5] ram compress: Refactor ram compression functions

Yuan Liu wrote: > Refactor legacy RAM compression functions to support both IAA > compression and CPU compression. > > Signed-off-by: Yuan Liu > Reviewed-by: Nanhai Zou Cmopression code is declared obsolete (see patches on list). I don't think it is a good idea that you put things there. And h

Re: [PATCH 5/5] migration iaa-compress: Implement IAA compression

Yuan Liu wrote: > Implement the functions of IAA for data compression and decompression. > The implementation uses non-blocking job submission and polling to check > the job completion status to reduce IAA's overhead in the live migration > process. > > Signed-off-by: Yuan Liu > Reviewed-by: Nanh

Re: [PATCH v2 00/19] target/i386: decoder changes for 8.2

On 10/19/23 12:46, Paolo Bonzini wrote: This includes: - implementing SHA and CMPccXADD instruction extensions - introducing a new mechanism for flags writeback that avoids a tricky failure - converting the more orthogonal parts of the one-byte opcode map, as well as the CMOVcc and SETcc

Re: [PATCH 0/5] Live Migration Acceleration with IAA Compression

Yuan Liu wrote: > Hi, > > I am writing to submit a code change aimed at enhancing live migration > acceleration by leveraging the compression capability of the Intel > In-Memory Analytics Accelerator (IAA). > > Enabling compression functionality during the live migration process can > enhance perf

Re: [PATCH v2 03/19] target/i386: implement SHA instructions

On 10/19/23 12:59, Philippe Mathieu-Daudé wrote: +    /* Even round */ +    t = SHA256_CH(E, F, G) + SHA256_RNDS1(E) + wk0 + H; +    AA = t + SHA256_MAJ(A, B, C) + SHA256_RNDS0(A); +    EE = t + D; + +    /* These will be B and F at the end of the odd round */ +    d->L(2) = AA; +    d->L(0) = E

Re: [PULL 13/38] migration: Non multifd migration don't care about multifd flushes

17.10.2023 11:29, Juan Quintela: RDMA was having trouble because migrate_multifd_flush_after_each_section() can only be true or false, but we don't want to send any flush when we are not in multifd migration. CC: Fabiano Rosas Is it worth to pick it up for stable-8.1? /mjt

Re: [PATCH v4 2/4] hw/cxl: Use switch statements for read and write of cachemem registers

On Thu, 19 Oct 2023 12:24:48 +0100 Jonathan Cameron wrote: > On Thu, 19 Oct 2023 05:23:04 -0400 > "Michael S. Tsirkin" wrote: > > > On Thu, Oct 19, 2023 at 10:09:24AM +0100, Jonathan Cameron wrote: > > > On Wed, 18 Oct 2023 17:31:42 +0100 > > > Jonathan Cameron wrote: > > > > > > > On W

[PATCH v2 11/11] migration: Rename ram_compressed_pages() to compress_ram_pages()

We are moving to have all functions exported from ram-compress.c to start with compress_. Signed-off-by: Juan Quintela --- migration/ram-compress.h | 2 +- migration/ram-compress.c | 2 +- migration/ram.c | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/migration/r

[PATCH v3] hw/pci: modify pci_setup_iommu() to set PCIIOMMUOps

From: Liu Yi L This patch modifies pci_setup_iommu() to set PCIIOMMUOps instead of setting PCIIOMMUFunc. PCIIOMMUFunc is used to get an address space for a PCI device in vendor specific way. The PCIIOMMUOps still offers this functionality. But using PCIIOMMUOps leaves space to add more iommu rela

Re: [PATCH v4 10/12] tests/qtest/migration: Support more than one QEMU binary

Thomas Huth wrote: > On 18/10/2023 21.27, Fabiano Rosas wrote: >> We have strict rules around migration compatibility between different >> QEMU versions but no test to validate the migration state between >> different binaries. >> Add infrastructure to allow running the migration tests with two >>

Re: [PATCH v4 07/12] tests/qtest/migration: Define a machine for all architectures

Fabiano Rosas wrote: > Stop relying on defaults and select a machine explicitly for every > architecture. > > This is a prerequisite for being able to select machine types for > migration using different QEMU binaries for source and destination. > > Signed-off-by: Fabiano Rosas Reviewed-by: Juan

Re: [PATCH v4 08/12] tests/qtest/migration: Specify the geometry of the bootsector

Fabiano Rosas wrote: > We're about to enable the x86_64 tests to run with the q35 machine, > but that machine does not work with the program we use to dirty the > memory for the tests. > > The issue is that QEMU needs to guess the geometry of the "disk" we > give to it and the guessed geometry doe

Re: [PATCH 11/12] hw/xen: automatically assign device index to block devices

Am 18.10.2023 um 12:52 hat David Woodhouse geschrieben: > > Actually, how does this play together with xen_config_dev_blk()? This > > looks like it tried to implement a very similar thing (which is IF_XEN > > even already existed). > > Ah yes, thanks for spotting that! I hadn't been looking at the

[PATCH v2 05/11] migration: Simplify compress_page_with_multithread()

Move the goto to a while true. Reviewed-by: Lukas Straub Signed-off-by: Juan Quintela --- migration/ram-compress.c | 48 1 file changed, 24 insertions(+), 24 deletions(-) diff --git a/migration/ram-compress.c b/migration/ram-compress.c index ef03d60a6d.

Re: [PATCH v4 09/12] tests/qtest/migration: Set q35 as the default machine for x86_86

Fabiano Rosas wrote: > Change the x86_64 to use the q35 machines in tests from now on. Keep > testing the pc macine on 32bit. > > Signed-off-by: Fabiano Rosas Reviewed-by: Juan Quintela

Re: [PULL 13/38] migration: Non multifd migration don't care about multifd flushes

Michael Tokarev wrote: > 17.10.2023 11:29, Juan Quintela: >> RDMA was having trouble because >> migrate_multifd_flush_after_each_section() can only be true or false, >> but we don't want to send any flush when we are not in multifd >> migration. >> CC: Fabiano Rosas > Fixes: 294e5a4034e81 ("multif

Re: [PATCH 1/5] configure: add qpl meson option

Yuan Liu wrote: > Intel Query Processing Library (QPL) is an open-source library that > supports features of the new Intel In-Memory Analytics Accelerator (IAA) > available on Intel Xeon Sapphire Rapids processors, including > high-throughput compression and decompression. > > add --enable-qpl and

Re: [PATCH v3 00/13] VIRTIO-IOMMU/VFIO: Don't assume 64b IOVA space

On Thu, Oct 19, 2023 at 01:07:41PM +0200, Cédric Le Goater wrote: > On 10/18/23 15:37, Michael S. Tsirkin wrote: > > On Wed, Oct 11, 2023 at 07:52:16PM +0200, Eric Auger wrote: > > > This applies on top of vfio-next: > > > https://github.com/legoater/qemu/, vfio-next branch > > > > virtio things m

[PATCH v2 03/11] migration: Remove save_page_use_compression()

After previous patch, we disable the posiblity that we use compression together with xbzrle. So we can use directly migrate_compress(). Once there, now we don't need the rs parameter, so remove it. Signed-off-by: Juan Quintela --- migration/ram.c | 34 +++--- 1 file

Re: [PATCH v4 11/12] tests/qtest/migration: Allow user to specify a machine type

Fabiano Rosas wrote: > Accept the QTEST_QEMU_MACHINE_TYPE environment variable to take a > machine type to use in the tests. > > The full machine type is recognized (e.g. pc-q35-8.2). Aliases > (e.g. pc) are also allowed and resolve to the latest machine version > for that alias, or, if using two

Re: [PATCH v4 00/12] tests/migration-test: Allow testing older machine types

Fabiano Rosas wrote: > (please ignore v3 which was bogus, but don't miss the discussion in it > about the caveats of this approach: > https://lore.kernel.org/r/87jzrkdne2@suse.de) queued for next pull request.

Re: deadlock when using iothread during backup_clean()

Am 18.10.2023 um 11:42 hat Fiona Ebner geschrieben: > Am 17.10.23 um 16:20 schrieb Kevin Wolf: > > Am 17.10.2023 um 15:37 hat Fiona Ebner geschrieben: > >> Am 17.10.23 um 14:12 schrieb Kevin Wolf: > >>> Am 17.10.2023 um 12:18 hat Fiona Ebner geschrieben: > I ran into similar issues now with mi

Re: Re: [PATCH] virtio-blk: don't start dataplane during the stop of dataplane

On Thu, 19 Oct 2023 at 00:31, wrote: > > On Tue, Oct 17, 2023 at 10:04PM +0800, stefa...@redhat.com wrote: > > > > From: hujian > > > > > > > > During the stop of dataplane for virtio-blk, > > > virtio_bus_cleanup_host_notifier() is be > > > > called to clean up notifier at the end, if polled io

[PATCH v2 06/11] migration: Move busy++ to migrate_with_multithread

And now we can simplify save_compress_page(). Reviewed-by: Lukas Straub Signed-off-by: Juan Quintela --- migration/ram-compress.c | 1 + migration/ram.c | 8 ++-- 2 files changed, 3 insertions(+), 6 deletions(-) diff --git a/migration/ram-compress.c b/migration/ram-compress.c inde

Re: [PATCH v2 02/27] vfio: Introduce base object for VFIOContainer and targetted interface

On 10/19/23 04:29, Duan, Zhenzhong wrote: -Original Message- From: Cédric Le Goater Sent: Wednesday, October 18, 2023 4:04 PM Subject: Re: [PATCH v2 02/27] vfio: Introduce base object for VFIOContainer and targetted interface On 10/18/23 04:41, Duan, Zhenzhong wrote: Hi Cédric, -

Re: [PATCH v4] migration: Allow user to specify available switchover bandwidth

Markus Armbruster wrote: > Peter Xu writes: [..] >>> "unconvergence" isn't a word :) >>> >>> Suggest "like migration not converging, because the automatically >>> detected migration bandwidth is hilariously low for whatever reason." >>> >>> Appreciate the thorough explanation! >> >> Thanks fo

Re: [PULL v2 38/53] hw/cxl: Support 4 HDM decoders at all levels of topology

On Thu, 5 Oct 2023 at 04:45, Michael S. Tsirkin wrote: > > From: Jonathan Cameron > > Support these decoders in CXL host bridges (pxb-cxl), CXL Switch USP > and CXL Type 3 end points. > > Signed-off-by: Jonathan Cameron > > -/* TODO: Support multiple HDM decoders and DPA skip */ > static boo

Re: [PATCH] tests/vm/openbsd: Use the system dtc package

Thomas Huth writes: > We can use the pre-packaged libfdt from the dtc package to avoid > that we have to compile this code each time again and again. > > While we're at it, the "--python=python3" does not seemt to be > necessary anymore, so we can drop it. > > Signed-off-by: Thomas Huth Queue

Re: [PATCH] tests/docker: avoid invalid escape in Python string

Paolo Bonzini writes: > This is an error in Python 3.12; fix it by using a raw string literal. > > Cc: qemu-sta...@nongnu.org > Signed-off-by: Paolo Bonzini Queued to testing/next, thanks. -- Alex Bennée Virtualisation Tech Lead @ Linaro

Re: [PATCH v3] hw/pci: modify pci_setup_iommu() to set PCIIOMMUOps

Hi Cédric, On 10/19/23 13:54, Cédric Le Goater wrote: > From: Liu Yi L > > This patch modifies pci_setup_iommu() to set PCIIOMMUOps > instead of setting PCIIOMMUFunc. PCIIOMMUFunc is used to > get an address space for a PCI device in vendor specific > way. The PCIIOMMUOps still offers this functi

Re: [PATCH v3 00/13] VIRTIO-IOMMU/VFIO: Don't assume 64b IOVA space

On 10/18/23 15:37, Michael S. Tsirkin wrote: On Wed, Oct 11, 2023 at 07:52:16PM +0200, Eric Auger wrote: This applies on top of vfio-next: https://github.com/legoater/qemu/, vfio-next branch virtio things make sense Reviewed-by: Michael S. Tsirkin let me know how you want to merge all this.

Re: [PATCH v1 20/23] xen platform: unplug ahci object

On Thu, 2023-06-22 at 05:40 +, Bernhard Beschow wrote: > Am 20. Juni 2023 17:24:54 UTC schrieb Joel Upham : > > This will unplug the ahci device when the Xen driver calls for an unplug. > > This has been tested to work in linux and Windows guests. > > When q35 is detected, we will remove the ah

Re: [PATCH v2 2/2] tests/tcg: Add -fno-stack-protector

Thomas Huth writes: > On 31/07/2023 11.10, Akihiko Odaki wrote: >> A build of GCC 13.2 will have stack protector enabled by default if it >> was configured with --enable-default-ssp option. For such a compiler, >> it is necessary to explicitly disable stack protector when linking >> without sta

Re: [PATCH] migration: Fix parse_ramblock() on overwritten retvals

On Tue, 17 Oct 2023 at 21:40, Peter Xu wrote: > > It's possible that some errors can be overwritten with success retval later > on, and then ignored. Always capture all errors and report. > > Reported by Coverity 1522861, but actually I spot one more in the same > function. The other one is CID

Re: [RFC PATCH v2 01/78] include/qemu/compiler.h: replace QEMU_FALLTHROUGH with fallthrough

Peter Maydell writes: > On Wed, 18 Oct 2023 at 14:12, Alex Bennée wrote: >> >> >> Manos Pitsidianakis writes: >> >> > On Wed, 18 Oct 2023 13:32, Alex Bennée wrote: >> >>> diff --git a/audio/pwaudio.c b/audio/pwaudio.c >> >>> index 3ce5f6507b..bf26fadb06 100644 >> >>> --- a/audio/pwaudio.c >>

[PATCH v2 1/4] target/loongarch: Add cpu model 'max'

We use cpu la464 for the 'max' cpu. Signed-off-by: Song Gao --- target/loongarch/cpu.c | 7 +++ 1 file changed, 7 insertions(+) diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c index ef1bf89dac..ef6922e812 100644 --- a/target/loongarch/cpu.c +++ b/target/loongarch/cpu.c @@ -474,

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