On Wed, Oct 11, 2023 at 04:58:01PM -0400, Stefan Hajnoczi wrote:
> On Wed, 11 Oct 2023 at 04:48, Daniel P. Berrangé wrote:
> >
> > On Wed, Oct 11, 2023 at 07:35:24AM +0200, Philippe Mathieu-Daudé wrote:
> > > Hi Paolo,
> > >
> > > On 7/9/23 14:59, Paolo Bonzini wrote:
> > > > This allows building
From: Alex Williamson
The below referenced commit renames scanout_width/height to
backing_width/height, but also promotes these fields in various portions
of the egl interface. Meanwhile vfio dmabuf support has never used the
previous scanout fields and is therefore missed in the update. This
r
The following patches are queued for QEMU stable v8.1.2:
https://gitlab.com/qemu-project/qemu/-/commits/staging-8.1
Patch freeze is 2023-12-14, and the release is planned for 2023-14-16:
https://wiki.qemu.org/Planning/8.1
Please respond here or CC qemu-sta...@nongnu.org on any additional pa
From: Fiona Ebner
Commit 59bde21374 ("util/log: do not close and reopen log files when
flags are turned off") prevented switching away from stderr on a
subsequent invocation of qemu_set_log_internal(). This prevented
switching away from stderr with the 'logfile' monitor command as well
as an invo
From: Volker Rümelin
Reset the current sample counter when writing the Channel Sample
Count Register. The Linux ens1370 driver and the AROS sb128
driver expect the current sample counter counts down from sample
count to 0 after a write to the Channel Sample Count Register.
Currently the current s
From: Peter Xu
QEMU will crash if anyone tries to set tls-authz (which is a type
StrOrNull) with 'null' value. Fix it in the easy way by converting it to
qstring just like the other two tls parameters.
Cc: qemu-sta...@nongnu.org # v4.0+
Fixes: d2f1d29b95 ("migration: add support for a "tls-auth
The system test shutdown uses the 'loongarch_virt_pm' region.
We can use the write AcpiFadtData.sleep_clt register to realize the shutdown.
Signed-off-by: Song Gao
---
hw/loongarch/virt.c | 48 +
tests/tcg/loongarch64/system/boot.S | 7 +++--
2 files
12.10.2023 10:16, Michael Tokarev:
..
I was quite busy the last few days, - so I had to move the initially planned
release by 2 days, - freeze from Oct-10 to Oct-12 (today), release from
Oct-12 to Oct-14. Please excuse me for this delay.
Sigh. That's a fiasco, bro :)) Being busy does not help
The file is obviously related to the raspberrypi machine, so
it should reside in hw/arm/ instead of hw/misc/. And while we're
at it, also adjust the wildcard in MAINTAINERS so that it covers
this file, too.
Signed-off-by: Thomas Huth
---
MAINTAINERS| 2 +-
inc
On 11/10/2023 20.46, Fabiano Rosas wrote:
We've found the source of flakiness in this test, so re-enable it.
Reviewed-by: Juan Quintela
Signed-off-by: Fabiano Rosas
---
tests/qtest/migration-test.c | 10 ++
1 file changed, 2 insertions(+), 8 deletions(-)
diff --git a/tests/qtest/mi
On 06/10/2023 14.39, Fabiano Rosas wrote:
We're adding support for using more than one QEMU binary in
tests. Modify qtest_get_machines() to take an environment variable
that contains the QEMU binary path.
Since the function keeps a cache of the machines list in the form of a
static variable, ref
Thomas Huth writes:
> The file is obviously related to the raspberrypi machine, so
> it should reside in hw/arm/ instead of hw/misc/. And while we're
> at it, also adjust the wildcard in MAINTAINERS so that it covers
> this file, too.
>
> Signed-off-by: Thomas Huth
Reviewed-by: Alex Bennée
On 12/10/23 09:34, Thomas Huth wrote:
The file is obviously related to the raspberrypi machine, so
it should reside in hw/arm/ instead of hw/misc/.
Not quite. These are the VideoCore DSP definitions. Firmware
running on SoC including a VC can use this syscall-like interface.
FWIW there are a p
On 12/10/23 09:23, Song Gao wrote:
The system test shutdown uses the 'loongarch_virt_pm' region.
We can use the write AcpiFadtData.sleep_clt register to realize the shutdown.
Signed-off-by: Song Gao
---
hw/loongarch/virt.c | 48 +
tests/tcg/loongar
QEMU has validations to make sure that a VM is not started with more memory
(static and hotpluggable memory) than what the guest processor can address
directly with its addressing bits. This change adds a test to make sure QEMU
fails to start with a specific error message when an attempt is made to
On 2023/10/3 20:49, Rob Bradford wrote:
Check the PMU available bitmask when checking if a counter is valid
rather than comparing the index against the number of PMUs.
Signed-off-by: Rob Bradford
---
target/riscv/csr.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git
On 2023/10/11 22:45, Rob Bradford wrote:
During the FDT generation use the existing mask containing the enabled
counters rather then generating a new one. Using the existing mask will
support the use of discontinuous counters.
Signed-off-by: Rob Bradford
---
hw/riscv/virt.c| 2 +-
targ
6 out of 7 calls to get_arm_cp_reginfo() are checked
Signed-off-by: Sergey Mironov
---
target/arm/helper.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 74fbb6e1d7..cffbbaf571 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -198
On 2023/10/11 22:45, Rob Bradford wrote:
Add 32-bit version of mask generating macro and use it in the RISC-V PMU
code.
CC Richard
Signed-off-by: Rob Bradford
---
include/qemu/bitops.h | 3 +++
target/riscv/pmu.c| 2 --
2 files changed, 3 insertions(+), 2 deletions(-)
diff --git a/i
Hi Sergey,
On 12/10/23 10:50, Sergey Mironov wrote:
6 out of 7 calls to get_arm_cp_reginfo() are checked
Signed-off-by: Sergey Mironov
---
target/arm/helper.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 74fbb6e1d7..cffbbaf571 100644
--
6 out of 7 calls to get_arm_cp_reginfo() are checked
Signed-off-by: Sergey Mironov
---
target/arm/helper.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 74fbb6e1d7..cffbbaf571 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -198
It was my mistake :)
От: Philippe Mathieu-Daudé
Отправлено: 12 октября 2023 г. 11:52:58
Кому: Миронов Сергей Владимирович; qemu-devel@nongnu.org;
peter.mayd...@linaro.org; qemu-...@nongnu.org
Тема: Re: [PATCH 100742/100742] target/arm: Adding a check for the resu
On Wed, 11 Oct 2023 17:37:11 +
Vikram Sethi wrote:
> Hi Jonathan,
>
> > -Original Message-
> > From: Jonathan Cameron
> > Sent: Monday, October 9, 2023 7:27 AM
> > To: Ankit Agrawal
> > Cc: Jason Gunthorpe ; alex.william...@redhat.com;
> > c...@redhat.com; shannon.zha...@gmail.com;
On 2023/10/11 22:45, Rob Bradford wrote:
Using a mask instead of the number of PMU devices supports the accurate
emulation of platforms that have a discontinuous set of PMU counters.
Generate a warning if the old property changed from the default but
still go ahead and use it to generate the ma
On Thu, 12 Oct 2023 10:10:36 +0530
Ani Sinha wrote:
> > On 11-Oct-2023, at 10:01 PM, Jonathan Cameron
> > wrote:
> >
> > On Wed, 11 Oct 2023 16:23:35 +0530
> > Ani Sinha wrote:
> >
> >> pc_get_device_memory_range() finds the device memory size by calculating
> >> the
> >> difference betwe
On 2023/10/11 22:45, Rob Bradford wrote:
This has been replaced by a "pmu-mask" property that provides much more
flexibility.
Signed-off-by: Rob Bradford
---
docs/about/deprecated.rst | 10 ++
1 file changed, 10 insertions(+)
diff --git a/docs/about/deprecated.rst b/docs/about/dep
On Wed, Oct 11, 2023 at 07:09:19PM +0200, Cédric Le Goater wrote:
> On 10/10/23 15:46, Marc-André Lureau wrote:
> > Hi
> >
> > On Tue, Oct 10, 2023 at 4:49 PM Cédric Le Goater wrote:
> > >
> > > Hello,
> > >
> > > On 10/9/23 08:32, marcandre.lur...@redhat.com wrote:
> > > > From: Marc-André Lur
Hi Gavin,
> From: Gavin Shan
> Sent: Thursday, October 12, 2023 1:07 AM
> To: Salil Mehta ; qemu-devel@nongnu.org; qemu-
> a...@nongnu.org
> Cc: m...@kernel.org; jean-phili...@linaro.org; Jonathan Cameron
> ; lpieral...@kernel.org;
> peter.mayd...@linaro.org; richard.hender...@linaro.org;
> imamm
> From: Gavin Shan
> Sent: Thursday, October 12, 2023 1:18 AM
> To: Salil Mehta ; Salil Mehta
> ; qemu-devel@nongnu.org; qemu-...@nongnu.org
> Cc: m...@kernel.org; jean-phili...@linaro.org; Jonathan Cameron
> ; lpieral...@kernel.org;
> peter.mayd...@linaro.org; richard.hender...@linaro.org;
> imam
On 2023-10-10 at 02:05:39 -0400, Xiaoyao Li wrote:
> When explicitly booting a multiple vcpus vm with "-cpu +ht", it gets
> warning of
>
> warning: host doesn't support requested feature: CPUID.01H:EDX.ht [bit 28]
>
> Make CPUID_HT as supported unconditionally can resolve the warning.
> However
On Wed, Oct 11, 2023 at 01:47:21PM +0200, Björn Töpel wrote:
> From: Björn Töpel
>
> Qemu fw_cfg support was missing for RISC-V, which made it hard to do
> proper vmcore dumps from qemu.
>
> Add the missing RISC-V arch-defines.
>
> You can now do vmcore dumps from qemu. Add "-device vmcoreinfo"
I haven't really been working on LoongArch for some time now,
so let's remove myself from this entry.
Signed-off-by: Xiaojuan Yang
---
MAINTAINERS | 2 --
1 file changed, 2 deletions(-)
diff --git a/MAINTAINERS b/MAINTAINERS
index c3cc12dc29..5c386f1f37 100644
--- a/MAINTAINERS
+++ b/MAINTAINER
Juan Quintela writes:
> Set the 'block_incremental' migration parameter to 'true' instead.
>
> Reviewed-by: Thomas Huth
> Signed-off-by: Juan Quintela
> ---
> docs/about/deprecated.rst | 7 +++
> qapi/migration.json | 12 ++--
> migration/migration.c | 6 ++
> 3 fil
Signed-off-by: Rajnesh Kanwal
Reviewed-by: Alistair Francis
---
target/riscv/csr.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 4b4ab56c40..d99d954ff3 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -1525,7 +1525,7
This series adds M and HS-mode virtual interrupt and IRQ filtering support.
This allows inserting virtual interrupts from M/HS-mode into S/VS-mode
using mvien/hvien and mvip/hvip csrs. IRQ filtering is a use case of
this change, i-e M-mode can stop delegating an interrupt to S-mode and
instead enab
This is to allow virtual interrupts to be inserted into S and VS
modes. Given virtual interrupts will be maintained in separate
mvip and hvip CSRs, riscv_cpu_update_mip will no longer be in the
path and interrupts need to be triggered for these cases from
rmw_hvip64 and rmw_mvip64 functions.
Signe
Juan Quintela writes:
> It is obsolete. It is better to use driver-mirror with NBD instead.
drive-mirror
Several more below.
>
> CC: Kevin Wolf
> CC: Eric Blake
> CC: Stefan Hajnoczi
> CC: Hanna Czenczek
>
> Signed-off-by: Juan Quintela
> ---
> docs/about/deprecated.rst | 10 ++
This change adds support for inserting virtual interrupts from HS-mode
into VS-mode using hvien and hvip csrs. This also allows for IRQ filtering
from HS-mode.
Also, the spec doesn't mandate the interrupt to be actually supported
in hardware. Which allows HS-mode to assert virtual interrupts to VS
With H-Ext supported, VS bits are all hardwired to one in MIDELEG
denoting always delegated interrupts. This is being done in rmw_mideleg
but given mideleg is used in other places when routing interrupts
this change initializes it in riscv_cpu_realize to be on the safe side.
Signed-off-by: Rajnesh
This change adds support for inserting virtual interrupts from M-mode
into S-mode using mvien and mvip csrs. IRQ filtering is a use case of
this change, i-e M-mode can stop delegating an interrupt to S-mode and
instead enable it in MIE and receive those interrupts in M-mode and then
selectively inj
RISCV_EXCP_SEMIHOST is set to 0x10, which can be a local interrupt id
as well. This change moves RISCV_EXCP_SEMIHOST to switch case so that
async flag check is performed before invoking semihosting logic.
Signed-off-by: Rajnesh Kanwal
Reviewed-by: Alistair Francis
---
target/riscv/cpu_helper.c
Juan Quintela writes:
> Signed-off-by: Juan Quintela
> Acked-by: Peter Xu
> ---
> docs/about/deprecated.rst | 8 +++
> qapi/migration.json | 102 --
> migration/options.c | 13 +
> 3 files changed, 86 insertions(+), 37 deletions(-)
>
> dif
On 10/12/23 11:18, Gerd Hoffmann wrote:
On Wed, Oct 11, 2023 at 07:09:19PM +0200, Cédric Le Goater wrote:
On 10/10/23 15:46, Marc-André Lureau wrote:
Hi
On Tue, Oct 10, 2023 at 4:49 PM Cédric Le Goater wrote:
Hello,
On 10/9/23 08:32, marcandre.lur...@redhat.com wrote:
From: Marc-André Lur
On 9/7/23 09:25, Nicholas Piggin wrote:
On Wed Sep 6, 2023 at 2:33 PM AEST, Harsh Prateek Bora wrote:
Once the L1 has created a nested guest and its associated VCPU, it can
request for the execution of nested guest by setting its initial state
which can be done either using the h_guest_set_st
On 9/7/23 09:26, Nicholas Piggin wrote:
On Wed Sep 6, 2023 at 2:33 PM AEST, Harsh Prateek Bora wrote:
Adding initial documentation about Nested PAPR API to describe the set
of APIs and its usage. Also talks about the Guest State Buffer elements
and it's format which is used between L0/L1 to c
From: Björn Töpel
Qemu fw_cfg support was missing for RISC-V, which made it hard to do
proper vmcore dumps from qemu.
Add the missing RISC-V arch-defines.
You can now do vmcore dumps from qemu. Add "-device vmcoreinfo" to the
qemu command-line. From the qemu monitor:
(qemu) dump-guest-memory
This is intended to be a semantic revert of commit 9b09503752
("migration: run setup callbacks out of big lock"). There have been so
many changes since that commit (e.g. a new setup callback
dirty_bitmap_save_setup() that also needs to be adapted now), it's
easier to do the revert manually.
For sn
At the end of the first if we see 'vc->gfx.surface = NULL;',
further checking of it is pointless. In the second if, ectx is taken.
Found by Linux Verification Center (linuxtesting.org) with SVACE.
Co-developed-by: Linux Verification Center
Signed-off-by: Sergey Mironov
---
ui/gtk.c | 2 +-
1 f
Add new XSCOM registers introduced in PHB5.
Apply bit-masks within xscom-write methods.
Signed-off-by: Saif Abrar
---
hw/pci-host/pnv_phb4.c | 29 +++--
hw/pci-host/pnv_phb4_pec.c | 33 -
include/hw/pci-host/pnv_phb4.h |
Currently, nested_ptcr is being used by existing nested-hv API to store
nested guest related info. This need to be organised to extend support
for the nested PAPR API which would need to store additional info related
to nested guests in next series of patches.
Signed-off-by: Michael Neuling
Signe
Markus Armbruster wrote:
> Juan Quintela writes:
>
>> Set the 'block_incremental' migration parameter to 'true' instead.
>>
>> # @blk: do block migration (full disk copy)
>> #
>> -# @inc: incremental disk copy migration
>> +# @inc: incremental disk copy migration. This option is deprecated.
>>
Introduce the nested PAPR hcalls:
- H_GUEST_GET_STATE which is used to get state of a nested guest or
a guest VCPU. The value field for each element in the request is
ignored and on success, will be updated to reflect current state.
- H_GUEST_SET_STATE which is used to modify th
Most of the nested code has already been moved to spapr_nested.c
This logic inside spapr_get_pate is related to nested guests and
better suited for spapr_nested.c, hence moving there.
Signed-off-by: Harsh Prateek Bora
---
hw/ppc/spapr.c| 28 ++--
hw/ppc/sp
Introduce the nested PAPR hcall H_GUEST_CREATE_VCPU which is used to
create and initialize the specified VCPU resource for the previously
created guest. Each guest can have multiple VCPUs upto max 2048.
All VCPUs for a guest gets deallocated on guest delete.
Signed-off-by: Michael Neuling
Signed-
For nested PAPR API, we use SpaprMachineStateNestedGuest struct to store
partition table info, use the same in spapr_get_pate_nested() as well.
Signed-off-by: Michael Neuling
Signed-off-by: Harsh Prateek Bora
---
hw/ppc/spapr.c| 5 +---
hw/ppc/spapr_nested.c | 49 ++
Introduce the nested PAPR hcalls:
- H_GUEST_CREATE which is used to create and allocate resources for
nested guest being created.
- H_GUEST_DELETE which is used to delete and deallocate resources
for the nested guest being deleted. It also supports deleting all nested
guests at once using a
Nested PAPR API provides a standard Guest State Buffer (GSB) format
with unique IDs for each guest state element for which get/set state is
supported by the API. Some of the elements are read-only and/or guest-wide.
Introducing helper routines for state exchange of each of the nested guest
state el
Adding initial documentation about Nested PAPR API to describe the set
of APIs and its usage. Also talks about the Guest State Buffer elements
and it's format which is used between L0/L1 to communicate L2 state.
Signed-off-by: Michael Neuling
Signed-off-by: Harsh Prateek Bora
---
docs/devel/nes
Introduce the nested PAPR hcalls:
- H_GUEST_GET_CAPABILITIES which is used to query the capabilities
of the API and the L2 guests it provides.
- H_GUEST_SET_CAPABILITIES which is used to set the Guest API
capabilities that the Host Partition supports and may use.
Signed-off-by: Michael Neu
Renaming nested host state variable name to reflect the nested-hv API
being used. For nested PAPR API, similar convention shall be used in
upcoming patch which helps distinguishing them from each other.
Signed-off-by: Harsh Prateek Bora
---
hw/ppc/spapr_nested.c | 18 +-
Introduce a SPAPR capability cap-nested-papr which provides a nested
HV facility to the guest. This is similar to cap-nested-hv, but uses
a different (incompatible) API and so they are mutually exclusive.
This new API is to enable support for KVM on PowerVM and recently the
Linux kernel side patche
There is an existing Nested-HV API to enable nested guests on powernv
machines. However, that is not supported on pseries/PowerVM LPARs.
This patch series implements required hcall interfaces to enable nested
guests with KVM on PowerVM.
Unlike Nested-HV, with this API, entire L2 state is retained b
spapr_exit_nested gets triggered on a nested guest exit and currently
being used only for nested-hv API. Isolating code flows based on API
helps extending it to be used with nested PAPR API as well.
Signed-off-by: Harsh Prateek Bora
---
hw/ppc/spapr_nested.c | 15 ---
1 file changed,
The H_GUEST_RUN_VCPU hcall is used to start execution of a Guest VCPU.
The Hypervisor will update the state of the Guest VCPU based on the
input buffer, restore the saved Guest VCPU state, and start its execution.
The Guest VCPU can stop running for numerous reasons including HCALLs,
hypervisor ex
Since cap-nested-hv and cap-nested-papr are mutually exclusive, now it
makes sense to register api specfic hcalls only when respective
capability is enabled, hence this change.
Signed-off-by: Harsh Prateek Bora
---
hw/ppc/spapr_caps.c | 1 +
hw/ppc/spapr_hcall.c | 2 --
2 files changed, 1 inser
Hi Martin, Paolo, Markus, Marc-André,
With the following changes:
-- >8 --
diff --git a/hw/ppc/prep.c b/hw/ppc/prep.c
index 137276bcb9..291495f798 100644
--- a/hw/ppc/prep.c
+++ b/hw/ppc/prep.c
@@ -245,6 +245,7 @@ static void ibm_40p_init(MachineState *machine)
uint32_t kernel_base = 0, ini
On 12/10/2023 10.22, Philippe Mathieu-Daudé wrote:
On 12/10/23 09:34, Thomas Huth wrote:
The file is obviously related to the raspberrypi machine, so
it should reside in hw/arm/ instead of hw/misc/.
Not quite. These are the VideoCore DSP definitions. Firmware
running on SoC including a VC can
Nina Schoetterl-Glausch writes:
> From: Pierre Morel
>
> S390 adds two new SMP levels, drawers and books to the CPU
> topology.
> S390 CPUs have specific topology features like dedication and
> entitlement. These indicate to the guest information on host
> vCPU scheduling and help the guest make
Am 12.10.2023 um 12:01 hat Markus Armbruster geschrieben:
> Juan Quintela writes:
>
> > It is obsolete. It is better to use driver-mirror with NBD instead.
>
> drive-mirror
>
> Several more below.
Actually, blockdev-mirror, please. We don't want to move people from the
oldest way to the next
Nina Schoetterl-Glausch writes:
> From: Pierre Morel
>
> On interception of STSI(15.1.x) the System Information Block
> (SYSIB) is built from the list of pre-ordered topology entries.
>
> Signed-off-by: Pierre Morel
> Reviewed-by: Nina Schoetterl-Glausch
> Co-developed-by: Nina Schoetterl-Glau
We already list system/qtest.c in the qtest section, so the
corresponding header file should be listed here, too.
Signed-off-by: Thomas Huth
---
MAINTAINERS | 1 +
1 file changed, 1 insertion(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index f90c9d814c..bf8ce0e6c7 100644
--- a/MAINTAINERS
+++ b/M
On 12/10/23 13:14, Thomas Huth wrote:
We already list system/qtest.c in the qtest section, so the
corresponding header file should be listed here, too.
Signed-off-by: Thomas Huth
---
MAINTAINERS | 1 +
1 file changed, 1 insertion(+)
Reviewed-by: Philippe Mathieu-Daudé
Nina Schoetterl-Glausch writes:
> From: Pierre Morel
>
> The modification of the CPU attributes are done through a monitor
> command.
>
> It allows to move the core inside the topology tree to optimize
> the cache usage in the case the host's hypervisor previously
> moved the CPU.
>
> The same c
Nina Schoetterl-Glausch writes:
> From: Pierre Morel
>
> S390x provides two more topology attributes, entitlement and dedication.
>
> Let's add these CPU attributes to the QAPI command query-cpu-fast.
>
> Signed-off-by: Pierre Morel
> Reviewed-by: Nina Schoetterl-Glausch
> Co-developed-by: Nin
Philippe Mathieu-Daudé writes:
> Hi Srivatsa,
>
> On 11/10/23 18:52, Srivatsa Vaddagiri wrote:
>> Add a new accelerator, gunyah, with basic functionality of creating a
>> VM. Subsequent patches will add support for other functions required to
>> run a VM.
>> Signed-off-by: Srivatsa Vaddagiri
>
In the subject: QAPI event
Nina Schoetterl-Glausch writes:
> From: Pierre Morel
>
> When the guest asks to change the polarization this change
> is forwarded to the upper layer using QAPI.
> The upper layer is supposed to take according decisions concerning
> CPU provisioning.
>
> Signed-off-by
Nina Schoetterl-Glausch writes:
> From: Pierre Morel
>
> The query-s390x-cpu-polarization qmp command returns the current
> CPU polarization of the machine.
>
> Signed-off-by: Pierre Morel
> Reviewed-by: Thomas Huth
> Reviewed-by: Nina Schoetterl-Glausch
> Co-developed-by: Nina Schoetterl-Gla
Markus Armbruster wrote:
> Juan Quintela writes:
>
>> It is obsolete. It is better to use driver-mirror with NBD instead.
>
> drive-mirror
>
> Several more below.
Done.
>> +# Features:
>> +#
>> +# @deprecated: @disk migration is deprecated. Use driver-mirror
>> +# with NBD instead.
>> +#
On Tue, 3 Oct 2023 16:42:37 -0400
"Michael S. Tsirkin" wrote:
> On Tue, Sep 19, 2023 at 10:34:32AM +0100, Jonathan Cameron wrote:
> > Establishing that only register accesses of size 4 and 8 can occur
> > using these functions requires looking at their callers. Make it
> > easier to see that by u
Markus Armbruster wrote:
> Juan Quintela writes:
>
>> -# @deprecated: @disk migration is deprecated. Use driver-mirror
>> -# with NBD instead.
>> +# @deprecated: @disk migration is deprecated. Use driver-mirror with
>> +# NBD instead. @compression is unreliable and untested. It is
>> +
On 11/10/2023 16.53, Michael Tokarev wrote:
11.10.2023 17:42, Thomas Huth wrote:
This job is failing since weeks. Let's mark it as manual until
it gets fixed.
Signed-off-by: Thomas Huth
I was about to sent something like this about a month ago, but
got distracted.
Acked-by: Michael Tokarev
Thomas Huth writes:
> Rename some variables to avoid compiler warnings when compiling
> with -Wshadow=local.
>
> Signed-off-by: Thomas Huth
> ---
> v2: Renamed the variable to something more unique
>
> contrib/vhost-user-gpu/vugpu.h | 8
> contrib/vhost-user-gpu/vhost-user-gp
When multiple QOM types are registered in the same file,
it is simpler to use the the DEFINE_TYPES() macro. In
particular because type array declared with such macro
are easier to review.
Remove a pointless structure declaration in "designware.h".
Signed-off-by: Philippe Mathieu-Daudé
---
inclu
As mentioned in previous commit, the PCI root function is
irrelevant for the ViewPorts. Move the fields to the host
bridge state.
This is a migration compatibility break for the machines
using the i.MX7 SoC (currently the mcimx7d-sabre machine).
Signed-off-by: Philippe Mathieu-Daudé
---
include
designware_pcie_root_realize() uses get_system_memory()
as the "host side memory region", as opposed to the "PCI
side" one. Introduce the 'host_mem' variable for clarity.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/pci-host/designware.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
Hi,
While trying this PCI host bridge in a hegerogeneous setup
I noticed few discrepancies due to the fact that host bridge
pieces were managed by the root function.
This series move these pieces (ViewPort and MSI regs) to the
host bridge side where they belong. Unfortunately this is
a migration
The PCI root function is irrelevant for the ViewPort; only
a reference to the host bridge is required. Since we can
directly access the PCI bus, remove the pci_get_bus() call.
Signed-off-by: Philippe Mathieu-Daudé
---
include/hw/pci-host/designware.h | 2 +-
hw/pci-host/designware.c | 7
There is always an unique root function for the host bridge
controller. We create this function when the controller is
realized, in designware_pcie_host_realize().
No need to call qdev_get_parent_bus() each time the root function
want to resolve its host part. Hoist a pointer in its state. Set
the
The MSI registers belong the the host bridge. Move the
DesignwarePCIEMSI field to the host bridge state.
This is a migration compatibility break for the machines
using the i.MX7 SoC (currently the mcimx7d-sabre machine).
Signed-off-by: Philippe Mathieu-Daudé
---
include/hw/pci-host/designware.h
There are no root function properties exposed by the host
bridge, so using a 2-step QOM creation isn't really useful.
Simplify by creating the root function when the host bridge
is realized.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/pci-host/designware.c | 15 ---
1 file changed,
ViewPorts are managed by the host bridge part, so create them
when the host bridge is realized. The host bridge become the
owner of the memory regions.
The PCI root function realize() method now only contains PCI
specific code.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/pci-host/designware.c
* Philippe Mathieu-Daud? [2023-10-12 06:30:24]:
> Hi Srivatsa,
>
> (+Markus/Peter for QOM fu)
>
> On 11/10/23 18:52, Srivatsa Vaddagiri wrote:
> > Avoid dereferencing a NULL pointer that its_class_name() could return.
>
> While your patch is correct, there is some code smell
> around its_class
* Alex Benn?e [2023-10-12 12:32:34]:
> >> create mode 100644 include/sysemu/gunyah_int.h
> >
> > Can we move gunyah_int.h to accel/gunyah/?
>
> If it's all internal to gunyah itself you could rename it to internal.h
> (although we do have various forms of foo-internal.h across the code
> base)
* Philippe Mathieu-Daud? [2023-10-12 06:43:38]:
> > -void *gunyah_cpu_thread_fn(void *arg)
> > -{
> > -CPUState *cpu = arg;
> > -
> > -do {
> > -/* Do nothing */
> > -} while (!cpu->unplug || cpu_can_run(cpu));
> > -
> > -return NULL;
> > -}
>
> This diff could be nicer i
* Philippe Mathieu-Daud? [2023-10-12 06:52:04]:
> > +Limitations
> > +---
> > +
> > +Below features are not yet supported.
> > +
> > +* virtio-pci (support for which in Qemu seems to rely heavily on KVM, which
> > + needs to be made multi-hypervisor friendly).
>
> Is QUIC interested in
On Thu, 2023-10-12 at 17:05 +0800, LIU Zhiwei wrote:
>
>
>
>
> On 2023/10/11 22:45, Rob Bradford wrote:
>
>
> >
> > Using a mask instead of the number of PMU devices supports the
> > accurate
> > emulation of platforms that have a discontinuous set of PMU
> > counters.
> >
> > Generat
On 10/12/23 12:48, Saif Abrar wrote:
Add new XSCOM registers introduced in PHB5.
Apply bit-masks within xscom-write methods.
Signed-off-by: Saif Abrar
I didn't check the masks, the rest looks correct.
Reviewed-by: Cédric Le Goater
Thanks,
C.
---
hw/pci-host/pnv_phb4.c |
This series wraps Dave Jiang's v4 with tests as per v2.
The kernel code using this is now at v10 and reflects the changes made here.
https://lore.kernel.org/linux-cxl/33155160-b627-4d70-b7f7-0fba16218...@intel.com/T/#t
The discussions around the QEMU patches resulted in significant fixes
to the k
Addition of QTG in following patch requires an update to the test
data.
Signed-off-by: Jonathan Cameron
Reviewed-by: Fan Ni
Reviewed-by: Dave Jiang
---
v5 : No change
tests/qtest/bios-tables-test-allowed-diff.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/tests/qtest/bios-tables-test-a
From: Dave Jiang
Add a simple _DSM call support for the ACPI0017 device to return fake QTG
ID values of 0 and 1 in all cases. This for _DSM plumbing testing from the OS.
Following edited for readability
Device (CXLM)
{
Name (_HID, "ACPI0017") // _HID: Hardware ID
...
Method (_DSM, 4, S
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