[PATCH v3 09/13] migration/rdma: Remove qemu_ prefix from exported functions

Functions are long enough even without this. Reviewed-by: Peter Xu Signed-off-by: Juan Quintela --- migration/rdma.h | 12 ++-- migration/ram.c| 14 +++--- migration/rdma.c | 40 +++- migration/trace-events | 28 +++

[PATCH v3 13/13] migration/rdma: Remove all "ret" variables that are used only once

Change code that is: int ret; ... ret = foo(); if (ret[ < 0]?) { to: if (foo()[ < 0]) { Signed-off-by: Juan Quintela --- migration/rdma.c | 29 - 1 file changed, 8 insertions(+), 21 deletions(-) diff --git a/migration/rdma.c b/migration/rdma.c index a43527a83c..c

[PATCH v3 02/13] migration/rdma: Unfold ram_control_before_iterate()

Once there: - Remove unused data parameter - unfold it in its callers. - change all callers to call qemu_rdma_registration_start() - We need to call QIO_CHANNEL_RDMA() after we check for migrate_rdma() Reviewed-by: Peter Xu Signed-off-by: Juan Quintela -- initilazize rioc after checknig that r

[PATCH v3 07/13] qemu-file: Remove QEMUFileHooks

The only user was rdma, and its use is gone. Reviewed-by: Peter Xu Signed-off-by: Juan Quintela --- migration/qemu-file.h | 4 migration/qemu-file.c | 6 -- migration/rdma.c | 9 - 3 files changed, 19 deletions(-) diff --git a/migration/qemu-file.h b/migration/qemu-file.h

[PATCH 0/1] migration: Fix non-multifd migration

Fix sending multifd sync packets when not multifd is seleceted. Basically we were using: if (migrate_multifd_flush_after_each_iteration()) { ...} and if (!migrate_multifd_flush_after_each_iteration()) { ...} But that is not enough for non multifd migration, so changed to also check first if mi

[PATCH 1/1] migration: Non multifd migration don't care about multifd flushes

RDMA was having trouble because migrate_multifd_flush_after_each_section() can only be true or false, but we don't want to send any flush when we are not in multifd migration. CC: Fabiano Rosas Signed-off-by: Juan Quintela --- migration/ram.c | 14 -- 1 file changed, 8 insertions(+)

Re: [PULL 50/51] subprojects: add wrap file for libblkio

On Wed, 11 Oct 2023 at 04:48, Daniel P. Berrangé wrote: > > On Wed, Oct 11, 2023 at 07:35:24AM +0200, Philippe Mathieu-Daudé wrote: > > Hi Paolo, > > > > On 7/9/23 14:59, Paolo Bonzini wrote: > > > This allows building libblkio at the same time as QEMU, if QEMU is > > > configured with --enable-bl

Re: [PATCH] memory: initialize 'fv' in MemoryRegionCache to make Coverity happy

On Mon, 9 Oct 2023 at 06:44, Ilya Maximets wrote: > > Coverity scan reports multiple false-positive "defects" for the > following series of actions in virtio.c: > > MemoryRegionCache indirect_desc_cache; > address_space_cache_init_empty(&indirect_desc_cache); > address_space_cache_destroy(&i

[PATCH v3 3/4] migration: Deprecate block migration

It is obsolete. It is better to use driver-mirror with NBD instead. CC: Kevin Wolf CC: Eric Blake CC: Stefan Hajnoczi CC: Hanna Czenczek Signed-off-by: Juan Quintela --- docs/about/deprecated.rst | 10 ++ qapi/migration.json | 30 +- migration/bloc

[PATCH v3 4/4] migration: Deprecate old compression method

Signed-off-by: Juan Quintela Acked-by: Peter Xu --- docs/about/deprecated.rst | 8 +++ qapi/migration.json | 102 -- migration/options.c | 13 + 3 files changed, 86 insertions(+), 37 deletions(-) diff --git a/docs/about/deprecated.rst b/doc

[PATCH v3 2/4] migration: migrate 'blk' command option is deprecated.

Set the 'block' migration capability to 'true' instead. Signed-off-by: Juan Quintela Reviewed-by: Thomas Huth --- docs/about/deprecated.rst | 7 +++ qapi/migration.json | 10 +++--- migration/migration.c | 5 + 3 files changed, 19 insertions(+), 3 deletions(-) diff --gi

[PATCH v3 1/4] migration: migrate 'inc' command option is deprecated.

Set the 'block_incremental' migration parameter to 'true' instead. Reviewed-by: Thomas Huth Signed-off-by: Juan Quintela --- docs/about/deprecated.rst | 7 +++ qapi/migration.json | 12 ++-- migration/migration.c | 6 ++ 3 files changed, 23 insertions(+), 2 deletions

[PULL v2 00/12] Trivial patches for 2023-10-11

The following changes since commit 0ad0d9dcd16f2ea816a413008ac5191ebef45c95: Merge tag 'firmware/seabios-20231010-pull-request' of https://gitlab.com/kraxel/qemu into staging (2023-10-10 10:22:16 -0400) are available in the Git repository at: https://gitlab.com/mjt0k/qemu.git tags/pull-triv

Re: [PATCH v7 00/15] iotests: use vm.cmd()

On Fri, Oct 6, 2023 at 11:41 AM Vladimir Sementsov-Ogievskiy wrote: > > Hi all! > > Let's get rid of pattern > > result = self.vm.qmp(...) > self.assert_qmp(result, 'return', {}) > > And switch to just > > self.vm.cmd(...) > > v7: add r-bs and small wording/grammar fixes by Eric > 05

Re: [PATCH V5 8/9] physmem: Add helper function to destroy CPU AddressSpace

Hi Salil, On 10/12/23 05:43, Salil Mehta wrote: Virtual CPU Hot-unplug leads to unrealization of a CPU object. This also involves destruction of the CPU AddressSpace. Add common function to help destroy the CPU AddressSpace. Signed-off-by: Salil Mehta Tested-by: Vishnu Pajjuri --- include/e

Re: [PATCH V5 8/9] physmem: Add helper function to destroy CPU AddressSpace

Hi Gavin, On 12/10/2023 00:31, Gavin Shan wrote: Hi Salil, On 10/12/23 05:43, Salil Mehta wrote: Virtual CPU Hot-unplug leads to unrealization of a CPU object. This also involves destruction of the CPU AddressSpace. Add common function to help destroy the CPU AddressSpace. Signed-off-by: Sali

Re: [PATCH V5 9/9] gdbstub: Add helper function to unregister GDB register space

Hi Salil, On 10/12/23 05:43, Salil Mehta wrote: Add common function to help unregister the GDB Register Space. This shall be done in context to the CPU unrealization. Signed-off-by: Salil Mehta Tested-by: Vishnu Pajjuri --- gdbstub/gdbstub.c | 15 +++ include/exec/gdbstub.

Re: [PATCH] riscv, qemu_fw_cfg: Add support for RISC-V architecture

On Wed, Oct 11, 2023 at 11:34 PM Björn Töpel wrote: > > From: Björn Töpel > > Qemu fw_cfg support was missing for RISC-V, which made it hard to do > proper vmcore dumps from qemu. > > Add the missing RISC-V arch-defines. > > You can now do vmcore dumps from qemu. Add "-device vmcoreinfo" to the >

Re: [PATCH V5 8/9] physmem: Add helper function to destroy CPU AddressSpace

Hi Salil, On 10/12/23 10:04, Salil Mehta wrote: On 12/10/2023 00:31, Gavin Shan wrote: On 10/12/23 05:43, Salil Mehta wrote: [...] +void cpu_address_space_destroy(CPUState *cpu, int asidx) +{ +    CPUAddressSpace *cpuas; + +    assert(asidx < cpu->num_ases); +    assert(asidx == 0 || !kvm_e

Re: [PATCH 1/1] migration: Non multifd migration don't care about multifd flushes

On 12/10/2023 04:55, Juan Quintela wrote: > RDMA was having trouble because > migrate_multifd_flush_after_each_section() can only be true or false, > but we don't want to send any flush when we are not in multifd > migration. > > CC: Fabiano Rosas Fixes: 294e5a4034e81b3d8db03b4e0f691386f20d6ed3

RE: [PATCH] vfio/pci: Remove vfio_detach_device from vfio_realize error path

>-Original Message- >From: Eric Auger >Sent: Thursday, October 12, 2023 4:10 AM >To: eric.auger@gmail.com; eric.au...@redhat.com; qemu- >de...@nongnu.org; alex.william...@redhat.com; c...@redhat.com; Duan, >Zhenzhong ; Liu, Yi L ; >yangh...@redhat.com >Subject: [PATCH] vfio/pci: Rem

Re: [PATCH v2 1/6] target/riscv: Propagate error from PMU setup

On 2023/10/11 22:45, Rob Bradford wrote: More closely follow the QEMU style by returning an Error and propagating it there is an error relating to the PMU setup. Further simplify the function by removing the num_counters parameter as this is available from the passed in cpu pointer. Signed-of

Re: [PATCH RFC v4 0/9] Add loongarch kvm accel support

Hi Philippe Mathieu-Daudé : Hi, On 9/10/23 11:01, xianglai li wrote: This series add loongarch kvm support, mainly implement some interfaces used by kvm such as kvm_arch_get/set_regs, kvm_arch_handle_exit, kvm_loongarch_set_interrupt, etc. Currently, we are able to boot LoongArch KVM Linux Gue

[PULL 07/54] target/riscv/cpu.c: add riscv_cpu_add_qdev_prop_array()

From: Daniel Henrique Barboza The code inside riscv_cpu_add_user_properties() became quite repetitive after recent changes. Add a helper to hide the repetition away. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Andrew Jones Reviewed-by: Alistair Francis Reviewed-by: Philippe Mathieu-Da

[PULL 11/54] avocado, risc-v: add tuxboot tests for 'max' CPU

From: Daniel Henrique Barboza Add smoke tests to ensure that we'll not break the 'max' CPU type when adding new frozen/ratified RISC-V extensions. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Reviewed-by: Philippe Mathieu-Daudé Tested-by: Philippe Mathieu-Daudé Messag

[PULL 22/54] disas/riscv: Fix the typo of inverted order of pmpaddr13 and pmpaddr14

From: Alvin Chang Fix the inverted order of pmpaddr13 and pmpaddr14 in csr_name(). Signed-off-by: Alvin Chang Reviewed-by: Alistair Francis Message-ID: <20230907084500.328-1-alvi...@andestech.com> Signed-off-by: Alistair Francis --- disas/riscv.c | 4 ++-- 1 file changed, 2 insertions(+), 2

[PULL 21/54] target/riscv: Clear CSR values at reset and sync MPSTATE with host

From: "liguang.zhang" This patch fixes guest reboot errors when using KVM. There are two issues when rebooting a guest using KVM 1. When the guest initiates a reboot the host is unable to stop the vcpu 2. When running a SMP guest the qemu monitor system_reset causes a vcpu crash This can be fix

[PULL 03/54] target/riscv/cpu.c: split kvm prop handling to its own helper

From: Daniel Henrique Barboza Future patches will split the existing Property arrays even further, and the existing code in riscv_cpu_add_user_properties() will start to scale bad with it because it's dealing with KVM constraints mixed in with TCG constraints. We're going to pay a high price to s

[PULL 00/54] riscv-to-apply queue

The following changes since commit a51e5124a655b3dad80b36b18547cb1eca2c5eb2: Merge tag 'pull-omnibus-111023-1' of https://gitlab.com/stsquad/qemu into staging (2023-10-11 09:43:10 -0400) are available in the Git repository at: https://github.com/alistair23/qemu.git tags/pull-riscv-to-apply-

[PULL 12/54] target/riscv: deprecate the 'any' CPU type

From: Daniel Henrique Barboza The 'any' CPU type was introduced in commit dc5bd18fa5725 ("RISC-V CPU Core Definition"), being around since the beginning. It's not an easy CPU to use: it's undocumented and its name doesn't tell users much about what the CPU is supposed to bring. 'git log' doesn't

[PULL 25/54] target/riscv: move riscv_cpu_validate_set_extensions() to tcg-cpu.c

From: Daniel Henrique Barboza This function is the core of the RISC-V validations for TCG CPUs, and it has a lot going on. Functions in cpu.c were made public to allow them to be used by the KVM accelerator class later on. 'cpu_cfg_ext_get_min_version()' is notably hard to move it to another fil

[PULL 15/54] target/riscv/cpu.c: introduce cpu_cfg_ext_auto_update()

From: Daniel Henrique Barboza During realize() time we're activating a lot of extensions based on some criteria, e.g.: if (cpu->cfg.ext_zk) { cpu->cfg.ext_zkn = true; cpu->cfg.ext_zkr = true; cpu->cfg.ext_zkt = true; } This practice resulted in at least one case

[PULL 13/54] target/riscv/cpu.c: use offset in isa_ext_is_enabled/update_enabled

From: Daniel Henrique Barboza We'll have future usage for a function where, given an offset of the struct RISCVCPUConfig, the flag is updated to a certain val. Change all existing callers to use edata->ext_enable_offset instead of 'edata'. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Al

[PULL 08/54] target/riscv/cpu.c: add riscv_cpu_add_kvm_unavail_prop_array()

From: Daniel Henrique Barboza Use a helper in riscv_cpu_add_kvm_properties() to eliminate some of its code repetition. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Andrew Jones Reviewed-by: Alistair Francis Message-ID: <20230912132423.268494-9-dbarb...@ventanamicro.com> Signed-off-by:

[PULL 02/54] target/riscv/cpu.c: skip 'bool' check when filtering KVM props

From: Daniel Henrique Barboza After the introduction of riscv_cpu_options[] all properties in riscv_cpu_extensions[] are booleans. This check is now obsolete. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Reviewed-by: Andrew Jones Message-ID: <20230912132423.268494-3-db

[PULL 14/54] target/riscv: make CPUCFG() macro public

From: Daniel Henrique Barboza The RISC-V KVM driver uses a CPUCFG() macro that calculates the offset of a certain field in the struct RISCVCPUConfig. We're going to use this macro in target/riscv/cpu.c as well in the next patches. Make it public. Rename it to CPU_CFG_OFFSET() for more clarity wh

[PATCH 2/3] hw/pci-host/sh_pcic: Correct PCI host / devfn#0 function names

Host bridge device and PCI function #0 are inverted. Signed-off-by: Philippe Mathieu-Daudé --- hw/pci-host/sh_pci.c | 16 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/hw/pci-host/sh_pci.c b/hw/pci-host/sh_pci.c index 41aed48c85..580e273d96 100644 --- a/hw/pci-ho

[PULL 51/54] target/riscv/tcg: remove RVG warning

From: Daniel Henrique Barboza Vendor CPUs that set RVG are displaying user warnings about other extensions that RVG must enable, one warning per CPU. E.g.: $ ./build/qemu-system-riscv64 -smp 8 -M virt -cpu veyron-v1 -nographic qemu-system-riscv64: warning: Setting G will also set IMAFD_Zicsr_Zif

[PULL 45/54] softmmu: pass the main loop status to gdb "Wxx" packet

From: Clément Chigot gdb_exit function aims to close gdb sessions and sends the exit code of the current execution. It's being called by qemu_cleanup once the main loop is over. Until now, the exit code sent was always 0. Now that hardware can shutdown this main loop with custom exit codes, these

[PULL 38/54] target/riscv/cpu.c: make misa_ext_cfgs[] 'const'

From: Daniel Henrique Barboza The array isn't marked as 'const' because we're initializing their elements in riscv_cpu_add_misa_properties(), 'name' and 'description' fields. In a closer look we can see that we're not using these 2 fields after creating the MISA properties. And we can create the

[PULL 53/54] target/riscv: deprecate capital 'Z' CPU properties

From: Daniel Henrique Barboza At this moment there are eleven CPU extension properties that starts with capital 'Z': Zifencei, Zicsr, Zihintntl, Zihintpause, Zawrs, Zfa, Zfh, Zfhmin, Zve32f, Zve64f and Zve64d. All other extensions are named with lower-case letters. We want all properties to be n

[PULL 39/54] target/riscv/tcg: move riscv_cpu_add_misa_properties() to tcg-cpu.c

From: Daniel Henrique Barboza All code related to MISA TCG properties is also moved. At this point, all TCG properties handling is done in tcg-cpu.c, all KVM properties handling is done in kvm-cpu.c. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Andrew Jones Reviewed-by: Alistair Franci

[PULL 32/54] target/riscv: remove kvm-stub.c

From: Daniel Henrique Barboza This file is not needed for some time now. Both kvm_riscv_reset_vcpu() and kvm_riscv_set_irq() have public declarations in kvm_riscv.h and are wrapped in 'if kvm_enabled()' blocks that the compiler will rip it out in non-KVM builds. Signed-off-by: Daniel Henrique Ba

[PATCH 3/3] hw/pci-host/sh_pcic: Replace magic value by proper definition

Signed-off-by: Philippe Mathieu-Daudé --- hw/pci-host/sh_pci.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/hw/pci-host/sh_pci.c b/hw/pci-host/sh_pci.c index 580e273d96..4edebced5e 100644 --- a/hw/pci-host/sh_pci.c +++ b/hw/pci-host/sh_pci.c @@ -40,7 +40,7 @@ struct SH

[PULL 24/54] target/riscv: move riscv_cpu_realize_tcg() to TCG::cpu_realizefn()

From: Daniel Henrique Barboza riscv_cpu_realize_tcg() was added to allow TCG cpus to have a different realize() path during the common riscv_cpu_realize(), making it a good choice to start moving TCG exclusive code to tcg-cpu.c. Rename it to tcg_cpu_realizefn() and assign it as a implementation

[PULL 04/54] target/riscv: add DEFINE_PROP_END_OF_LIST() to riscv_cpu_options[]

From: Daniel Henrique Barboza Add DEFINE_PROP_END_OF_LIST() and eliminate the ARRAY_SIZE() usage when iterating in the riscv_cpu_options[] array, making it similar to what we already do when working with riscv_cpu_extensions[]. We also have a more sophisticated motivation behind this change. In

[PULL 10/54] target/riscv: add 'max' CPU type

From: Daniel Henrique Barboza The 'max' CPU type is used by tooling to determine what's the most capable CPU a current QEMU version implements. Other archs such as ARM implements this type. Let's add it to RISC-V. What we consider "most capable CPU" in this context are related to ratified, non-v

[PULL 34/54] target/riscv: move KVM only files to kvm subdir

From: Daniel Henrique Barboza Move the files to a 'kvm' dir to promote more code separation between accelerators and making our lives easier supporting build options such as --disable-tcg. Rename kvm.c to kvm-cpu.c to keep it in line with its TCG counterpart. Signed-off-by: Daniel Henrique Barb

[PULL 37/54] target/riscv/tcg: introduce tcg_cpu_instance_init()

From: Daniel Henrique Barboza tcg_cpu_instance_init() will be the 'cpu_instance_init' impl for the TCG accelerator. It'll be called from within riscv_cpu_post_init(), via accel_cpu_instance_init(), similar to what happens with KVM. In fact, to preserve behavior, the implementation will be similar

[PULL 18/54] target/riscv: use isa_ext_update_enabled() in init_max_cpu_extensions()

From: Daniel Henrique Barboza Before adding support to detect if an extension was user set we need to handle how we're enabling extensions in riscv_init_max_cpu_extensions(). object_property_set_bool() calls the set() callback for the property, and we're going to use this callback to set the 'mul

[PULL 17/54] target/riscv/cpu.c: introduce RISCVCPUMultiExtConfig

From: Daniel Henrique Barboza If we want to make better decisions when auto-enabling extensions during realize() we need a way to tell if an user set an extension manually. The RISC-V KVM driver has its own solution via a KVMCPUConfig struct that has an 'user_set' flag that is set during the Prop

[PULL 16/54] target/riscv/cpu.c: use cpu_cfg_ext_auto_update() during realize()

From: Daniel Henrique Barboza Let's change the other instances in realize() where we're enabling an extension based on a certain criteria (e.g. it's a dependency of another extension). We're leaving icsr and ifencei being enabled during RVG for later - we'll want to error out in that case. Every

[PULL 30/54] target/riscv: move riscv_cpu_add_kvm_properties() to kvm.c

From: Daniel Henrique Barboza We'll introduce the KVM accelerator class with a 'cpu_instance_init' implementation that is going to be invoked during the common riscv_cpu_post_init() (via accel_cpu_instance_init()). This instance_init will execute KVM exclusive code that TCG doesn't care about, su

[PULL 36/54] target/riscv/cpu.c: export set_misa()

From: Daniel Henrique Barboza We'll move riscv_init_max_cpu_extensions() to tcg-cpu.c in the next patch and set_misa() needs to be usable from there. Rename it to riscv_cpu_set_misa() and make it public. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: A

[PULL 09/54] target/riscv/cpu.c: limit cfg->vext_spec log message

From: Daniel Henrique Barboza Inside riscv_cpu_validate_v() we're always throwing a log message if the user didn't set a vector version via 'vext_spec'. We're going to include one case with the 'max' CPU where env->vext_ver will be set in the cpu_init(). But that alone will not stop the "vector

[PULL 27/54] target/riscv/cpu.c: add .instance_post_init()

From: Daniel Henrique Barboza All generic CPUs call riscv_cpu_add_user_properties(). The 'max' CPU calls riscv_init_max_cpu_extensions(). Both can be moved to a common instance_post_init() callback, implemented in riscv_cpu_post_init(), called by all CPUs. The call order then becomes: riscv_cpu_

[PULL 29/54] target/riscv/cpu.c: mark extensions arrays as 'const'

From: Daniel Henrique Barboza We'll need to export these arrays to the accelerator classes in the next patches. Mark them as 'const' now because they should not be modified at runtime. Note that 'riscv_cpu_options' will also be exported, but can't be marked as 'const', because the properties are

[PULL 01/54] target/riscv/cpu.c: split CPU options from riscv_cpu_extensions[]

From: Daniel Henrique Barboza We'll add a new CPU type that will enable a considerable amount of extensions. To make it easier for us we'll do a few cleanups in our existing riscv_cpu_extensions[] array. Start by splitting all CPU non-boolean options from it. Create a new riscv_cpu_options[] arr

[PULL 06/54] target/riscv/cpu.c: split vendor exts from riscv_cpu_extensions[]

From: Daniel Henrique Barboza Our goal is to make riscv_cpu_extensions[] hold only ratified, non-vendor extensions. Create a new riscv_cpu_vendor_exts[] array for them, changing riscv_cpu_add_user_properties() and riscv_cpu_add_kvm_properties() accordingly. Signed-off-by: Daniel Henrique Barboz

[PULL 41/54] target/riscv/cpu: move priv spec functions to tcg-cpu.c

From: Daniel Henrique Barboza Priv spec validation is TCG specific. Move it to the TCG accel class. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Andrew Jones Reviewed-by: Alistair Francis Reviewed-by: Philippe Mathieu-Daudé Message-ID: <20230925175709.35696-20-dbarb...@ventanamicro.co

[PULL 49/54] target/riscv/kvm: improve 'init_multiext_cfg' error msg

From: Daniel Henrique Barboza Our error message is returning the value of 'ret', which will be always -1 in case of error, and will not be that useful: qemu-system-riscv64: Unable to read ISA_EXT KVM register ssaia, error -1 Improve the error message by outputting 'errno' instead of 'ret'. Use

[PULL 52/54] target/riscv: Use env_archcpu for better performance

From: "Richard W.M. Jones" RISCV_CPU(cs) uses a checked cast. When QOM cast debugging is enabled this adds about 5% total overhead when emulating RV64 on x86-64 host. Using a RISC-V guest with 16 vCPUs, 16 GB of guest RAM, virtio-blk disk. The guest has a copy of the qemu source tree. The tes

[PULL 05/54] target/riscv/cpu.c: split non-ratified exts from riscv_cpu_extensions[]

From: Daniel Henrique Barboza Create a new riscv_cpu_experimental_exts[] to store the non-ratified extensions properties. Once they are ratified we'll move them back to riscv_cpu_extensions[]. riscv_cpu_add_user_properties() and riscv_cpu_add_kvm_properties() are changed to keep adding non-ratif

[PULL 40/54] target/riscv/cpu.c: export isa_edata_arr[]

From: Daniel Henrique Barboza This array will be read by the TCG accel class, allowing it to handle priv spec verifications on its own. The array will remain here in cpu.c because it's also used by the riscv,isa string function. To export it we'll finish it with an empty element since ARRAY_SIZE

[PULL 43/54] target/riscv/tcg-cpu.c: add extension properties for all cpus

From: Daniel Henrique Barboza At this moment we do not expose extension properties for vendor CPUs because that would allow users to change them via command line. The drawback is that if we were to add an API that shows all CPU properties, e.g. qmp-query-cpu-model-expansion, we won't be able to s

[PULL 54/54] target/riscv: Fix vfwmaccbf16.vf

From: Max Chou The operator (fwmacc16) of vfwmaccbf16.vf helper function should be replaced by fwmaccbf16. Fixes: adf772b0f7 ("target/riscv: Add support for Zvfbfwma extension") Signed-off-by: Max Chou Reviewed-by: LIU Zhiwei Reviewed-by: Philippe Mathieu-Daudé Message-ID: <20231005095734.567

[PULL 33/54] target/riscv: introduce KVM AccelCPUClass

From: Daniel Henrique Barboza Add a KVM accelerator class like we did with TCG. The difference is that, at least for now, we won't be using a realize() implementation for this accelerator. We'll start by assiging kvm_riscv_cpu_add_kvm_properties(), renamed to kvm_cpu_instance_init(), as a 'cpu_i

[PULL 35/54] target/riscv/kvm: do not use riscv_cpu_add_misa_properties()

From: Daniel Henrique Barboza riscv_cpu_add_misa_properties() is being used to fill the missing KVM MISA properties but it is a TCG helper that was adapted to do so. We'll move it to tcg-cpu.c in the next patches, meaning that KVM needs to fill the remaining MISA properties on its own. Do not us

[PULL 42/54] target/riscv: add riscv_cpu_get_name()

From: Daniel Henrique Barboza We'll introduce generic errors that will output a CPU type name via its RISCVCPU pointer. Create a helper for that. Use the helper in tcg_cpu_realizefn() instead of hardcoding the 'host' CPU name. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Alistair Franci

[PULL 47/54] hw/char: riscv_htif: replace exit calls with proper shutdown

From: Clément Chigot This replaces the exit calls by shutdown requests, ensuring a proper cleanup of Qemu. Otherwise, some connections like gdb could be broken before its final packet ("Wxx") is being sent. This part, being done inside qemu_cleanup function, can be reached only when the main loop

[PULL 19/54] target/riscv/cpu.c: honor user choice in cpu_cfg_ext_auto_update()

From: Daniel Henrique Barboza Add a new cpu_cfg_ext_is_user_set() helper to check if an extension was set by the user in the command line. Use it inside cpu_cfg_ext_auto_update() to verify if the user set a certain extension and, if that's the case, do not change its value. This will make us hon

[PULL 28/54] target/riscv: move 'host' CPU declaration to kvm.c

From: Daniel Henrique Barboza This CPU only exists if we're compiling with KVM so move it to the kvm specific file. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Andrew Jones Reviewed-by: LIU Zhiwei Reviewed-by: Alistair Francis Message-ID: <2023092

[PATCH 1/3] hw/pci-host/sh_pcic: Declare CPU QOM types using DEFINE_TYPES() macro

When multiple QOM types are registered in the same file, it is simpler to use the the DEFINE_TYPES() macro. In particular because type array declared with such macro are easier to review. Signed-off-by: Philippe Mathieu-Daudé --- hw/pci-host/sh_pci.c | 40 +---

[PULL 31/54] target/riscv: make riscv_add_satp_mode_properties() public

From: Daniel Henrique Barboza This function is used for both accelerators. Make it public, and call it from kvm_riscv_cpu_add_kvm_properties(). This will make it easier to split KVM specific code for the KVM accelerator class in the next patch. Signed-off-by: Daniel Henrique Barboza Reviewed-by

[PULL 23/54] target/riscv: introduce TCG AccelCPUClass

From: Daniel Henrique Barboza target/riscv/cpu.c needs to handle all possible accelerators (TCG and KVM at this moment) during both init() and realize() time. This forces us to resort to a lot of "if tcg" and "if kvm" throughout the code, which isn't wrong, but can get cluttered over time. Splitt

[PULL 26/54] target/riscv: move riscv_tcg_ops to tcg-cpu.c

From: Daniel Henrique Barboza Move the remaining of riscv_tcg_ops now that we have a working realize() implementation. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Andrew Jones Reviewed-by: LIU Zhiwei Reviewed-by: Alistair Francis Message-ID: <2023

[PULL 44/54] softmmu: add means to pass an exit code when requesting a shutdown

From: Clément Chigot As of now, the exit code was either EXIT_FAILURE when a panic shutdown was requested or EXIT_SUCCESS otherwise. However, some hardware could want to pass more complex exit codes. Thus, introduce a new shutdown request function allowing that. Signed-off-by: Clément Chigot Re

[PULL 20/54] target/riscv/cpu.c: consider user option with RVG

From: Daniel Henrique Barboza Enabling RVG will enable a set of extensions that we're not checking if the user was okay enabling or not. And in this case we want to error out, instead of ignoring, otherwise we will be inconsistent enabling RVG without all its extensions. After this patch, disabl

[PULL 50/54] target/riscv/kvm: support KVM_GET_REG_LIST

From: Daniel Henrique Barboza KVM for RISC-V started supporting KVM_GET_REG_LIST in Linux 6.6. It consists of a KVM ioctl() that retrieves a list of all available regs for get_one_reg/set_one_reg. Regs that aren't present in the list aren't supported in the host. This simplifies our lives when i

[PULL 48/54] gdbstub: replace exit calls with proper shutdown for softmmu

From: Clément Chigot This replaces the exit calls by shutdown requests, ensuring a proper cleanup of Qemu. Features like net/vhost-vdpa.c are expecting qemu_cleanup to be called to remove their last residuals. Signed-off-by: Clément Chigot Reviewed-by: Alistair Francis Message-ID: <20231003071

[PULL 46/54] hw/misc/sifive_test.c: replace exit calls with proper shutdown

From: Clément Chigot This replaces the exit calls by shutdown requests, ensuring a proper cleanup of Qemu. Otherwise, some connections like gdb could be broken before its final packet ("Wxx") is being sent. This part, being done inside qemu_cleanup function, can be reached only when the main loop

[PATCH 0/3] hw/pci-host/sh_pcic: Style cleanup

- Use QOM DEFINE_TYPES - Rename few functions - Replace magic value by definition Philippe Mathieu-Daudé (3): hw/pci-host/sh_pcic: Declare CPU QOM types using DEFINE_TYPES() macro hw/pci-host/sh_pcic: Correct PCI host / devfn#0 function names hw/pci-host/sh_pcic: Replace magic value by prope

Re: [RFC/PATCH v0 01/12] hw/arm/virt: Avoid NULL pointer de-reference

Hi Srivatsa, (+Markus/Peter for QOM fu) On 11/10/23 18:52, Srivatsa Vaddagiri wrote: Avoid dereferencing a NULL pointer that its_class_name() could return. While your patch is correct, there is some code smell around its_class_name(). IMHO a foo_class_name() handler should never return NULL.

Re: [RFC/PATCH v0 03/12] gunyah: Basic support

Hi Srivatsa, On 11/10/23 18:52, Srivatsa Vaddagiri wrote: Add a new accelerator, gunyah, with basic functionality of creating a VM. Subsequent patches will add support for other functions required to run a VM. Signed-off-by: Srivatsa Vaddagiri --- MAINTAINERS | 7 +++

Re: [RFC/PATCH v0 08/12] gunyah: Specific device-tree location

On 11/10/23 18:52, Srivatsa Vaddagiri wrote: Specify the location of device-tree and its size, as Gunyah requires the device-tree to be parsed before VM can begin its execution. Signed-off-by: Srivatsa Vaddagiri --- MAINTAINERS | 1 + hw/arm/virt.c | 6 ++ includ

Re: [RFC/PATCH v0 09/12] gunyah: Customize device-tree

On 11/10/23 18:52, Srivatsa Vaddagiri wrote: Customize device-tree with Gunyah specific properties. Some of these properties include specification of doorbells that need to be created and associated with various interrupts. Signed-off-by: Srivatsa Vaddagiri --- hw/arm/virt.c | 11 ++

Re: [PATCH] hw/i386/cxl: ensure maxram is greater than ram size for calculating cxl range

> On 11-Oct-2023, at 10:01 PM, Jonathan Cameron > wrote: > > On Wed, 11 Oct 2023 16:23:35 +0530 > Ani Sinha wrote: > >> pc_get_device_memory_range() finds the device memory size by calculating the >> difference between maxram and ram sizes. This calculation makes sense only >> when >> maxr

Re: [RFC/PATCH v0 10/12] gunyah: CPU execution loop

On 11/10/23 18:52, Srivatsa Vaddagiri wrote: Complete the cpu execution loop. At this time, we recognize exits associated with only MMIO access. Future patches will add support for recognizing other exit reasons, such as PSCI calls made by guest. Signed-off-by: Srivatsa Vaddagiri --- accel/gu

Re: [RFC/PATCH v0 12/12] gunyah: Documentation

Hi Srivatsa, On 11/10/23 18:52, Srivatsa Vaddagiri wrote: Add gunyah.rst that provide some informaiton on how to build and test 'gunyah' accelerator with open-source Gunyah hypervisor. Signed-off-by: Srivatsa Vaddagiri --- MAINTAINERS| 1 + docs/system/arm/gunyah.rst | 214

Re: [RFC/PATCH v0 01/12] hw/arm/virt: Avoid NULL pointer de-reference

Philippe Mathieu-Daudé writes: > Hi Srivatsa, > > (+Markus/Peter for QOM fu) QOM fu needs Paolo; cc'ed. I'm not sure how much this is about QOM, though. Perhaps it's more about good taste. > On 11/10/23 18:52, Srivatsa Vaddagiri wrote: >> Avoid dereferencing a NULL pointer that its_class_name

[PATCH 0/4] gdbstub and TCG plugin improvements

This series extracts fixes and refactorings that can be applied independently from "[PATCH v9 00/23] plugins: Allow to read registers". The patch "target/riscv: Move MISA limits to class" was replaced with patch "target/riscv: Move misa_mxl_max to class" since I found instances may have different

[PATCH 4/4] plugins: Remove an extra parameter

copy_call() has an unused parameter so remove it. Signed-off-by: Akihiko Odaki --- accel/tcg/plugin-gen.c | 9 +++-- 1 file changed, 3 insertions(+), 6 deletions(-) diff --git a/accel/tcg/plugin-gen.c b/accel/tcg/plugin-gen.c index 39b3c9351f..78b331b251 100644 --- a/accel/tcg/plugin-gen.c

[PATCH 1/4] target/riscv: Remove misa_mxl validation

It is initialized with a simple assignment and there is little room for error. In fact, the validation is even more complex. Signed-off-by: Akihiko Odaki --- target/riscv/cpu.c | 13 ++--- 1 file changed, 2 insertions(+), 11 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cp

[PATCH 3/4] target/riscv: Validate misa_mxl_max only once

misa_mxl_max is now a class member and initialized only once for each class. This also moves the initialization of gdb_core_xml_file which will be referenced before realization in the future. Signed-off-by: Akihiko Odaki --- target/riscv/cpu.c | 6 ++ 1 file changed, 2 insertions(+), 4 delet

[PATCH 2/4] target/riscv: Move misa_mxl_max to class

misa_mxl_max is common for all instances of a RISC-V CPU class so they are better put into class. Signed-off-by: Akihiko Odaki --- target/riscv/cpu-qom.h | 1 + target/riscv/cpu.h | 1 - hw/riscv/boot.c | 2 +- target/riscv/cpu.c | 127 +++

[PATCH v10 05/18] target/ppc: Use GDBFeature for dynamic XML

In preparation for a change to use GDBFeature as a parameter of gdb_register_coprocessor(), convert the internal representation of dynamic feature from plain XML to GDBFeature. Signed-off-by: Akihiko Odaki Reviewed-by: Richard Henderson --- target/ppc/cpu-qom.h | 4 ++-- target/ppc/cpu.h

[PATCH v10 00/18] plugins: Allow to read registers

Based-on: <20231012054223.37870-1-akihiko.od...@daynix.com> ("[PATCH 0/4] gdbstub and TCG plugin improvements") I and other people in the University of Tokyo, where I research processor design, found TCG plugins are very useful for processor design exploration. The feature we find missing is the

[PATCH v10 03/18] gdbstub: Introduce GDBFeatureBuilder

GDBFeatureBuilder unifies the logic to generate dynamic GDBFeature. Signed-off-by: Akihiko Odaki Reviewed-by: Richard Henderson --- include/exec/gdbstub.h | 20 ++ gdbstub/gdbstub.c | 59 ++ 2 files changed, 79 insertions(+) diff --git a

[PATCH v10 14/18] gdbstub: Expose functions to read registers

gdb_find_feature() and gdb_find_feature_register() find registers. gdb_read_register() actually reads registers. Signed-off-by: Akihiko Odaki --- include/exec/gdbstub.h | 5 + gdbstub/gdbstub.c | 31 ++- 2 files changed, 35 insertions(+), 1 deletion(-) diff

[PATCH v10 15/18] cpu: Call plugin hooks only when ready

The initialization and exit hooks will not affect the state of vCPU outside TCG context, but they may depend on the state of vCPU. Therefore, it's better to call plugin hooks after the vCPU state is fully initialized and before it gets uninitialized. Signed-off-by: Akihiko Odaki --- cpu-target.c

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