There's one commit, tagged v7.2.2, without Signed-off-by line.
Due to this, check-dco test always fail on 7.2. Since this is
a stable branch with almost all commits coming from master
already with S-o-b (except of the version bumps and very rare
stable-specific commits), and v7.2.2 is already cast
25.08.2023 23:08, Denis V. Lunev wrote:
+/* Remember parent's stderr if we will be restoring it. */
+if (verbose /* fork_process is set */) {
+opts.stderr = dup(STDERR_FILENO);
+if (opts.stderr < 0) {
+error_report("Could
On 9/8/23 10:21, Philippe Mathieu-Daudé wrote:
On 8/9/23 08:04, Alistair Francis wrote:
From: Daniel Henrique Barboza
Future patches will split the existing Property arrays even further, and
the existing code in riscv_cpu_add_user_properties() will start to scale
bad with it because it's de
08.09.2023 10:54, Paolo Bonzini wrote:
It is forbidden to block on the event loop during a coroutine, as that
can cause deadlocks due to recursive locking.
Signed-off-by: Paolo Bonzini
---
include/block/aio.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/block/a
On 9/7/23 05:46, Andrew Jones wrote:
Add instructions for how to cross-compile QEMU for RISC-V. The
file is named generically because there's no reason not to collect
other architectures steps into the same file, especially because
several subsections like those for cross-compiling QEMU depend
I'm just wondering if there are any plans to apply my patch in this version or
if you would like me to change anything more in the patch? I am aware that
during this time of the year many have been away on vacation and it has also
been a new release 8.1 which has blocked any submitted patches but b
On Sat, 19 Aug 2023 at 03:02, Richard Henderson
wrote:
>
> Signed-off-by: Richard Henderson
Reviewed-by: Ard Biesheuvel
> ---
> include/crypto/clmul.h | 41 +
> crypto/clmul.c | 60 ++
> crypto/meson.build | 9 ++
On Sat, 19 Aug 2023 at 03:02, Richard Henderson
wrote:
>
> Signed-off-by: Richard Henderson
Reviewed-by: Ard Biesheuvel
> ---
> include/crypto/clmul.h | 16
> crypto/clmul.c | 21 +
> 2 files changed, 37 insertions(+)
>
> diff --git a/include/crypt
On Sat, 19 Aug 2023 at 03:02, Richard Henderson
wrote:
>
> Signed-off-by: Richard Henderson
Reviewed-by: Ard Biesheuvel
> ---
> include/crypto/clmul.h | 7 +++
> crypto/clmul.c | 13 +
> 2 files changed, 20 insertions(+)
>
> diff --git a/include/crypto/clmul.h b/inclu
On Mon, 21 Aug 2023 at 18:19, Richard Henderson
wrote:
>
> Signed-off-by: Richard Henderson
Replied to v2 by accident:
Reviewed-by: Ard Biesheuvel
> ---
> include/crypto/clmul.h | 7 +++
> crypto/clmul.c | 13 +
> 2 files changed, 20 insertions(+)
>
> diff --git a/i
On Mon, 21 Aug 2023 at 18:19, Richard Henderson
wrote:
>
> Signed-off-by: Richard Henderson
Reviewed-by: Ard Biesheuvel
> ---
> host/include/generic/host/crypto/clmul.h | 15 +++
> include/crypto/clmul.h | 19 +++
> crypto/clmul.c
On Mon, 21 Aug 2023 at 18:19, Richard Henderson
wrote:
>
> Detect PCLMUL in cpuinfo; implement the accel hook.
>
> Signed-off-by: Richard Henderson
Reviewed-by: Ard Biesheuvel
> ---
> host/include/i386/host/cpuinfo.h| 1 +
> host/include/i386/host/crypto/clmul.h | 29 ++
On Mon, 21 Aug 2023 at 18:18, Richard Henderson
wrote:
>
> Signed-off-by: Richard Henderson
Reviewed-by: Ard Biesheuvel
> ---
> include/crypto/clmul.h | 41 +
> crypto/clmul.c | 60 ++
> crypto/meson.build | 9 +
On Mon, 21 Aug 2023 at 18:19, Richard Henderson
wrote:
>
> Signed-off-by: Richard Henderson
> ---
> include/crypto/clmul.h | 16
> crypto/clmul.c | 21 +
> 2 files changed, 37 insertions(+)
>
> diff --git a/include/crypto/clmul.h b/include/crypto/clmu
Applied, thanks.
Please update the changelog at https://wiki.qemu.org/ChangeLog/8.2 for any
user-visible changes.
signature.asc
Description: PGP signature
Applied, thanks.
Please update the changelog at https://wiki.qemu.org/ChangeLog/8.2 for any
user-visible changes.
signature.asc
Description: PGP signature
Applied, thanks.
Please update the changelog at https://wiki.qemu.org/ChangeLog/8.2 for any
user-visible changes.
signature.asc
Description: PGP signature
08.09.2023 07:24, Nicholas Piggin wrote:
Nicholas Piggin (26):
target/ppc: Remove single-step suppression inside 0x100-0xf00
target/ppc: Improve book3s branch trace interrupt for v2.07S
target/ppc: Suppress single step interrupts on rfi-type instructions
target/pp
On Tue, Sep 5, 2023 at 3:06 PM Andrei Gudkov
wrote:
> This patch allows to measure dirty page rate for
> sub-second intervals of time. An optional argument is
> introduced -- calc-time-unit. For example:
> {"execute": "calc-dirty-rate", "arguments":
> {"calc-time": 500, "calc-time-unit": "milli
Hi!
For quite some time I'm collecting stuff for stable, pocking various
people with questions about stable, etc, so has become somewhat more
visible and somewhat annoying too :) Especially when I publish the
next stable patch round-up, which has not only become larger when
counting individual p
09.09.2023 16:04, Michael Tokarev wrote:
From: Niklas Cassel
For NCQ, PxCI is cleared on command queued successfully.
For non-NCQ, PxCI is cleared on command completed successfully.
Successfully means ERR_STAT, BUSY and DRQ are all cleared.
A command that has ERR_STAT set, does not get to clea
Hi Philippe,
On 9/8/23 21:22, Philippe Mathieu-Daudé wrote:
Add a field to return the QOM type name of a CPU class.
Signed-off-by: Philippe Mathieu-Daudé
---
include/hw/core/cpu.h | 2 ++
hw/core/cpu-common.c| 2 +-
target/alpha/cpu.c | 1 +
target/arm/cpu.c| 1 +
targ
On 9/8/23 21:22, Philippe Mathieu-Daudé wrote:
Signed-off-by: Philippe Mathieu-Daudé
---
target/alpha/cpu.c | 7 ++-
1 file changed, 2 insertions(+), 5 deletions(-)
Reviewed-by: Gavin Shan
diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c
index 270ae787b1..351ee2e9f2 100644
--
On 9/8/23 21:22, Philippe Mathieu-Daudé wrote:
Leverage the public CPUClass::cpu_resolving_type field and
call object_class_dynamic_cast() once in cpu_class_by_name().
Signed-off-by: Philippe Mathieu-Daudé
---
hw/core/cpu-common.c | 3 ++-
target/alpha/cpu.c | 3 +--
target/arm/cpu.
On 9/8/23 21:23, Philippe Mathieu-Daudé wrote:
On 8/9/23 10:04, Philippe Mathieu-Daudé wrote:
On 8/9/23 01:44, Gavin Shan wrote:
On 9/7/23 18:20, David Hildenbrand wrote:
On 07.09.23 02:35, Gavin Shan wrote:
For target/s390x, the CPU type name is always the combination of the
CPU modle name
On 9/8/23 17:56, Philippe Mathieu-Daudé wrote:
On 8/9/23 01:49, Gavin Shan wrote:
On 9/7/23 19:05, Philippe Mathieu-Daudé wrote:
On 7/9/23 02:35, Gavin Shan wrote:
The names of supported CPU models instead of CPU types should be
printed when the user specified CPU type isn't supported, to be
c
On Sun, Sep 10, 2023 at 6:58 PM Daniel Henrique Barboza
wrote:
>
>
>
> On 9/8/23 10:21, Philippe Mathieu-Daudé wrote:
> > On 8/9/23 08:04, Alistair Francis wrote:
> >> From: Daniel Henrique Barboza
> >>
> >> Future patches will split the existing Property arrays even further, and
> >> the existin
On Sat, Sep 2, 2023 at 5:48 AM Daniel Henrique Barboza
wrote:
>
> Hi,
>
> This new version contains suggestions made by Andrew Jones in v8.
>
> Most notable change is the removal of the opensbi.py test in patch 11,
> which was replaced by a TuxBoot test. It's more suitable to test the
> integrity
On Fri, Sep 8, 2023 at 4:38 PM Michael Tokarev wrote:
>
> 08.09.2023 09:03, Alistair Francis wrote:
>
> > Akihiko Odaki (1):
> >target/riscv: Allocate itrigger timers only once
> >
> > Ard Biesheuvel (2):
> >target/riscv: Use existing lookup tables for MixColumns
> >target/
Philippe Mathieu-Daudé writes:
> On 8/9/23 08:54, Mark Cave-Ayland wrote:
>> On 07/07/2023 09:29, Philippe Mathieu-Daudé wrote:
>>
>>> On 2/7/23 17:48, Mark Cave-Ayland wrote:
This determines whether the Apple Sound Chip (ASC) is set to enhanced mode
(default) or to original mode. The
Kindly ping for any comments.
Thanks,
Qian
On 8/29/2023 12:24 PM, Qian Wen wrote:
> CPUID.1.EBX[23:16]: Maximum number of addressable IDs for logical
> processors in this physical package.
> CPUID.4:EAX[31:26]: Maximum number of addressable IDs for processor cores
> in the physical package.
>
> T
On 2023/9/10 1:43, Richard Henderson wrote:
On 9/7/23 20:23, LIU Zhiwei wrote:
From: LIU Zhiwei
Signed-off-by: LIU Zhiwei
---
include/qemu/timer.h | 19 +++
1 file changed, 19 insertions(+)
diff --git a/include/qemu/timer.h b/include/qemu/timer.h
index 9a91cb1248..ce0b66
On 2023/9/9 22:45, Palmer Dabbelt wrote:
On Sat, 09 Sep 2023 00:18:02 PDT (-0700), pbonz...@redhat.com wrote:
Il sab 9 set 2023, 03:35 Atish Patra ha scritto:
On Fri, Sep 8, 2023 at 3:29 AM Paolo Bonzini
wrote:
>
> Queued, thanks.
>
I didn't realize it was already queued. Gmail threads f
On 10/09/2023 09.30, Michael Tokarev wrote:
There's one commit, tagged v7.2.2, without Signed-off-by line.
Due to this, check-dco test always fail on 7.2. Since this is
a stable branch with almost all commits coming from master
already with S-o-b (except of the version bumps and very rare
stable
On 9/7/23 05:18, Nicholas Piggin wrote:
On Wed Sep 6, 2023 at 2:33 PM AEST, Harsh Prateek Bora wrote:
Adding new macros for the new hypercall op-codes, their return codes,
Guest State Buffer (GSB) element IDs and few registers which shall be
used in following patches to support Nested PAPR AP
Signed-off-by: LIU Zhiwei
---
v2:
1) Use rdtime instead of rdcycle for dynamic cpuclk adjustment.
2) Read timeh twice in case of time overflow for 32-bit cpu.
---
include/qemu/timer.h | 22 ++
1 file changed, 22 insertions(+)
diff --git a/include/qemu/timer.h b/include/qemu
From: Thomas Huth
The character that should be printed is stored in the 64 bit "payload"
variable. The code currently tries to print it by taking the address
of the variable and passing this pointer to qemu_chr_fe_write(). However,
this only works on little endian hosts where the least significan
The following changes since commit c5ea91da443b458352c1b629b490ee6631775cb4:
Merge tag 'pull-trivial-patches' of https://gitlab.com/mjt0k/qemu into
staging (2023-09-08 10:06:25 -0400)
are available in the Git repository at:
https://github.com/alistair23/qemu.git tags/pull-riscv-to-apply-202
From: Thomas Huth
Values that have been read via cpu_physical_memory_read() from the
guest's memory have to be swapped in case the host endianess differs
from the guest.
Fixes: a6e13e31d5 ("riscv_htif: Support console output via proxy syscall")
Signed-off-by: Thomas Huth
Reviewed-by: Alistair F
From: Daniel Henrique Barboza
The 'host' CPU is available in a CONFIG_KVM build and it's currently
available for all accels, but is a KVM only CPU. This means that in a
RISC-V KVM capable host we can do things like this:
$ ./build/qemu-system-riscv64 -M virt,accel=tcg -cpu host --nographic
qemu-
From: Max Chou
Adds sm4_ck constant for use in sm4 cryptography across different targets.
Signed-off-by: Max Chou
Reviewed-by: Frank Chang
Signed-off-by: Max Chou
Message-ID: <20230711165917.2629866-15-max.c...@sifive.com>
Signed-off-by: Alistair Francis
---
include/crypto/sm4.h | 1 +
cry
From: Nazar Kazakov
Move the checks out of `do_opiv{v,x,i}_gvec{,_shift}` functions
and into the corresponding macros. This enables the functions to be
reused in proceeding commits without check duplication.
Signed-off-by: Nazar Kazakov
Reviewed-by: Richard Henderson
Reviewed-by: Weiwei Li
Si
From: Nazar Kazakov
Remove the redundant "vl == 0" check which is already included within the
vstart >= vl check, when vl == 0.
Signed-off-by: Nazar Kazakov
Reviewed-by: Weiwei Li
Signed-off-by: Max Chou
Acked-by: Alistair Francis
Message-ID: <20230711165917.2629866-4-max.c...@sifive.com>
From: LIU Zhiwei
Commit bef6f008b98(accel/tcg: Return bool from page_check_range) converts
integer return value to bool type. However, it wrongly converted the use
of the API in riscv fault-only-first, where page_check_range < = 0, should
be converted to !page_check_range.
Signed-off-by: LIU Zhi
From: Nazar Kazakov
This commit adds support for the Zvkned vector-crypto extension, which
consists of the following instructions:
* vaesef.[vv,vs]
* vaesdf.[vv,vs]
* vaesdm.[vv,vs]
* vaesz.vs
* vaesem.[vv,vs]
* vaeskf1.vi
* vaeskf2.vi
Translation functions are defined in
`target/riscv/insn_tra
From: Lawrence Hunter
This commit adds support for the Zvbc vector-crypto extension, which
consists of the following instructions:
* vclmulh.[vx,vv]
* vclmul.[vx,vv]
Translation functions are defined in
`target/riscv/insn_trans/trans_rvvk.c.inc` and helpers are defined in
`target/riscv/vcrypto_
From: Yong-Xuan Wang
We create a vAIA chip by using the KVM_DEV_TYPE_RISCV_AIA and then set up
the chip with the KVM_DEV_RISCV_AIA_GRP_* APIs.
We also extend KVM accelerator to specify the KVM AIA mode. The "riscv-aia"
parameter is passed along with --accel in QEMU command-line.
1) "riscv-aia=emu
From: Kiran Ostrolenk
Move some macros out of `vector_helper` and into `vector_internals`.
This ensures they can be used by both vector and vector-crypto helpers
(latter implemented in proceeding commits).
Signed-off-by: Kiran Ostrolenk
Reviewed-by: Weiwei Li
Signed-off-by: Max Chou
Message-I
From: Rob Bradford
These are WARL fields - zero out the bits for unavailable counters and
special case the TM bit in mcountinhibit which is hardwired to zero.
This patch achieves this by modifying the value written so that any use
of the field will see the correctly masked bits.
Tested by modify
From: Max Chou
This commit adds support for the Zvksed vector-crypto extension, which
consists of the following instructions:
* vsm4k.vi
* vsm4r.[vv,vs]
Translation functions are defined in
`target/riscv/insn_trans/trans_rvvk.c.inc` and helpers are defined in
`target/riscv/vcrypto_helper.c`.
S
From: Daniel Henrique Barboza
Commit 6df0b37e2ab breaks a --enable-debug build in a non-KVM
environment with the following error:
/usr/bin/ld: libqemu-riscv64-softmmu.fa.p/hw_intc_riscv_aplic.c.o: in function
`riscv_kvm_aplic_request':
./qemu/build/../hw/intc/riscv_aplic.c:486: undefined refere
From: Conor Dooley
On a dtb dumped from the virt machine, dt-validate complains:
soc: pmu: {'riscv,event-to-mhpmcounters': [[1, 1, 524281], [2, 2, 524284],
[65561, 65561, 524280], [65563, 65563, 524280], [65569, 65569, 524280]],
'compatible': ['riscv,pmu']} should not be valid under {'type': 'o
From: Yong-Xuan Wang
In this patch, we create the APLIC and IMSIC FDT helper functions and
remove M mode AIA devices when using KVM acceleration.
Signed-off-by: Yong-Xuan Wang
Reviewed-by: Jim Shu
Reviewed-by: Daniel Henrique Barboza
Reviewed-by: Andrew Jones
Message-ID: <20230727102439.2255
From: Lawrence Hunter
This commit adds support for the Zvksh vector-crypto extension, which
consists of the following instructions:
* vsm3me.vv
* vsm3c.vi
Translation functions are defined in
`target/riscv/insn_trans/trans_rvvk.c.inc` and helpers are defined in
`target/riscv/vcrypto_helper.c`.
From: Kiran Ostrolenk
Refactor the non SEW-specific stuff out of `GEN_OPIVV_TRANS` into
function `opivv_trans` (similar to `opivi_trans`). `opivv_trans` will be
used in proceeding vector-crypto commits.
Signed-off-by: Kiran Ostrolenk
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
On 9/8/23 11:29, Joao Martins wrote:
QEMU computes the DMA logging ranges for two predefined ranges: 32-bit
and 64-bit. In the OVMF case, when the dynamic MMIO window is enabled,
QEMU includes in the 64-bit range the RAM regions at the lower part
and vfio-pci device RAM regions which are at the t
From: Vineet Gupta
zicond is now codegen supported in both llvm and gcc.
This change allows seamless enabling/testing of zicond in downstream
projects. e.g. currently riscv-gnu-toolchain parses elf attributes
to create a cmdline for qemu but fails short of enabling it because of
the "x-" prefix.
From: Daniel Henrique Barboza
zmmul was promoted from experimental to ratified in commit 6d00ffad4e95.
Add a riscv,isa string for it.
Fixes: 6d00ffad4e95 ("target/riscv: move zmmul out of the experimental
properties")
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Weiwei Li
Reviewed-by:
From: Yong-Xuan Wang
KVM AIA can't emulate APLIC only. When "aia=aplic" parameter is passed,
APLIC devices is emulated by QEMU. For "aia=aplic-imsic", remove the
mmio operations of APLIC when using KVM AIA and send wired interrupt
signal via KVM_IRQ_LINE API.
After KVM AIA enabled, MSI messages a
From: Yong-Xuan Wang
Select KVM AIA when the host kernel has in-kernel AIA chip support.
Since KVM AIA only has one APLIC instance, we map the QEMU APLIC
devices to KVM APLIC.
Signed-off-by: Yong-Xuan Wang
Reviewed-by: Jim Shu
Reviewed-by: Daniel Henrique Barboza
Reviewed-by: Andrew Jones
Me
From: Max Chou
Allows sharing of sm4_subword between different targets.
Signed-off-by: Max Chou
Reviewed-by: Frank Chang
Reviewed-by: Richard Henderson
Signed-off-by: Max Chou
Message-ID: <20230711165917.2629866-14-max.c...@sifive.com>
Signed-off-by: Alistair Francis
---
include/crypto/sm4
From: Dickon Hood
This commit adds support for the Zvbb vector-crypto extension, which
consists of the following instructions:
* vrol.[vv,vx]
* vror.[vv,vx,vi]
* vbrev8.v
* vrev8.v
* vandn.[vv,vx]
* vbrev.v
* vclz.v
* vctz.v
* vcpop.v
* vwsll.[vv,vx,vi]
Translation functions are defined in
`tar
From: LIU Zhiwei
We should not use types dependend on host arch for target_ucontext.
This bug is found when run rv32 applications.
Signed-off-by: LIU Zhiwei
Reviewed-by: Richard Henderson
Reviewed-by: Daniel Henrique Barboza
Reviewed-by: Philippe Mathieu-Daudé
Message-ID: <20230811055438.194
From: Nazar Kazakov
This commit adds support for the Zvkg vector-crypto extension, which
consists of the following instructions:
* vgmul.vv
* vghsh.vv
Translation functions are defined in
`target/riscv/insn_trans/trans_rvvk.c.inc` and helpers are defined in
`target/riscv/vcrypto_helper.c`.
Co-
From: Jason Chien
When writing the upper mtime, we should keep the original lower mtime
whose value is given by cpu_riscv_read_rtc() instead of
cpu_riscv_read_rtc_raw(). The same logic applies to writes to lower mtime.
Signed-off-by: Jason Chien
Reviewed-by: Alistair Francis
Message-ID: <20230
On 9/7/23 06:36, Nicholas Piggin wrote:
On Wed Sep 6, 2023 at 2:33 PM AEST, Harsh Prateek Bora wrote:
This patch introduces new data structures to be used with Nested PAPR
API. Also extends kvmppc_hv_guest_state with additional set of registers
supported with nested PAPR API.
Signed-off-by:
From: Daniel Henrique Barboza
The cpu->cfg.epmp extension is still experimental, but it already has a
'smepmp' riscv,isa string. Add it.
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Weiwei Li
Reviewed-by: Alistair Francis
Message-Id: <20230720132424.371132-3-dbarb...@ventanamicro.com>
From: Kiran Ostrolenk
Take some functions/macros out of `vector_helper` and put them in a new
module called `vector_internals`. This ensures they can be used by both
vector and vector-crypto helpers (latter implemented in proceeding
commits).
Signed-off-by: Kiran Ostrolenk
Reviewed-by: Weiwei L
From: Weiwei Li
The Svadu specification updated the name of the *envcfg bit from
HADE to ADUE.
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
Reviewed-by: Daniel Henrique Barboza
Message-ID: <20230816141916.66898-1-liwei...@iscas.ac.cn>
Signed-off-by: Alistair Francis
---
target/risc
From: LIU Zhiwei
Commit a47842d ("riscv: Add support for the Zfa extension") implemented the zfa
extension.
However, it has some typos for fleq.d and fltq.d. Both of them misused the
fltq.s
helper function.
Fixes: a47842d ("riscv: Add support for the Zfa extension")
Signed-off-by: LIU Zhiwei
From: Ard Biesheuvel
Use the accelerated SubBytes/ShiftRows/AddRoundKey AES helper to
implement the first half of the key schedule derivation. This does not
actually involve shifting rows, so clone the same value into all four
columns of the AES vector to counter that operation.
Cc: Richard Hend
From: Kiran Ostrolenk
This commit adds support for the Zvknh vector-crypto extension, which
consists of the following instructions:
* vsha2ms.vv
* vsha2c[hl].vv
Translation functions are defined in
`target/riscv/insn_trans/trans_rvvk.c.inc` and helpers are defined in
`target/riscv/vcrypto_helpe
From: Jason Chien
The variables whose values are given by cpu_riscv_read_rtc() should be named
"rtc". The variables whose value are given by cpu_riscv_read_rtc_raw()
should be named "rtc_r".
Signed-off-by: Jason Chien
Reviewed-by: Alistair Francis
Message-ID: <20230728082502.26439-2-jason.ch..
From: Robbin Ehn
This patch adds the new extensions in
linux 6.5 to the hwprobe syscall.
And fixes RVC check to OR with correct value.
The previous variable contains 0 therefore it
did work.
Signed-off-by: Robbin Ehn
Acked-by: Richard Henderson
Acked-by: Alistair Francis
Message-ID:
Signed-
On Fri, Sep 8, 2023 at 5:55 PM Philippe Mathieu-Daudé
wrote:
> On 8/9/23 17:47, Albert Esteve wrote:
> > v1 link ->
> https://lists.gnu.org/archive/html/qemu-devel/2023-05/msg00598.html
> > v2 link ->
> https://lists.gnu.org/archive/html/qemu-devel/2023-05/msg04530.html
> > v3 link ->
> https://l
From: Dickon Hood
Zvbb (implemented in later commit) has a widening instruction, which
requires an extra check on the enabled extensions. Refactor
GEN_OPIVX_WIDEN_TRANS() to take a check function to avoid reimplementing
it.
Signed-off-by: Dickon Hood
Reviewed-by: Richard Henderson
Reviewed-by
From: Tommy Wu
According to the new spec, when vsiselect has a reserved value, attempts
from M-mode or HS-mode to access vsireg, or from VS-mode to access
sireg, should preferably raise an illegal instruction exception.
Signed-off-by: Tommy Wu
Reviewed-by: Frank Chang
Message-ID: <202308160616
From: Leon Schuermann
When the rule-lock bypass (RLB) bit is set in the mseccfg CSR, the PMP
configuration lock bits must not apply. While this behavior is
implemented for the pmpcfgX CSRs, this bit is not respected for
changes to the pmpaddrX CSRs. This patch ensures that pmpaddrX CSR
writes wor
From: Nikita Shubin
As per ISA:
"For CSRRWI, if rd=x0, then the instruction shall not read the CSR and
shall not cause any of the side effects that might occur on a CSR read."
trans_csrrwi() and trans_csrrw() call do_csrw() if rd=x0, do_csrw() calls
riscv_csrrw_do64(), via helper_csrw() passing
From: Daniel Henrique Barboza
A build with --enable-debug and without KVM will fail as follows:
/usr/bin/ld: libqemu-riscv64-softmmu.fa.p/hw_riscv_virt.c.o: in function
`virt_machine_init':
./qemu/build/../hw/riscv/virt.c:1465: undefined reference to
`kvm_riscv_aia_create'
This happens becaus
From: Yong-Xuan Wang
We check the in-kernel irqchip support when using KVM acceleration.
Signed-off-by: Yong-Xuan Wang
Reviewed-by: Jim Shu
Reviewed-by: Daniel Henrique Barboza
Reviewed-by: Andrew Jones
Message-ID: <20230727102439.22554-3-yongxuan.w...@sifive.com>
Signed-off-by: Alistair Fra
From: Akihiko Odaki
riscv_trigger_init() had been called on reset events that can happen
several times for a CPU and it allocated timers for itrigger. If old
timers were present, they were simply overwritten by the new timers,
resulting in a memory leak.
Divide riscv_trigger_init() into two func
From: Jason Chien
RVA23 Profiles states:
The RVA23 profiles are intended to be used for 64-bit application
processors that will run rich OS stacks from standard binary OS
distributions and with a substantial number of third-party binary user
applications that will be supported over a considerable
From: Daniel Henrique Barboza
In the same emulated RISC-V host, the 'host' KVM CPU takes 4 times
longer to boot than the 'rv64' KVM CPU.
The reason is an unintended behavior of riscv_cpu_satp_mode_finalize()
when satp_mode.supported = 0, i.e. when cpu_init() does not set
satp_mode_max_supported(
From: Ard Biesheuvel
The AES MixColumns and InvMixColumns operations are relatively
expensive 4x4 matrix multiplications in GF(2^8), which is why C
implementations usually rely on precomputed lookup tables rather than
performing the calculations on demand.
Given that we already carry those table
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