Instead of manually setting "foo-len" and "foo[i]" properties, build a
QList and use the new qdev_prop_set_array() helper to set the whole
array property with a single call.
Signed-off-by: Kevin Wolf
---
hw/i386/pc.c | 8 +---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/hw/
Instead of manually setting "foo-len" and "foo[i]" properties, build a
QList and use the new qdev_prop_set_array() helper to set the whole
array property with a single call.
Signed-off-by: Kevin Wolf
---
hw/arm/mps2.c | 12
1 file changed, 8 insertions(+), 4 deletions(-)
diff --git
Instead of manually setting "foo-len" and "foo[i]" properties, build a
QList and use the new qdev_prop_set_array() helper to set the whole
array property with a single call.
Signed-off-by: Kevin Wolf
---
hw/arm/xlnx-versal.c | 9 +++--
1 file changed, 7 insertions(+), 2 deletions(-)
diff --
Instead of manually setting "foo-len" and "foo[i]" properties, build a
QList and use the new qdev_prop_set_array() helper to set the whole
array property with a single call.
Signed-off-by: Kevin Wolf
---
hw/arm/virt.c | 31 +--
1 file changed, 17 insertions(+), 14 del
Instead of manually setting "foo-len" and "foo[i]" properties, build a
QList and use the new qdev_prop_set_array() helper to set the whole
array property with a single call.
Signed-off-by: Kevin Wolf
---
hw/rx/rx62n.c | 19 ++-
1 file changed, 10 insertions(+), 9 deletions(-)
di
On Fri, 8 Sep 2023 14:45:24 +0200
Tim Wiederhake wrote:
> Synchronizing the list of cpu features and models with qemu is a recurring
> task in libvirt. For x86, this is done by reading qom-list-properties for
> max-x86_64-cpu and manually filtering out everthing that does not look like
> a featu
On Thu, 2023-09-07 at 11:02 +0200, Thomas Huth wrote:
> On 01/09/2023 17.58, Nina Schoetterl-Glausch wrote:
> > From: Pierre Morel
> >
> > Polarization is changed on a request from the guest.
> > Let's verify the polarization is accordingly set by QEMU.
> >
> > Signed-off-by: Pierre Morel
> > C
Am 07.09.2023 um 17:44 hat Stefan Hajnoczi geschrieben:
> Applied, thanks.
>
> Please update the changelog at https://wiki.qemu.org/ChangeLog/8.2 for any
> user-visible changes.
Something in this has broken the build for me, it seems to be the
linux-user binary that doesn't link any more:
/us
> On 08-Sep-2023, at 7:46 PM, David Hildenbrand wrote:
>
> On 08.09.23 16:12, Ani Sinha wrote:
>>> On 08-Sep-2023, at 3:58 PM, David Hildenbrand wrote:
>>>
>>> On 08.09.23 11:50, Ani Sinha wrote:
Depending on the number of available address bits of the current
processor, a
VM
On Fri, 8 Sept 2023 at 15:37, Kevin Wolf wrote:
>
> Until now, array properties are actually implemented with a hack that
> uses multiple properties on the QOM level: a static "foo-len" property
> and after it is set, dynamically created "foo[i]" properties.
>
> In external interfaces (-device on
On Fri, 8 Sept 2023 at 12:55, Peter Maydell wrote:
>
> On Wed, 30 Aug 2023 at 00:24, Richard Henderson
> wrote:
> >
> > Changes for v5:
> > * Updates for review.
> > * Include linux-user ESR changes.
> >
> > Patch 10 is the only one without review.
> >
> >
> > r~
>
> Applied to target-arm.nex
Add three new vhost-user protocol
`VHOST_USER_BACKEND_SHARED_OBJECT_* messages`.
These new messages are sent from vhost-user
back-ends to interact with the virtio-dmabuf
table in order to add or remove themselves as
virtio exporters, or lookup for virtio dma-buf
shared objects.
The action taken in
This API manages objects (in this iteration,
dmabuf fds) that can be shared along different
virtio devices, associated to a UUID.
The API allows the different devices to add,
remove and/or retrieve the objects by simply
invoking the public functions that reside in the
virtio-dmabuf file.
For vhos
v1 link -> https://lists.gnu.org/archive/html/qemu-devel/2023-05/msg00598.html
v2 link -> https://lists.gnu.org/archive/html/qemu-devel/2023-05/msg04530.html
v3 link -> https://lists.gnu.org/archive/html/qemu-devel/2023-05/msg06126.html
v4 link -> https://lists.gnu.org/archive/html/qemu-devel/2023-
In the libvhost-user library we need to
handle VHOST_USER_GET_SHARED_OBJECT requests,
and add helper functions to allow sending messages
to interact with the virtio shared objects
hash table.
Signed-off-by: Albert Esteve
---
subprojects/libvhost-user/libvhost-user.c | 120 ++
I wonder how it passed CI?
https://gitlab.com/qemu-project/qemu/-/pipelines/996175923/
Stefan
On Fri, 8 Sept 2023 at 11:02, Kevin Wolf wrote:
>
> Am 07.09.2023 um 17:44 hat Stefan Hajnoczi geschrieben:
> > Applied, thanks.
> >
> > Please update the changelog at https://wiki.qemu.org/ChangeLog/8.
Add hash function to uuid module using the
djb2 hash algorithm.
Add a couple simple unit tests for the hash
function, checking collisions for similar UUIDs.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Albert Esteve
---
include/qemu/uuid.h| 2 ++
tests/unit/test-uuid.c | 27
On 8/9/23 17:47, Albert Esteve wrote:
v1 link -> https://lists.gnu.org/archive/html/qemu-devel/2023-05/msg00598.html
v2 link -> https://lists.gnu.org/archive/html/qemu-devel/2023-05/msg04530.html
v3 link -> https://lists.gnu.org/archive/html/qemu-devel/2023-05/msg06126.html
v4 link -> https://lis
On 08.09.23 17:13, Ani Sinha wrote:
On 08-Sep-2023, at 7:46 PM, David Hildenbrand wrote:
On 08.09.23 16:12, Ani Sinha wrote:
On 08-Sep-2023, at 3:58 PM, David Hildenbrand wrote:
On 08.09.23 11:50, Ani Sinha wrote:
Depending on the number of available address bits of the current processor
On 08/09/2023 10:42, Philippe Mathieu-Daudé wrote:
On 8/9/23 08:54, Mark Cave-Ayland wrote:
On 07/07/2023 09:29, Philippe Mathieu-Daudé wrote:
On 2/7/23 17:48, Mark Cave-Ayland wrote:
This determines whether the Apple Sound Chip (ASC) is set to enhanced mode
(default) or to original mode. Th
On 08.09.23 18:02, David Hildenbrand wrote:
On 08.09.23 17:13, Ani Sinha wrote:
On 08-Sep-2023, at 7:46 PM, David Hildenbrand wrote:
On 08.09.23 16:12, Ani Sinha wrote:
On 08-Sep-2023, at 3:58 PM, David Hildenbrand wrote:
On 08.09.23 11:50, Ani Sinha wrote:
Depending on the number of av
On 8/9/23 17:13, Ani Sinha wrote:
On 08-Sep-2023, at 7:46 PM, David Hildenbrand wrote:
On 08.09.23 16:12, Ani Sinha wrote:
On 08-Sep-2023, at 3:58 PM, David Hildenbrand wrote:
On 08.09.23 11:50, Ani Sinha wrote:
Depending on the number of available address bits of the current processor,
On 8/9/23 18:03, Mark Cave-Ayland wrote:
On 08/09/2023 10:42, Philippe Mathieu-Daudé wrote:
On 8/9/23 08:54, Mark Cave-Ayland wrote:
On 07/07/2023 09:29, Philippe Mathieu-Daudé wrote:
On 2/7/23 17:48, Mark Cave-Ayland wrote:
This determines whether the Apple Sound Chip (ASC) is set to
enhan
Hi Kevin,
On 8/9/23 17:01, Kevin Wolf wrote:
Am 07.09.2023 um 17:44 hat Stefan Hajnoczi geschrieben:
Applied, thanks.
Please update the changelog at https://wiki.qemu.org/ChangeLog/8.2 for any
user-visible changes.
Something in this has broken the build for me, it seems to be the
linux-user
On 7/9/23 14:59, Paolo Bonzini wrote:
If dtc is available, compile the .dts files in the pc-bios directory
instead of using the precompiled binaries.
Reviewed-by: Richard Henderson
Signed-off-by: Paolo Bonzini
---
pc-bios/Makefile| 19 ---
pc-bios/meson.build | 25 ++
On Fri, Sep 08, 2023 at 04:48:46PM +0200, Igor Mammedov wrote:
> On Fri, 8 Sep 2023 14:45:24 +0200
> Tim Wiederhake wrote:
>
> > Synchronizing the list of cpu features and models with qemu is a recurring
> > task in libvirt. For x86, this is done by reading qom-list-properties for
> > max-x86_64
08.08.2023 17:44, Jonathan Cameron:
Sorry, I'm running a bit behind. Have this one a few other fixes
still queued up - I didn't consider any of them particularly critical
for the release so wasn't rushing.
I'll aim to get them out as a series soon though so they are
available for start of next
From: Aaron Lindsay
Rename isar_feature_aa64_pauth_arch to isar_feature_aa64_pauth_qarma5
to distinguish the other architectural algorithm qarma3.
Add ARMPauthFeature and isar_feature_pauth_feature to cover the
other pauth conditions.
Reviewed-by: Peter Maydell
Signed-off-by: Aaron Lindsay
Si
From: Richard Henderson
Provide a stub implementation, as a write is a "request".
Signed-off-by: Richard Henderson
Message-id: 20230831232441.66020-2-richard.hender...@linaro.org
Reviewed-by: Peter Maydell
Signed-off-by: Peter Maydell
---
target/arm/helper.c | 64
From: Francisco Iglesias
Introduce a model of Xilinx Versal's Configuration Frame broadcast
controller (CFRAME_BCAST_REG).
Signed-off-by: Francisco Iglesias
Reviewed-by: Peter Maydell
Message-id: 20230831165701.2016397-7-francisco.igles...@amd.com
Signed-off-by: Peter Maydell
---
include/hw/
From: Richard Henderson
STGP writes to tag memory, it does not check it.
This happened to work because we wrote tag memory first
so that the check always succeeded.
Signed-off-by: Richard Henderson
Message-id: 20230901203103.136408-1-richard.hender...@linaro.org
Reviewed-by: Peter Maydell
Sign
From: Aaron Lindsay
An instruction is a 'combined' Pointer Authentication instruction
if it does something in addition to PAC -- for instance, branching
to or loading an address from the authenticated pointer.
Knowing whether a PAC operation is 'combined' is needed to
implement FEAT_FPACCOMBINE.
From: Francisco Iglesias
Connect the Configuration Frame controller (CFRAME_REG) and the
Configuration Frame broadcast controller (CFRAME_BCAST_REG) to the
Versal machine.
Signed-off-by: Francisco Iglesias
Reviewed-by: Peter Maydell
Message-id: 20230831165701.2016397-9-francisco.igles...@amd.c
From: Aaron Lindsay
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Signed-off-by: Aaron Lindsay
Signed-off-by: Peter Maydell
Signed-off-by: Richard Henderson
Message-id: 20230829232335.965414-3-richard.hender...@linaro.org
[PMM: drop the HVF part of the patch and just com
From: Colton Lewis
Due to recent KVM changes, QEMU is setting a ptimer offset resulting
in unintended trap and emulate access and a consequent performance
hit. Filter out the PTIMER_CNT register to restore trapless ptimer
access.
Quoting Andrew Jones:
Simply reading the CNT register and writing
From: Philippe Mathieu-Daudé
Fix when using GCC v11.4 (Ubuntu 11.4.0-1ubuntu1~22.04) with CFLAGS=-Og:
[4/6] Compiling C object libcommon.fa.p/hw_intc_arm_gicv3_its.c.o
FAILED: libcommon.fa.p/hw_intc_arm_gicv3_its.c.o
inlined from ‘lookup_vte’ at hw/intc/arm_gicv3_its.c:453:9,
inl
From: Richard Henderson
Implement the QARMA3 cryptographic algorithm for PAC calculation.
Implement a cpu feature to select the algorithm and document it.
Signed-off-by: Aaron Lindsay
Reviewed-by: Peter Maydell
Reviewed-by: Richard Henderson
Signed-off-by: Richard Henderson
Message-id: 20230
From: Shameer Kolothum
Now that we have Eager Page Split support added for ARM in the kernel,
enable it in Qemu. This adds,
-eager-split-size to -accel sub-options to set the eager page split chunk size.
-enable KVM_CAP_ARM_EAGER_SPLIT_CHUNK_SIZE.
The chunk size specifies how many pages to bre
From: Richard Henderson
We have cpu properties to adjust the pauth algorithm for the
purpose of speed of emulation. Retain the set of pauth features
supported by the cpu even as the algorithm changes.
This already affects the neoverse-v1 cpu, which has FEAT_EPAC.
Reviewed-by: Peter Maydell
Si
From: Aaron Lindsay
Signed-off-by: Aaron Lindsay
Reviewed-by: Richard Henderson
Signed-off-by: Richard Henderson
Message-id: 20230829232335.965414-10-richard.hender...@linaro.org
Message-Id: <20230609172324.982888-8-aa...@os.amperecomputing.com>
[rth: Simplify fpac comparison, reusing cmp_mask
From: Richard Henderson
The cortex-a710 is a first generation ARMv9.0-A processor.
Signed-off-by: Richard Henderson
Message-id: 20230831232441.66020-3-richard.hender...@linaro.org
Reviewed-by: Peter Maydell
Signed-off-by: Peter Maydell
---
docs/system/arm/virt.rst | 1 +
hw/arm/virt.c
From: Richard Henderson
With FEAT_FPAC, AUT* instructions that fail authentication
do not produce an error value but instead fault.
For pauth-2, install a signal handler and verify it gets called.
For pauth-4 and pauth-5, we are explicitly testing the error value,
so there's nothing to test wit
From: Francisco Iglesias
Introduce a model of Xilinx Versal's Configuration Frame controller
(CFRAME_REG).
Signed-off-by: Francisco Iglesias
Message-id: 20230831165701.2016397-6-francisco.igles...@amd.com
Reviewed-by: Peter Maydell
Signed-off-by: Peter Maydell
---
MAINTAINERS
From: Richard Henderson
Perform the check for EL2 enabled in the security space and the
TIDCP bit in an out-of-line helper.
Signed-off-by: Richard Henderson
Message-id: 20230831232441.66020-4-richard.hender...@linaro.org
Reviewed-by: Peter Maydell
Signed-off-by: Peter Maydell
---
target/arm/
From: Francisco Iglesias
Introduce a model of Xilinx Versal's Configuration Frame Unit's Single
Frame Read port (CFU_SFR).
Signed-off-by: Francisco Iglesias
Reviewed-by: Peter Maydell
Message-id: 20230831165701.2016397-5-francisco.igles...@amd.com
Signed-off-by: Peter Maydell
---
include/hw/
From: Richard Henderson
The linux kernel detects and enables this bit. Once trapped,
EC_SYSTEMREGISTERTRAP is treated like EC_UNCATEGORIZED, so
no changes required within linux-user/aarch64/cpu_loop.c.
Signed-off-by: Richard Henderson
Message-id: 20230831232441.66020-6-richard.hender...@linaro
From: Francisco Iglesias
Introduce the Xilinx Configuration Frame Interface (CFI) for transmitting
CFI data packets between the Xilinx Configuration Frame Unit models
(CFU_APB, CFU_FDRO and CFU_SFR), the Xilinx CFRAME controller (CFRAME_REG)
and the Xilinx CFRAME broadcast controller (CFRAME_BCAS
From: Aaron Lindsay
Signed-off-by: Aaron Lindsay
Reviewed-by: Peter Maydell
Reviewed-by: Richard Henderson
Signed-off-by: Richard Henderson
Message-id: 20230829232335.965414-8-richard.hender...@linaro.org
Message-Id: <20230609172324.982888-6-aa...@os.amperecomputing.com>
Signed-off-by: Richar
/git.linaro.org/people/pmaydell/qemu-arm.git
tags/pull-target-arm-20230908
for you to fetch changes up to c8f2eb5d414b788420b938f2ffdde891aa6c3ae8:
arm/kvm: Enable support for KVM_CAP_ARM_EAGER_SPLIT_CHUNK_SIZE (2023-09-08
16:41:36 +0100)
From: Francisco Iglesias
Connect the Configuration Frame Unit (CFU_APB, CFU_FDRO and CFU_SFR) to
the Versal machine.
Signed-off-by: Francisco Iglesias
Acked-by: Edgar E. Iglesias
Reviewed-by: Peter Maydell
Message-id: 20230831165701.2016397-8-francisco.igles...@amd.com
Signed-off-by: Peter Ma
From: Richard Henderson
Signed-off-by: Richard Henderson
Message-id: 20230831232441.66020-5-richard.hender...@linaro.org
Reviewed-by: Peter Maydell
Signed-off-by: Peter Maydell
---
docs/system/arm/emulation.rst | 1 +
target/arm/cpu.h | 5 +
target/arm/helper.h
From: Francisco Iglesias
Introduce a model of Xilinx Versal's Configuration Frame Unit's data out
port (CFU_FDRO).
Signed-off-by: Francisco Iglesias
Reviewed-by: Peter Maydell
Message-id: 20230831165701.2016397-4-francisco.igles...@amd.com
Signed-off-by: Peter Maydell
---
include/hw/misc/xln
From: Aaron Lindsay
Signed-off-by: Aaron Lindsay
Reviewed-by: Peter Maydell
Reviewed-by: Richard Henderson
Signed-off-by: Richard Henderson
Message-id: 20230829232335.965414-7-richard.hender...@linaro.org
Message-Id: <20230609172324.982888-5-aa...@os.amperecomputing.com>
Signed-off-by: Richar
From: Francisco Iglesias
Introduce a model of the software programming interface (CFU_APB) of
Xilinx Versal's Configuration Frame Unit.
Signed-off-by: Francisco Iglesias
Reviewed-by: Peter Maydell
Message-id: 20230831165701.2016397-3-francisco.igles...@amd.com
Signed-off-by: Peter Maydell
---
The following changes since commit 13d9f6dca08a38e9258b6328f3ad61bdb8e19619:
Merge tag 'ide-pull-request' of https://gitlab.com/jsnow/qemu into staging
(2023-09-07 10:28:33 -0400)
are available in the Git repository at:
https://repo.or.cz/qemu/kevin.git tags/for-upstream
for you to fetch c
On Fri, Sep 08, 2023 at 01:12:45PM +, J?rgen Hansen wrote:
> On 7/25/23 20:39, Fan Ni wrote:
> > From: Fan Ni
> >
> > Add dynamic capacity extent list representative to the definition of
> > CXLType3Dev and add get DC extent list mailbox command per
> > CXL.spec.3.0:.8.2.9.8.9.2.
> >
> > Signe
Am 08.09.2023 um 18:11 hat Philippe Mathieu-Daudé geschrieben:
> Hi Kevin,
>
> On 8/9/23 17:01, Kevin Wolf wrote:
> > Am 07.09.2023 um 17:44 hat Stefan Hajnoczi geschrieben:
> > > Applied, thanks.
> > >
> > > Please update the changelog at https://wiki.qemu.org/ChangeLog/8.2 for
> > > any user-v
08.09.2023 19:27, Philippe Mathieu-Daudé:
On 7/9/23 14:59, Paolo Bonzini wrote:
If dtc is available, compile the .dts files in the pc-bios directory
instead of using the precompiled binaries.
Reviewed-by: Richard Henderson
Signed-off-by: Paolo Bonzini
---
pc-bios/Makefile | 19 --
On Fri, Sep 08, 2023 at 01:00:16PM +, J?rgen Hansen wrote:
> On 7/25/23 20:39, Fan Ni wrote:
> > From: Fan Ni
> >
> > Per CXL spec 3.0, two mailbox commands are implemented:
> > Add Dynamic Capacity Response (Opcode 4802h) 8.2.9.8.9.3, and
> > Release Dynamic Capacity (Opcode 4803h) 8.2.9.8.9.
On Fri, Sep 08, 2023 at 07:16:16PM +0200, Kevin Wolf wrote:
> Am 08.09.2023 um 18:11 hat Philippe Mathieu-Daudé geschrieben:
> > Hi Kevin,
> >
> > On 8/9/23 17:01, Kevin Wolf wrote:
> > > Am 07.09.2023 um 17:44 hat Stefan Hajnoczi geschrieben:
> > > > Applied, thanks.
> > > >
> > > > Please updat
08.09.2023 20:16, Kevin Wolf:
Am 08.09.2023 um 18:11 hat Philippe Mathieu-Daudé geschrieben:
Hi Kevin,
On 8/9/23 17:01, Kevin Wolf wrote:
Am 07.09.2023 um 17:44 hat Stefan Hajnoczi geschrieben:
Applied, thanks.
Please update the changelog at https://wiki.qemu.org/ChangeLog/8.2 for any
user-
Am 08.09.2023 um 19:16 hat Kevin Wolf geschrieben:
> Am 08.09.2023 um 18:11 hat Philippe Mathieu-Daudé geschrieben:
> > Hi Kevin,
> >
> > On 8/9/23 17:01, Kevin Wolf wrote:
> > > Am 07.09.2023 um 17:44 hat Stefan Hajnoczi geschrieben:
> > > > Applied, thanks.
> > > >
> > > > Please update the cha
Am 08.09.2023 um 17:18 hat Peter Maydell geschrieben:
> On Fri, 8 Sept 2023 at 15:37, Kevin Wolf wrote:
> >
> > Until now, array properties are actually implemented with a hack that
> > uses multiple properties on the QOM level: a static "foo-len" property
> > and after it is set, dynamically crea
On Wed, Sep 06, 2023 at 12:52:22PM -0500, Eric Blake wrote:
> On Tue, Sep 05, 2023 at 05:36:15PM +0300, Vladimir Sementsov-Ogievskiy wrote:
> > On 29.08.23 20:58, Eric Blake wrote:
> > > Upcoming additions to support NBD 64-bit effect lengths allow for the
> > > possibility to distinguish between p
Hi Peter,
The Versal TRNG device is required to support both TRNG mode and PRNG mode, and
target/guest
software selects and changes the mode at will during runtime.
I do agree that, in the TRNG mode, the model using qemu_guest_getrandom() will
work without any issues.
When software selects the
Signed-off-by: Alexey Baturo
---
target/riscv/cpu.h | 10 ++
1 file changed, 10 insertions(+)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 62dabfa207..25fe60476b 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -88,6 +88,16 @@ typedef enum {
EXT_STATUS_DIRTY
Signed-off-by: Alexey Baturo
---
target/riscv/cpu.c| 1 +
target/riscv/cpu_helper.c | 1 +
target/riscv/csr.c| 4
target/riscv/machine.c| 1 +
target/riscv/pmp.c| 1 +
5 files changed, 8 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index af8
Signed-off-by: Alexey Baturo
---
target/riscv/cpu.c | 12 --
target/riscv/cpu.h | 30 +---
target/riscv/cpu_bits.h | 82 -
target/riscv/cpu_helper.c| 52 --
target/riscv/csr.c | 326 ---
target/riscv/machine.c
Signed-off-by: Alexey Baturo
---
target/riscv/translate.c | 21 +++--
target/riscv/vector_helper.c | 7 +++
2 files changed, 26 insertions(+), 2 deletions(-)
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 3434ba58b6..4aa0e2b9e1 100644
--- a/target
Signed-off-by: Alexey Baturo
---
target/riscv/cpu.h| 19 +--
target/riscv/cpu_helper.c | 4
target/riscv/translate.c | 10 ++
3 files changed, 27 insertions(+), 6 deletions(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 25fe60476b..17d0088cb4
Signed-off-by: Alexey Baturo
---
target/riscv/cpu.c | 7 +++
target/riscv/cpu_cfg.h | 3 +++
target/riscv/machine.c | 6 --
3 files changed, 14 insertions(+), 2 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index f937820976..af8f16b94f 100644
--- a/target/riscv/cp
Hi all,
This series of patches intends to update RISC-V Pointer Masking implementation
to the latest Zjpm v0.6.1 version.
The Pointer Masking functionality is simplified compared to previous version
of spec.
The changes have been tested with handwritten assembly tests and LLVM HWASAN
test suite.
Signed-off-by: Alexey Baturo
---
target/riscv/cpu.h| 6 ++--
target/riscv/cpu_helper.c | 58 +++
2 files changed, 62 insertions(+), 2 deletions(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 17d0088cb4..c87c4f26a2 100644
--- a/target/ri
Signed-off-by: Alexey Baturo
---
target/riscv/cpu_bits.h | 6 ++
target/riscv/csr.c | 8
target/riscv/pmp.c | 5 +
target/riscv/pmp.h | 12 +++-
4 files changed, 26 insertions(+), 5 deletions(-)
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bi
On Thu, 2023-09-07 at 11:05 +0200, Thomas Huth wrote:
> On 01/09/2023 17.58, Nina Schoetterl-Glausch wrote:
> > From: Pierre Morel
> >
> > Test changes in the entitlement from both a guest and a host point of
> > view, depending on the polarization.
> >
> > Signed-off-by: Pierre Morel
> > Co-de
On Fri, 8 Sept 2023 at 18:56, Ho, Tong wrote:
>
> Hi Peter,
>
> The Versal TRNG device is required to support both TRNG mode and PRNG mode,
> and target/guest
> software selects and changes the mode at will during runtime.
>
> I do agree that, in the TRNG mode, the model using qemu_guest_getrando
Hi Philippe,
Thank you for your comment.
On Wed, Sep 6, 2023 at 7:03 AM Philippe Mathieu-Daudé
wrote:
> +Gerd & Marc-André for the ui/fb parts.
>
> On 5/9/23 22:14, Strahinja Jankovic wrote:
> > This patch adds support for Allwinner A10 LCD controller.
> > Current emulation supports only RGB3
Hi Peter,
Your recommendation is noted. Thanks for your valuable input. I will present
V2 with better alignment.
Regards,
Tong Ho
-Original Message-
From: Peter Maydell
Sent: Friday, September 8, 2023 11:35 AM
To: Ho, Tong
Cc: Richard Henderson ; qemu-...@nongnu.org;
qemu-devel@no
On Fri, 8 Sep 2023, Michael Tokarev wrote:
08.09.2023 19:27, Philippe Mathieu-Daudé:
On 7/9/23 14:59, Paolo Bonzini wrote:
If dtc is available, compile the .dts files in the pc-bios directory
instead of using the precompiled binaries.
Reviewed-by: Richard Henderson
Signed-off-by: Paolo Bonzin
On Fri, Sep 8, 2023 at 7:28 PM Kevin Wolf wrote:
> Maybe the calls aren't eliminated because --enable-debug implies -O0?
My experience is that it will still fold simple dead code like "0 &&
foo()" or even "if (0) { ... }", but maybe it's a GCC vs. clang
difference. Philippe, I take it that you ar
08.09.2023 22:21, BALATON Zoltan:
..
I was about to ask, since when but probably nobody knows then. AFAIR I had no such errors for the canyonlands one when I've added it but that was
quite some years ago and things in dtc for example could have changed so it now gives these warnings.
I think it
On 9/7/23 09:03, Peter Maydell wrote:
The LDRT/STRT "unprivileged load/store" instructions behave like
normal ones if executed at EL0. We handle this correctly for
the load/store semantics, but get the MTE checking wrong.
We always look at s->mte_active[is_unpriv] to see whether we should
be doi
On Fri, 8 Sep 2023, Michael Tokarev wrote:
08.09.2023 22:21, BALATON Zoltan:
I was about to ask, since when but probably nobody knows then. AFAIR I had
no such errors for the canyonlands one when I've added it but that was
quite some years ago and things in dtc for example could have changed so
On 9/7/23 09:03, Peter Maydell wrote:
In every place that we call the get_a64_user_mem_index() function
we do it like this:
memidx = a->unpriv ? get_a64_user_mem_index(s) : get_mem_index(s);
Refactor so the caller passes in the bool that says whether they
want the 'unpriv' or 'normal' mem_index
On 9/7/23 09:03, Peter Maydell wrote:
The FEAT_MOPS memory operations can raise a Memory Copy or Memory Set
exception if a copy or set instruction is executed when the CPU
register state is not correct for that instruction. Define the
usual syn_* function that constructs the syndrome register val
On 9/7/23 09:03, Peter Maydell wrote:
@@ -198,6 +215,14 @@ static uint8_t *allocation_tag_mem(CPUARMState *env, int
ptr_mmu_idx,
return memory_region_get_ram_ptr(mr) + xlat;
#endif
}
+static uint8_t *allocation_tag_mem(CPUARMState *env, int ptr_mmu_idx,
Missed spacing.
Otherwise,
Re
On 9/7/23 09:03, Peter Maydell wrote:
The FEAT_MOPS instructions need a couple of helper routines that
check for MTE tag failures:
* mte_mops_probe() checks whether there is going to be a tag
error in the next up-to-a-page worth of data
* mte_check_fail() is an existing function to record
On 9/7/23 09:03, Peter Maydell wrote:
FEAT_MOPS defines a handful of new enable bits:
* HCRX_EL2.MSCEn, SCTLR_EL1.MSCEn, SCTLR_EL2.MSCen:
define whether the new insns should UNDEF or not
* HCRX_EL2.MCE2: defines whether memops exceptions from
EL1 should be taken to EL1 or EL2
Since w
qemu 8.1.0 breaks on illumos platforms due to _XOPEN_SOURCE and others
no longer being set correctly, leading to breakage such as:
https://us-central.manta.mnx.io/pkgsrc/public/reports/trunk/tools/20230908.1404/qemu-8.1.0/build.log
This is a result of meson conversion which incorrectly match
On Thu, Sep 07, 2023 at 11:07:10AM +0200, Cédric Le Goater wrote:
> [ ... ]
>
> > Applied to vfio-next.
>
> On that topic I am preparing a PR.
>
> Juan, Peter, Leonardo, is it ok for you if these migration changes
> go through the VFIO tree ?
All good here.
Thanks,
--
Peter Xu
This is a part of patchset where IBM's Flexible Service Interface is
introduced.
The LBUS device is embeded inside the scratchpad. The scratchpad
provides a non-functional registers. There is a 1-1 relation between
scratchpad and LBUS devices. Each LBUS device has 1K memory mapped in
the LBUS.
Si
Added maintainer for IBM FSI model
Signed-off-by: Ninad Palsule
---
V4:
- Added separate commit for MAINTAINER change.
---
MAINTAINERS | 22 ++
1 file changed, 22 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 6111b6b4d9..285f3a3bc9 100644
--- a/MAINTAINERS
+++
This is a part of patchset where IBM's Flexible Service Interface is
introduced.
The Common FRU Access Macro (CFAM), an address space containing
various "engines" that drive accesses on busses internal and external
to the POWER chip. Examples include the SBEFIFO and I2C masters. The
engines hang o
This is a part of patchset where IBM's Flexible Service Interface is
introduced.
This commit models the FSI bus. CFAM is hanging out of FSI bus. The bus
is model such a way that it is embeded inside the FSI master which is a
bus controller.
The FSI master: A controller in the platform service pro
Hello,
Please review the patch-set version 4.
I have incorporated review comments from Cedric and Thomas.
Ninad Palsule (10):
hw/fsi: Introduce IBM's Local bus
hw/fsi: Introduce IBM's scratchpad
hw/fsi: Introduce IBM's cfam,fsi-slave
hw/fsi: Introduce IBM's FSI
hw/fsi: IBM's On-chip Per
Added basic qtests for FSI model.
Signed-off-by: Ninad Palsule
---
v3:
- Added new qtest as per Cedric's comment.
V4:
- Remove MAINTAINER and documentation changes from this commit
---
tests/qtest/fsi-test.c | 210
tests/qtest/meson.build | 2 +
2 fi
Hello Thomas,
On 8/30/23 02:05, Thomas Huth wrote:
On 30/08/2023 04.26, Ninad Palsule wrote:
Added FSI document
Added basic qtests for FSI model.
Added MAINITAINER for FSI
Replaced some qemu logs to traces.
Sorry, that's not how we rework patch series in the QEMU development
process. Please
This is a part of patchset where IBM's Flexible Service Interface is
introduced.
The LBUS is modelled to maintain the qdev bus hierarchy and to take
advantage of the object model to automatically generate the CFAM
configuration block. The configuration block presents engines in the
order they are
Documentation for IBM FSI model.
Signed-off-by: Ninad Palsule
---
v4:
- Added separate commit for documentation
---
docs/specs/fsi.rst | 141 +
1 file changed, 141 insertions(+)
create mode 100644 docs/specs/fsi.rst
diff --git a/docs/specs/fsi.rst
This is a part of patchset where IBM's Flexible Service Interface is
introduced.
The On-Chip Peripheral Bus (OPB): A low-speed bus typically found in
POWER processors. This now makes an appearance in the ASPEED SoC due
to tight integration of the FSI master IP with the OPB, mainly the
existence of
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