[PULL 37/65] riscv: zicond: make non-experimental

2023-09-07 Thread Alistair Francis
From: Vineet Gupta zicond is now codegen supported in both llvm and gcc. This change allows seamless enabling/testing of zicond in downstream projects. e.g. currently riscv-gnu-toolchain parses elf attributes to create a cmdline for qemu but fails short of enabling it because of the "x-" prefix.

Re: [PULL 03/65] hw/char/riscv_htif: Fix the console syscall on big endian hosts

2023-09-07 Thread Michael Tokarev
08.09.2023 09:03, Alistair Francis wrote: From: Thomas Huth @@ -209,11 +210,11 @@ static void htif_handle_tohost_write(HTIFState *s, uint64_t val_written) } else { uint64_t syscall[8]; cpu_physical_memory_read(payload, syscall, sizeof(syscall

[PULL 26/65] hw/intc: Fix upper/lower mtime write calculation

2023-09-07 Thread Alistair Francis
From: Jason Chien When writing the upper mtime, we should keep the original lower mtime whose value is given by cpu_riscv_read_rtc() instead of cpu_riscv_read_rtc_raw(). The same logic applies to writes to lower mtime. Signed-off-by: Jason Chien Reviewed-by: Alistair Francis Message-ID: <20230

[PULL 04/65] target/riscv/cpu.c: add zmmul isa string

2023-09-07 Thread Alistair Francis
From: Daniel Henrique Barboza zmmul was promoted from experimental to ratified in commit 6d00ffad4e95. Add a riscv,isa string for it. Fixes: 6d00ffad4e95 ("target/riscv: move zmmul out of the experimental properties") Signed-off-by: Daniel Henrique Barboza Reviewed-by: Weiwei Li Reviewed-by:

[PULL 43/65] target/riscv/pmp.c: respect mseccfg.RLB for pmpaddrX changes

2023-09-07 Thread Alistair Francis
From: Leon Schuermann When the rule-lock bypass (RLB) bit is set in the mseccfg CSR, the PMP configuration lock bits must not apply. While this behavior is implemented for the pmpcfgX CSRs, this bit is not respected for changes to the pmpaddrX CSRs. This patch ensures that pmpaddrX CSR writes wor

[PULL 64/65] target/riscv/cpu.c: honor user choice in cpu_cfg_ext_auto_update()

2023-09-07 Thread Alistair Francis
From: Daniel Henrique Barboza Add a new cpu_cfg_ext_is_user_set() helper to check if an extension was set by the user in the command line. Use it inside cpu_cfg_ext_auto_update() to verify if the user set a certain extension and, if that's the case, do not change its value. This will make us hon

[PULL 34/65] hw/riscv: virt: Fix riscv,pmu DT node path

2023-09-07 Thread Alistair Francis
From: Conor Dooley On a dtb dumped from the virt machine, dt-validate complains: soc: pmu: {'riscv,event-to-mhpmcounters': [[1, 1, 524281], [2, 2, 524284], [65561, 65561, 524280], [65563, 65563, 524280], [65569, 65569, 524280]], 'compatible': ['riscv,pmu']} should not be valid under {'type': 'o

[PULL 62/65] target/riscv/cpu.c: introduce RISCVCPUMultiExtConfig

2023-09-07 Thread Alistair Francis
From: Daniel Henrique Barboza If we want to make better decisions when auto-enabling extensions during realize() we need a way to tell if an user set an extension manually. The RISC-V KVM driver has its own solution via a KVMCPUConfig struct that has an 'user_set' flag that is set during the Prop

[PULL 47/65] target/riscv/cpu.c: skip 'bool' check when filtering KVM props

2023-09-07 Thread Alistair Francis
From: Daniel Henrique Barboza After the introduction of riscv_cpu_options[] all properties in riscv_cpu_extensions[] are booleans. This check is now obsolete. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Reviewed-by: Andrew Jones Message-ID: <20230901194627.1214811-3-d

[PULL 65/65] target/riscv/cpu.c: consider user option with RVG

2023-09-07 Thread Alistair Francis
From: Daniel Henrique Barboza Enabling RVG will enable a set of extensions that we're not checking if the user was okay enabling or not. And in this case we want to error out, instead of ignoring, otherwise we will be inconsistent enabling RVG without all its extensions. After this patch, disabl

[PULL 18/65] target/riscv: Add Zvksh ISA extension support

2023-09-07 Thread Alistair Francis
From: Lawrence Hunter This commit adds support for the Zvksh vector-crypto extension, which consists of the following instructions: * vsm3me.vv * vsm3c.vi Translation functions are defined in `target/riscv/insn_trans/trans_rvvk.c.inc` and helpers are defined in `target/riscv/vcrypto_helper.c`.

[PULL 49/65] target/riscv: add DEFINE_PROP_END_OF_LIST() to riscv_cpu_options[]

2023-09-07 Thread Alistair Francis
From: Daniel Henrique Barboza Add DEFINE_PROP_END_OF_LIST() and eliminate the ARRAY_SIZE() usage when iterating in the riscv_cpu_options[] array, making it similar to what we already do when working with riscv_cpu_extensions[]. We also have a more sophisticated motivation behind this change. In

[PULL 21/65] crypto: Add SM4 constant parameter CK

2023-09-07 Thread Alistair Francis
From: Max Chou Adds sm4_ck constant for use in sm4 cryptography across different targets. Signed-off-by: Max Chou Reviewed-by: Frank Chang Signed-off-by: Max Chou Message-ID: <20230711165917.2629866-15-max.c...@sifive.com> Signed-off-by: Alistair Francis --- include/crypto/sm4.h | 1 + cry

[PULL 46/65] target/riscv/cpu.c: split CPU options from riscv_cpu_extensions[]

2023-09-07 Thread Alistair Francis
From: Daniel Henrique Barboza We'll add a new CPU type that will enable a considerable amount of extensions. To make it easier for us we'll do a few cleanups in our existing riscv_cpu_extensions[] array. Start by splitting all CPU non-boolean options from it. Create a new riscv_cpu_options[] arr

[PULL 30/65] target/riscv: check the in-kernel irqchip support

2023-09-07 Thread Alistair Francis
From: Yong-Xuan Wang We check the in-kernel irqchip support when using KVM acceleration. Signed-off-by: Yong-Xuan Wang Reviewed-by: Jim Shu Reviewed-by: Daniel Henrique Barboza Reviewed-by: Andrew Jones Message-ID: <20230727102439.22554-3-yongxuan.w...@sifive.com> Signed-off-by: Alistair Fra

[PULL 56/65] avocado, risc-v: add tuxboot tests for 'max' CPU

2023-09-07 Thread Alistair Francis
From: Daniel Henrique Barboza Add smoke tests to ensure that we'll not break the 'max' CPU type when adding new frozen/ratified RISC-V extensions. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Reviewed-by: Philippe Mathieu-Daudé Tested-by: Philippe Mathieu-Daudé Messag

Re: [PATCH v4 12/15] vfio/common: Support device dirty page tracking with vIOMMU

2023-09-07 Thread Duan, Zhenzhong
Hi Joao, On 6/23/2023 5:48 AM, Joao Martins wrote: Currently, device dirty page tracking with vIOMMU is not supported, and a blocker is added and the migration is prevented. When vIOMMU is used, IOVA ranges are DMA mapped/unmapped on the fly as requesting by the vIOMMU. These IOVA ranges can po

[PULL 06/65] target/riscv: Fix page_check_range use in fault-only-first

2023-09-07 Thread Alistair Francis
From: LIU Zhiwei Commit bef6f008b98(accel/tcg: Return bool from page_check_range) converts integer return value to bool type. However, it wrongly converted the use of the API in riscv fault-only-first, where page_check_range < = 0, should be converted to !page_check_range. Signed-off-by: LIU Zhi

Re: [PATCH v4 06/15] intel-iommu: Implement get_attr() method

2023-09-07 Thread Duan, Zhenzhong
On 6/23/2023 5:48 AM, Joao Martins wrote: Implement IOMMU MR get_attr() method and use the dma_translation property to report the IOMMU_ATTR_DMA_TRANSLATION attribute. Additionally add the necessary get_iommu_attr into the PCIIOMMUOps to support pci_device_iommu_get_attr(). The callback in the

Re: [PATCH v4 15/15] vfio/common: Block migration with vIOMMUs without address width limits

2023-09-07 Thread Duan, Zhenzhong
On 6/23/2023 5:48 AM, Joao Martins wrote: Only block the case when the underlying vIOMMU model does not report any address space limits, in addition to DMA translation being off or no vIOMMU present. The limits are needed such that can define the IOVA limits that arm the device dirty tracker.

Re: [PULL 00/65] riscv-to-apply queue

2023-09-07 Thread Michael Tokarev
08.09.2023 09:03, Alistair Francis wrote: Akihiko Odaki (1): target/riscv: Allocate itrigger timers only once Ard Biesheuvel (2): target/riscv: Use existing lookup tables for MixColumns target/riscv: Use accelerated helper for AES64KS1I Conor Dooley (1): hw/riscv: v

Re: [PULL v2 00/35] ppc queue

2023-09-07 Thread Michael Tokarev
08.09.2023 07:24, Nicholas Piggin wrote: On Fri Sep 8, 2023 at 8:15 AM AEST, Cédric Le Goater wrote: .. The decrementer fixes are good candidates but there are quite a few patches and you might encounter conflicts. Decrementer I was nervous about since there were quite a lot of interacting is

[PULL 33/65] target/riscv: select KVM AIA in riscv virt machine

2023-09-07 Thread Alistair Francis
From: Yong-Xuan Wang Select KVM AIA when the host kernel has in-kernel AIA chip support. Since KVM AIA only has one APLIC instance, we map the QEMU APLIC devices to KVM APLIC. Signed-off-by: Yong-Xuan Wang Reviewed-by: Jim Shu Reviewed-by: Daniel Henrique Barboza Reviewed-by: Andrew Jones Me

Re: [virtio-dev] [RFC PATCH v2] docs/interop: define PROBE feature for vhost-user VirtIO devices

2023-09-07 Thread Alex Bennée
Stefan Hajnoczi writes: > On Tue, Sep 05, 2023 at 10:34:11AM +0100, Alex Bennée wrote: >> >> Albert Esteve writes: >> >> > This looks great! Thanks for this proposal. >> > >> > On Fri, Sep 1, 2023 at 1:00 PM Alex Bennée wrote: >> > >> > Currently QEMU has to know some details about the Vir

Re: [PATCH v7 5/5] ebpf: Updated eBPF program and skeleton.

2023-09-07 Thread Jason Wang
On Mon, Sep 4, 2023 at 7:23 PM Andrew Melnichenko wrote: > > Hi Jason, > According to our previous conversation, I've added checks to the meson script. > Please confirm that everything is correct I've queued this series. Thanks

[PULL 00/17] Net patches

2023-09-07 Thread Jason Wang
The following changes since commit 03a3a62fbd0aa5227e978eef3c67d3978aec9e5f: Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into staging (2023-09-07 10:29:06 -0400) are available in the git repository at: https://github.com/jasowang/qemu.git tags/net-pull-request for you to fe

[PULL 02/17] tap: Add check for USO features

2023-09-07 Thread Jason Wang
From: Yuri Benditovich Tap indicates support for USO features according to capabilities of current kernel module. Signed-off-by: Yuri Benditovich Signed-off-by: Andrew Melnychecnko Signed-off-by: Jason Wang --- include/net/net.h | 3 +++ net/net.c | 9 + net/tap-bsd.c |

[PULL 06/17] igb: rename E1000E_RingInfo_st

2023-09-07 Thread Jason Wang
From: Tomasz Dzieciol Rename E1000E_RingInfo_st and E1000E_RingInfo according to qemu typdefs guide. Signed-off-by: Tomasz Dzieciol Reviewed-by: Akihiko Odaki Tested-by: Akihiko Odaki Signed-off-by: Jason Wang --- hw/net/e1000e_core.c | 34 +- hw/net/igb_core

[PULL 04/17] virtio-net: Add support for USO features

2023-09-07 Thread Jason Wang
From: Yuri Benditovich USO features of virtio-net device depend on kernel ability to support them, for backward compatibility by default the features are disabled on 8.0 and earlier. Signed-off-by: Yuri Benditovich Signed-off-by: Andrew Melnychecnko Signed-off-by: Jason Wang --- hw/core/mach

[PULL 05/17] igb: remove TCP ACK detection

2023-09-07 Thread Jason Wang
From: Tomasz Dzieciol TCP ACK detection is no longer present in igb. Signed-off-by: Tomasz Dzieciol Reviewed-by: Akihiko Odaki Tested-by: Akihiko Odaki Signed-off-by: Jason Wang --- hw/net/igb_core.c | 5 - 1 file changed, 5 deletions(-) diff --git a/hw/net/igb_core.c b/hw/net/igb_core

[PULL 03/17] virtio-net: Add USO flags to vhost support.

2023-09-07 Thread Jason Wang
From: Andrew Melnychenko New features are subject to check with vhost-user and vdpa. Signed-off-by: Yuri Benditovich Signed-off-by: Andrew Melnychenko Signed-off-by: Jason Wang --- hw/net/vhost_net.c | 3 +++ net/vhost-vdpa.c | 3 +++ 2 files changed, 6 insertions(+) diff --git a/hw/net/v

[PULL 07/17] igb: RX descriptors guest writting refactoring

2023-09-07 Thread Jason Wang
From: Tomasz Dzieciol Refactoring is done in preparation for support of multiple advanced descriptors RX modes, especially packet-split modes. Signed-off-by: Tomasz Dzieciol Reviewed-by: Akihiko Odaki Tested-by: Akihiko Odaki Signed-off-by: Jason Wang --- hw/net/igb_core.c | 170 +

[PULL 12/17] net: add initial support for AF_XDP network backend

2023-09-07 Thread Jason Wang
From: Ilya Maximets AF_XDP is a network socket family that allows communication directly with the network device driver in the kernel, bypassing most or all of the kernel networking stack. In the essence, the technology is pretty similar to netmap. But, unlike netmap, AF_XDP is Linux-native and

[PULL 10/17] igb: packet-split descriptors support

2023-09-07 Thread Jason Wang
From: Tomasz Dzieciol Packet-split descriptors are used by Linux VF driver for MTU values from 2048 Signed-off-by: Tomasz Dzieciol Reviewed-by: Akihiko Odaki Tested-by: Akihiko Odaki Signed-off-by: Jason Wang --- hw/net/igb_core.c | 348 +---

[PULL 16/17] qmp: Added new command to retrieve eBPF blob.

2023-09-07 Thread Jason Wang
From: Andrew Melnychenko Now, the binary objects may be retrieved by id. It would require for future qmp commands that may require specific eBPF blob. Added command "request-ebpf". This command returns eBPF program encoded base64. The program taken from the skeleton and essentially is an ELF obj

[PULL 09/17] igb: add IPv6 extended headers traffic detection

2023-09-07 Thread Jason Wang
From: Tomasz Dzieciol Signed-off-by: Tomasz Dzieciol Reviewed-by: Akihiko Odaki Tested-by: Akihiko Odaki Signed-off-by: Jason Wang --- hw/net/igb_core.c | 4 +++- hw/net/igb_regs.h | 1 + 2 files changed, 4 insertions(+), 1 deletion(-) diff --git a/hw/net/igb_core.c b/hw/net/igb_core.c inde

[PULL 08/17] igb: RX payload guest writting refactoring

2023-09-07 Thread Jason Wang
From: Tomasz Dzieciol Refactoring is done in preparation for support of multiple advanced descriptors RX modes, especially packet-split modes. Signed-off-by: Tomasz Dzieciol Reviewed-by: Akihiko Odaki Tested-by: Akihiko Odaki Signed-off-by: Jason Wang --- hw/net/e1000e_core.c | 18 ++--

[PULL 29/65] target/riscv: support the AIA device emulation with KVM enabled

2023-09-07 Thread Alistair Francis
From: Yong-Xuan Wang In this patch, we create the APLIC and IMSIC FDT helper functions and remove M mode AIA devices when using KVM acceleration. Signed-off-by: Yong-Xuan Wang Reviewed-by: Jim Shu Reviewed-by: Daniel Henrique Barboza Reviewed-by: Andrew Jones Message-ID: <20230727102439.2255

[PULL 01/17] tap: Add USO support to tap device.

2023-09-07 Thread Jason Wang
From: Andrew Melnychenko Passing additional parameters (USOv4 and USOv6 offloads) when setting TAP offloads Signed-off-by: Yuri Benditovich Signed-off-by: Andrew Melnychenko Signed-off-by: Jason Wang --- hw/net/e1000e_core.c | 2 +- hw/net/igb_core.c| 2 +- hw/net/virtio-net.c | 4 ++

[PULL 17/17] ebpf: Updated eBPF program and skeleton.

2023-09-07 Thread Jason Wang
From: Andrew Melnychenko Updated section name, so libbpf should init/gues proper program type without specifications during open/load. Also, added map_flags with explicitly declared BPF_F_MMAPABLE. Added check for BPF_F_MMAPABLE flag to meson script and requirements to libbpf version. Signed-off

[PULL 13/17] ebpf: Added eBPF map update through mmap.

2023-09-07 Thread Jason Wang
From: Andrew Melnychenko Changed eBPF map updates through mmaped array. Mmaped arrays provide direct access to map data. It should omit using bpf_map_update_elem() call, which may require capabilities that are not present. Signed-off-by: Andrew Melnychenko Signed-off-by: Jason Wang --- ebpf/e

[PULL 15/17] virtio-net: Added property to load eBPF RSS with fds.

2023-09-07 Thread Jason Wang
From: Andrew Melnychenko eBPF RSS program and maps may now be passed during initialization. Initially was implemented for libvirt to launch qemu without permissions, and initialized eBPF program through the helper. Signed-off-by: Andrew Melnychenko Signed-off-by: Jason Wang --- hw/net/virtio-

[PULL 14/17] ebpf: Added eBPF initialization by fds.

2023-09-07 Thread Jason Wang
From: Andrew Melnychenko It allows using file descriptors of eBPF provided outside of QEMU. QEMU may be run without capabilities for eBPF and run RSS program provided by management tool(g.e. libvirt). Signed-off-by: Andrew Melnychenko Signed-off-by: Jason Wang --- ebpf/ebpf_rss-stub.c | 6 ++

[PULL 11/17] e1000e: rename e1000e_ba_state and e1000e_write_hdr_to_rx_buffers

2023-09-07 Thread Jason Wang
From: Tomasz Dzieciol Rename e1000e_ba_state according and e1000e_write_hdr_to_rx_buffers for consistency with IGB. Signed-off-by: Tomasz Dzieciol Reviewed-by: Akihiko Odaki Tested-by: Akihiko Odaki Signed-off-by: Jason Wang --- hw/net/e1000e_core.c | 28 +++- 1 file

Re: [PATCH v8 11/12] virtio-sound: implement audio capture (RX)

2023-09-07 Thread Volker Rümelin
Am 28.08.23 um 21:55 schrieb Emmanouil Pitsidianakis: To perform audio capture we duplicate the TX logic of the previous commit with the following difference: we receive data from the QEMU audio backend and write it in the virt queue IO buffers the guest sends to QEMU. When they are full (i.e. th

[PULL 60/65] target/riscv/cpu.c: introduce cpu_cfg_ext_auto_update()

2023-09-07 Thread Alistair Francis
From: Daniel Henrique Barboza During realize() time we're activating a lot of extensions based on some criteria, e.g.: if (cpu->cfg.ext_zk) { cpu->cfg.ext_zkn = true; cpu->cfg.ext_zkr = true; cpu->cfg.ext_zkt = true; } This practice resulted in at least one case

Re: [PATCH 05/21] q800: add IOSB subsystem

2023-09-07 Thread Mark Cave-Ayland
On 07/07/2023 09:25, Philippe Mathieu-Daudé wrote: On 2/7/23 17:48, Mark Cave-Ayland wrote: It is needed because it defines the BIOSConfig area. Co-developed-by: Laurent Vivier Signed-off-by: Mark Cave-Ayland ---   MAINTAINERS    |   2 +   hw/m68k/Kconfig    |   1 +   hw/m68k/q80

Re: [PATCH 10/21] q800: add easc bool machine class property to switch between ASC and EASC

2023-09-07 Thread Mark Cave-Ayland
On 07/07/2023 09:29, Philippe Mathieu-Daudé wrote: On 2/7/23 17:48, Mark Cave-Ayland wrote: This determines whether the Apple Sound Chip (ASC) is set to enhanced mode (default) or to original mode. The real Q800 hardware used an EASC chip however a lot of older software only works with the olde

[PULL 41/65] target/riscv: Use accelerated helper for AES64KS1I

2023-09-07 Thread Alistair Francis
From: Ard Biesheuvel Use the accelerated SubBytes/ShiftRows/AddRoundKey AES helper to implement the first half of the key schedule derivation. This does not actually involve shifting rows, so clone the same value into all four columns of the AES vector to counter that operation. Cc: Richard Hend

[PULL 59/65] target/riscv: make CPUCFG() macro public

2023-09-07 Thread Alistair Francis
From: Daniel Henrique Barboza The RISC-V KVM driver uses a CPUCFG() macro that calculates the offset of a certain field in the struct RISCVCPUConfig. We're going to use this macro in target/riscv/cpu.c as well in the next patches. Make it public. Rename it to CPU_CFG_OFFSET() for more clarity wh

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