Re: [PATCH] hw/display/xlnx_dp: update comments

07.09.2023 23:34, Michael Tokarev wrote: --- a/hw/display/xlnx_dp.c +++ b/hw/display/xlnx_dp.c @@ -1,4 +1,4 @@ -/* +?* * Xilinx Display Port Without this glitch ofc, - already fixed. /mjt

[PATCH v3 1/2] block: add BDRV_BLOCK_COMPRESSED flag for bdrv_block_status()

Functions qcow2_get_host_offset(), get_cluster_offset(), vmdk_co_block_status() explicitly report compressed cluster types when data is compressed. However, this information is never passed further. Let's make use of it by adding new BDRV_BLOCK_COMPRESSED flag for bdrv_block_status(), so that cal

[PATCH v3 0/2] qemu-img: map: implement support for compressed clusters

v2 --> v3: * Make "compressed" field mandatory, not optional; * Adjust field description in qapi/block-core.json; * Squash patch 3 into patch 2 so that failing tests don't break bisect; * Update even more tests' outputs now that the field is mandatory. v2: https://lists.nongnu.org/archive/

Re: [RFC 1/3] hmp: avoid the nested event loop in handle_hmp_command()

On Thu, 7 Sept 2023 at 16:53, Dr. David Alan Gilbert wrote: > > * Stefan Hajnoczi (stefa...@gmail.com) wrote: > > On Thu, 7 Sept 2023 at 10:07, Dr. David Alan Gilbert > > wrote: > > > > > > * Stefan Hajnoczi (stefa...@redhat.com) wrote: > > > > On Thu, Sep 07, 2023 at 01:06:39AM +, Dr. David

Re: [PATCH 2/8] qemu-nbd: define struct NbdClientOpts when HAVE_NBD_DEVICE is not defined

On Wed, Sep 06, 2023 at 11:32:04AM +0200, Denis V. Lunev wrote: > This patch also drops definition of some locals in main() to avoid > useless data copy. > > Signed-off-by: Denis V. Lunev > CC: Eric Blake > CC: Vladimir Sementsov-Ogievskiy > --- > qemu-nbd.c | 60 --

Re: [PATCH 3/8] qemu-nbd: move srcpath into struct NbdClientOpts

On Wed, Sep 06, 2023 at 11:32:05AM +0200, Denis V. Lunev wrote: > We pass other parameters into nbd_client_thread() in this way. This patch > makes the code more consistent. > > Signed-off-by: Denis V. Lunev > CC: Eric Blake > CC: Vladimir Sementsov-Ogievskiy > --- > qemu-nbd.c | 17 +-

Re: [PATCH 4/8] qemu-nbd: put saddr into into struct NbdClientOpts

On Wed, Sep 06, 2023 at 11:32:06AM +0200, Denis V. Lunev wrote: > We pass other parameters into nbd_client_thread() in this way. This patch > makes the code more consistent. > > Signed-off-by: Denis V. Lunev > CC: Eric Blake > CC: Vladimir Sementsov-Ogievskiy > --- > qemu-nbd.c | 13 +++---

[PATCH 1/1] block: improve alignment detection and fix 271 test

Unfortunately 271 IO test is broken if started in non-cached mode. Commits commit a6b257a08e3d72219f03e461a52152672fec0612 Author: Nir Soffer Date: Tue Aug 13 21:21:03 2019 +0300 file-posix: Handle undetectable alignment and commit 9c60a5d1978e6dcf85c0e01b50e6f7f54ca09104

Re: [PATCH 5/8] qemu-nbd: invent nbd_client_release_pipe() helper

On Wed, Sep 06, 2023 at 11:32:07AM +0200, Denis V. Lunev wrote: > Move the code from main() and nbd_client_thread() into the specific > helper. This code is going to be grown. > > Signed-off-by: Denis V. Lunev > CC: Eric Blake > CC: Vladimir Sementsov-Ogievskiy > --- > qemu-nbd.c | 23

Re: [PATCH 6/8] qemu-nbd: Restore "qemu-nbd -v --fork" output

On Wed, Sep 06, 2023 at 11:32:08AM +0200, Denis V. Lunev wrote: > Closing stderr earlier is good for daemonized qemu-nbd under ssh > earlier, but breaks the case where -v is being used to track what is > happening in the server, as in iotest 233. > > When we know we are verbose, we should preserve

Re: [PATCH 7/8] qemu-nbd: document -v behavior in respect to --fork in man

On Wed, Sep 06, 2023 at 11:32:09AM +0200, Denis V. Lunev wrote: > Signed-off-by: Denis V. Lunev > CC: Eric Blake > CC: Vladimir Sementsov-Ogievskiy > --- > docs/tools/qemu-nbd.rst | 4 +++- > 1 file changed, 3 insertions(+), 1 deletion(-) > > diff --git a/docs/tools/qemu-nbd.rst b/docs/tools/q

Re: [PATCH 7/8] qemu-nbd: document -v behavior in respect to --fork in man

On 9/8/23 00:01, Eric Blake wrote: On Wed, Sep 06, 2023 at 11:32:09AM +0200, Denis V. Lunev wrote: Signed-off-by: Denis V. Lunev CC: Eric Blake CC: Vladimir Sementsov-Ogievskiy --- docs/tools/qemu-nbd.rst | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/docs/tools/qem

[PATCH v2 4/3] qemu-iotests/197: use more generic commands for formats other than qcow2

In the previous commit e2f938265e0 ("tests/qemu-iotests/197: add testcase for CoR with subclusters") we've introduced a new testcase for copy-on-read with subclusters. Test 197 always forces qcow2 as the top image, but allows backing image to be in any format. That last test case didn't meet thes

Re: [PATCH v2 3/3] tests/qemu-iotests/197: add testcase for CoR with subclusters

On 9/6/23 12:43, Denis V. Lunev wrote: > On 7/11/23 19:25, Andrey Drobyshev wrote: >> Add testcase which checks that allocations during copy-on-read are >> performed on the subcluster basis when subclusters are enabled in target >> image. >> >> This testcase also triggers the following assert with

Re: [PATCH v2 0/3] block: align CoR requests to subclusters

On 9/7/23 22:11, Michael Tokarev wrote: 11.07.2023 20:25, Andrey Drobyshev via wrote: v1 --> v2:   * Fixed line indentation;   * Fixed wording in a comment;   * Added R-b. v1: https://lists.nongnu.org/archive/html/qemu-block/2023-06/msg00606.html Andrey Drobyshev (3):    block: add subcluste

Re: [PATCH 8/8] qemu-nbd: fix formatting in main()

On Wed, Sep 06, 2023 at 11:32:10AM +0200, Denis V. Lunev wrote: > Just a formatting, no functional changes. > > Signed-off-by: Denis V. Lunev > CC: Eric Blake > CC: Vladimir Sementsov-Ogievskiy > --- > Do not really sure that this patch is mandatory, just stabs my eye. Feel free > to drop if th

Re: [PULL v2 00/35] ppc queue

On 9/7/23 21:10, Michael Tokarev wrote: 06.09.2023 17:36, Cédric Le Goater wrote: ... ppc queue : * debug facility improvements * timebase and decrementer fixes * record-replay fixes * TCG fixes * XIVE model improvements for multichip ---

Re: [PATCH v3 01/32] cpu: Add helper cpu_model_from_type()

On 9/7/23 18:54, Philippe Mathieu-Daudé wrote: On 7/9/23 02:35, Gavin Shan wrote: Add helper cpu_model_from_type() to extract the CPU model name from the CPU type name in two circumstances: (1) The CPU type name is the combination of the CPU model name and suffix. (2) The CPU type name is same t

Re: [PATCH v3 15/32] target/s390x: Use generic helper to show CPU model names

On 9/7/23 18:31, Thomas Huth wrote: On 07/09/2023 02.35, Gavin Shan wrote: For target/s390x, the CPU type name is always the combination of the CPU modle name and suffix. The CPU model names have been correctly s/modle/model/ Thanks, will be fixed in next respin. Thanks, Gavin

Re: [PATCH v3 15/32] target/s390x: Use generic helper to show CPU model names

On 9/7/23 18:20, David Hildenbrand wrote: On 07.09.23 02:35, Gavin Shan wrote: For target/s390x, the CPU type name is always the combination of the CPU modle name and suffix. The CPU model names have been correctly shown in s390_print_cpu_model_list_entry() and create_cpu_model_list(). Use ge

Re: riscv64 virt board crash upon startup

Question for Gerd below: On 9/7/23 14:29, Philippe Mathieu-Daudé wrote: > On 7/9/23 13:25, Laszlo Ersek wrote: >> This is with QEMU v8.1.0-391-gc152379422a2. >> >> I use the command line from (scroll to the bottom): >> >>    https://github.com/tianocore/edk2/commit/49f06b664018 >> >> (with "-full-

Re: [PATCH v3 27/32] machine: Print CPU model name instead of CPU type name

On 9/7/23 19:05, Philippe Mathieu-Daudé wrote: On 7/9/23 02:35, Gavin Shan wrote: The names of supported CPU models instead of CPU types should be printed when the user specified CPU type isn't supported, to be consistent with the output from '-cpu ?'. Correct the error messages to print CPU mo

Re: riscv64 virt board crash upon startup

On 9/8/23 01:47, Laszlo Ersek wrote: > I don't know why qemu_console_is_multihead() used a lot of QOM > trickery for this in the first place, but here's what I'd propose as > fix -- simply try to locate a QemuGraphicConsole in "consoles" that > references the same "device" that *this* QemuGraphicC

Re: [PATCH v2 4/3] qemu-iotests/197: use more generic commands for formats other than qcow2

On Fri, Sep 08, 2023 at 01:07:18AM +0300, Andrey Drobyshev via wrote: > In the previous commit e2f938265e0 ("tests/qemu-iotests/197: add > testcase for CoR with subclusters") we've introduced a new testcase for > copy-on-read with subclusters. Test 197 always forces qcow2 as the top > image, but a

Re: [PATCH] hw/riscv: split RAM into low and high memory

On 9/7/2023 11:46 PM, Anup Patel wrote: > On Tue, Aug 1, 2023 at 4:16 AM Daniel Henrique Barboza > wrote: >> >> >> >> On 7/30/23 22:53, Fei Wu wrote: >>> riscv virt platform's memory started at 0x8000 and >>> straddled the 4GiB boundary. Curiously enough, this choice >>> of a memory layout wil

Re: [PATCH] softmmu/dirtylimit: Fix usleep early return on signal

On 2023/9/4 21:27, Yong Huang wrote: On Fri, Sep 1, 2023 at 10:19 AM > wrote: From: alloc mailto:alloc.yo...@outlook.com>> Timeout functions like usleep can return early on signal, which reduces more dirty pages than expected. In dirtylimit case

[PULL 11/13] qemu-nbd: invent nbd_client_release_pipe() helper

From: "Denis V. Lunev" Move the code from main() and nbd_client_thread() into the specific helper. This code is going to be grown. Signed-off-by: Denis V. Lunev CC: Eric Blake CC: Vladimir Sementsov-Ogievskiy Message-ID: <20230906093210.339585-6-...@openvz.org> Reviewed-by: Eric Blake Signed

[PULL 04/13] io: check there are no qio_channel_yield() coroutines during ->finalize()

From: Stefan Hajnoczi Callers must clean up their coroutines before calling object_unref(OBJECT(ioc)) to prevent an fd handler leak. Add an assertion to check this. This patch is preparation for the fd handler changes that follow. Signed-off-by: Stefan Hajnoczi Reviewed-by: Daniel P. Berrangé

[PULL 07/13] qemu-nbd: improve error message for dup2 error

From: "Denis V. Lunev" This error happens if we are not able to close the pipe to the parent (to trace errors in the child process) and assign stderr to /dev/null as required by the daemonizing convention. Signed-off-by: Denis V. Lunev Suggested-by: Eric Blake CC: Eric Blake CC: Vladimir Seme

[PULL 13/13] qemu-nbd: document -v behavior in respect to --fork in man

From: "Denis V. Lunev" Signed-off-by: Denis V. Lunev CC: Eric Blake CC: Vladimir Sementsov-Ogievskiy Message-ID: <20230906093210.339585-8-...@openvz.org> Reviewed-by: Eric Blake [eblake: Wording improvement] Signed-off-by: Eric Blake --- docs/tools/qemu-nbd.rst | 4 +++- 1 file changed, 3 i

[PULL 03/13] nbd: drop unused nbd_start_negotiate() aio_context argument

From: Stefan Hajnoczi aio_context is always NULL, so drop it. Suggested-by: Fabiano Rosas Signed-off-by: Stefan Hajnoczi Reviewed-by: Eric Blake Reviewed-by: Philippe Mathieu-Daudé Message-ID: <20230830224802.493686-3-stefa...@redhat.com> Signed-off-by: Eric Blake --- nbd/client.c | 11 +++

[PULL 02/13] nbd: drop unused nbd_receive_negotiate() aio_context argument

From: Stefan Hajnoczi aio_context is always NULL, so drop it. Suggested-by: Fabiano Rosas Signed-off-by: Stefan Hajnoczi Reviewed-by: Eric Blake Reviewed-by: Philippe Mathieu-Daudé Message-ID: <20230830224802.493686-2-stefa...@redhat.com> Signed-off-by: Eric Blake --- include/block/nbd.h

[PULL 09/13] qemu-nbd: move srcpath into struct NbdClientOpts

From: "Denis V. Lunev" We pass other parameters into nbd_client_thread() in this way. This patch makes the code more consistent. Signed-off-by: Denis V. Lunev CC: Eric Blake CC: Vladimir Sementsov-Ogievskiy Message-ID: <20230906093210.339585-4-...@openvz.org> Reviewed-by: Eric Blake [eblake:

[PULL 01/13] qemu-iotests/197: use more generic commands for formats other than qcow2

From: Andrey Drobyshev In the previous commit e2f938265e0 ("tests/qemu-iotests/197: add testcase for CoR with subclusters") we've introduced a new testcase for copy-on-read with subclusters. Test 197 always forces qcow2 as the top image, but allows backing image to be in any format. That last t

[PULL 05/13] io: follow coroutine AioContext in qio_channel_yield()

From: Stefan Hajnoczi The ongoing QEMU multi-queue block layer effort makes it possible for multiple threads to process I/O in parallel. The nbd block driver is not compatible with the multi-queue block layer yet because QIOChannel cannot be used easily from coroutines running in multiple threads

[PULL 10/13] qemu-nbd: put saddr into into struct NbdClientOpts

From: "Denis V. Lunev" We pass other parameters into nbd_client_thread() in this way. This patch makes the code more consistent. Signed-off-by: Denis V. Lunev CC: Eric Blake CC: Vladimir Sementsov-Ogievskiy Message-ID: <20230906093210.339585-5-...@openvz.org> Reviewed-by: Eric Blake Signed-o

[PULL 00/13] NBD patches through 2023-09-07

The following changes since commit 03a3a62fbd0aa5227e978eef3c67d3978aec9e5f: Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into staging (2023-09-07 10:29:06 -0400) are available in the Git repository at: https://repo.or.cz/qemu/ericb.git tags/pull-nbd-2023-09-07 for you to fe

[PULL 12/13] qemu-nbd: Restore "qemu-nbd -v --fork" output

From: "Denis V. Lunev" Closing stderr earlier is good for daemonized qemu-nbd under ssh earlier, but breaks the case where -v is being used to track what is happening in the server, as in iotest 233. When we know we are verbose, we should preserve original stderr and restore it once the setup st

[PULL 06/13] util/iov: Avoid dynamic stack allocation

From: Philippe Mathieu-Daudé Use autofree heap allocation instead of variable-length array on the stack. The codebase has very few VLAs, and if we can get rid of them all we can make the compiler error on new additions. This is a defensive measure against security bugs where an on-stack dynamic

[PULL 08/13] qemu-nbd: define struct NbdClientOpts when HAVE_NBD_DEVICE is not defined

From: "Denis V. Lunev" This patch also drops definition of some locals in main() to avoid useless data copy. Signed-off-by: Denis V. Lunev CC: Eric Blake CC: Vladimir Sementsov-Ogievskiy Message-ID: <20230906093210.339585-3-...@openvz.org> Reviewed-by: Eric Blake Signed-off-by: Eric Blake -

[PATCH v4 07/16] tcg/loongarch64: Lower neg_vec to vneg

Signed-off-by: Jiajie Chen Reviewed-by: Richard Henderson --- tcg/loongarch64/tcg-target.c.inc | 8 tcg/loongarch64/tcg-target.h | 2 +- 2 files changed, 9 insertions(+), 1 deletion(-) diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg-target.c.inc index d569e443dd

[PATCH v4 09/16] tcg/loongarch64: Lower vector min max ops

Lower the following ops: - smin_vec - smax_vec - umin_vec - umax_vec Signed-off-by: Jiajie Chen Reviewed-by: Richard Henderson --- tcg/loongarch64/tcg-target.c.inc | 32 tcg/loongarch64/tcg-target.h | 2 +- 2 files changed, 33 insertions(+), 1 deletion(-)

[PATCH v4 05/16] tcg/loongarch64: Lower add/sub_vec to vadd/vsub

Lower the following ops: - add_vec - sub_vec Signed-off-by: Jiajie Chen --- tcg/loongarch64/tcg-target-con-set.h | 1 + tcg/loongarch64/tcg-target-con-str.h | 1 + tcg/loongarch64/tcg-target.c.inc | 61 3 files changed, 63 insertions(+) diff --git a/tcg/loong

[PATCH v4 16/16] tcg/loongarch64: Implement 128-bit load & store

If LSX is available, use LSX instructions to implement 128-bit load & store when MO_128 is required, otherwise use two 64-bit loads & stores. Signed-off-by: Jiajie Chen --- tcg/loongarch64/tcg-target-con-set.h | 2 + tcg/loongarch64/tcg-target.c.inc | 59 tcg/lo

[PATCH v4 14/16] tcg/loongarch64: Lower rotv_vec ops to LSX

Lower the following ops: - rotrv_vec - rotlv_vec Signed-off-by: Jiajie Chen Reviewed-by: Richard Henderson --- tcg/loongarch64/tcg-target.c.inc | 14 ++ tcg/loongarch64/tcg-target.h | 2 +- 2 files changed, 15 insertions(+), 1 deletion(-) diff --git a/tcg/loongarch64/tcg-targ

[PATCH v4 00/16] Lower TCG vector ops to LSX

This patch series allows qemu to utilize LSX instructions on LoongArch machines to execute TCG vector ops. Passed tcg tests with x86_64 and aarch64 cross compilers. Changes since v3: - Refactor add/sub_vec handling code to use a helper function - Only use vldx/vstx for MO_128 load/store, otherwi

[PATCH v4 11/16] tcg/loongarch64: Lower vector shift vector ops

Lower the following ops: - shlv_vec - shrv_vec - sarv_vec Signed-off-by: Jiajie Chen Reviewed-by: Richard Henderson --- tcg/loongarch64/tcg-target.c.inc | 24 tcg/loongarch64/tcg-target.h | 2 +- 2 files changed, 25 insertions(+), 1 deletion(-) diff --git a/tcg/l

[PATCH v4 06/16] tcg/loongarch64: Lower vector bitwise operations

Lower the following ops: - and_vec - andc_vec - or_vec - orc_vec - xor_vec - nor_vec - not_vec Signed-off-by: Jiajie Chen Reviewed-by: Richard Henderson --- tcg/loongarch64/tcg-target-con-set.h | 2 ++ tcg/loongarch64/tcg-target.c.inc | 44 tcg/loongarch64/tcg

[PATCH v4 08/16] tcg/loongarch64: Lower mul_vec to vmul

Signed-off-by: Jiajie Chen Reviewed-by: Richard Henderson --- tcg/loongarch64/tcg-target.c.inc | 8 tcg/loongarch64/tcg-target.h | 2 +- 2 files changed, 9 insertions(+), 1 deletion(-) diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg-target.c.inc index b36b706e39

[PATCH v4 04/16] tcg/loongarch64: Lower cmp_vec to vseq/vsle/vslt

Signed-off-by: Jiajie Chen Reviewed-by: Richard Henderson --- tcg/loongarch64/tcg-target-con-set.h | 1 + tcg/loongarch64/tcg-target-con-str.h | 1 + tcg/loongarch64/tcg-target.c.inc | 65 3 files changed, 67 insertions(+) diff --git a/tcg/loongarch64/tcg-targ

[PATCH v4 13/16] tcg/loongarch64: Lower vector shift integer ops

Lower the following ops: - shli_vec - shrv_vec - sarv_vec Signed-off-by: Jiajie Chen Reviewed-by: Richard Henderson --- tcg/loongarch64/tcg-target.c.inc | 21 + tcg/loongarch64/tcg-target.h | 2 +- 2 files changed, 22 insertions(+), 1 deletion(-) diff --git a/tcg/loon

[PATCH v4 15/16] tcg/loongarch64: Lower rotli_vec to vrotri

Signed-off-by: Jiajie Chen Reviewed-by: Richard Henderson --- tcg/loongarch64/tcg-target.c.inc | 21 + tcg/loongarch64/tcg-target.h | 2 +- 2 files changed, 22 insertions(+), 1 deletion(-) diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg-target.c.inc

[PATCH v4 03/16] tcg: pass vece to tcg_target_const_match()

Pass vece to tcg_target_const_match() to allow correct interpretation of const args of vector ops. Signed-off-by: Jiajie Chen Reviewed-by: Richard Henderson --- tcg/aarch64/tcg-target.c.inc | 2 +- tcg/arm/tcg-target.c.inc | 2 +- tcg/i386/tcg-target.c.inc| 2 +- tcg/loongar

[PATCH v4 12/16] tcg/loongarch64: Lower bitsel_vec to vbitsel

Signed-off-by: Jiajie Chen Reviewed-by: Richard Henderson --- tcg/loongarch64/tcg-target-con-set.h | 1 + tcg/loongarch64/tcg-target.c.inc | 11 ++- tcg/loongarch64/tcg-target.h | 2 +- 3 files changed, 12 insertions(+), 2 deletions(-) diff --git a/tcg/loongarch64/tcg-targ

[PATCH v4 10/16] tcg/loongarch64: Lower vector saturated ops

Lower the following ops: - ssadd_vec - usadd_vec - sssub_vec - ussub_vec Signed-off-by: Jiajie Chen Reviewed-by: Richard Henderson --- tcg/loongarch64/tcg-target.c.inc | 32 tcg/loongarch64/tcg-target.h | 2 +- 2 files changed, 33 insertions(+), 1 deletion

[PATCH v4 02/16] tcg/loongarch64: Lower basic tcg vec ops to LSX

LSX support on host cpu is detected via hwcap. Lower the following ops to LSX: - dup_vec - dupi_vec - dupm_vec - ld_vec - st_vec Signed-off-by: Jiajie Chen Reviewed-by: Richard Henderson --- tcg/loongarch64/tcg-target-con-set.h | 2 + tcg/loongarch64/tcg-target-con-str.h | 1 + tcg/loonga

Re: [PATCH RESEND v5 02/57] target/loongarch: Implement gvec_*_vl functions

在 2023/9/8 上午1:19, Richard Henderson 写道: On 9/7/23 01:31, Song Gao wrote: Using gvec_*_vl functions hides oprsz. We can use gvec_v* for oprsz 16. and gvec_v* for oprsz 32. Signed-off-by: Song Gao ---   target/loongarch/insn_trans/trans_vec.c.inc | 68 +   1 file changed, 44 i

Re: [PATCH RESEND v5 03/57] target/loongarch: Use gen_helper_gvec_4_ptr for 4OP + env vector instructions

在 2023/9/8 上午1:34, Richard Henderson 写道: On 9/7/23 01:31, Song Gao wrote: +static bool gen__ptr_vl(DisasContext *ctx, arg_ *a, uint32_t oprsz, +    gen_helper_gvec_4_ptr *fn) +{ +    tcg_gen_gvec_4_ptr(vec_full_offset(a->vd), +   vec_full_offs

[PATCH] qemu/timer: Add host ticks function for RISC-V

From: LIU Zhiwei Signed-off-by: LIU Zhiwei --- include/qemu/timer.h | 19 +++ 1 file changed, 19 insertions(+) diff --git a/include/qemu/timer.h b/include/qemu/timer.h index 9a91cb1248..ce0b66d122 100644 --- a/include/qemu/timer.h +++ b/include/qemu/timer.h @@ -979,6 +979,25 @@

[RESEND] qemu/timer: Add host ticks function for RISC-V

From: LIU Zhiwei Signed-off-by: LIU Zhiwei --- include/qemu/timer.h | 19 +++ 1 file changed, 19 insertions(+) diff --git a/include/qemu/timer.h b/include/qemu/timer.h index 9a91cb1248..105767c195 100644 --- a/include/qemu/timer.h +++ b/include/qemu/timer.h @@ -979,6 +979,25 @@

Re: [PULL v2 00/35] ppc queue

On Fri Sep 8, 2023 at 8:15 AM AEST, Cédric Le Goater wrote: > On 9/7/23 21:10, Michael Tokarev wrote: > > 06.09.2023 17:36, Cédric Le Goater wrote: > > ... > >> ppc queue : > >> > >> * debug facility improvements > >> * timebase and decrementer fixes > >> * record-replay fixes > >> * TCG fixes > >>

[PULL 03/65] hw/char/riscv_htif: Fix the console syscall on big endian hosts

From: Thomas Huth Values that have been read via cpu_physical_memory_read() from the guest's memory have to be swapped in case the host endianess differs from the guest. Fixes: a6e13e31d5 ("riscv_htif: Support console output via proxy syscall") Signed-off-by: Thomas Huth Reviewed-by: Alistair F

[PULL 02/65] hw/char/riscv_htif: Fix printing of console characters on big endian hosts

From: Thomas Huth The character that should be printed is stored in the 64 bit "payload" variable. The code currently tries to print it by taking the address of the variable and passing this pointer to qemu_chr_fe_write(). However, this only works on little endian hosts where the least significan

[PULL 01/65] target/riscv/cpu.c: do not run 'host' CPU with TCG

From: Daniel Henrique Barboza The 'host' CPU is available in a CONFIG_KVM build and it's currently available for all accels, but is a KVM only CPU. This means that in a RISC-V KVM capable host we can do things like this: $ ./build/qemu-system-riscv64 -M virt,accel=tcg -cpu host --nographic qemu-

[PULL 12/65] target/riscv: Move vector translation checks

From: Nazar Kazakov Move the checks out of `do_opiv{v,x,i}_gvec{,_shift}` functions and into the corresponding macros. This enables the functions to be reused in proceeding commits without check duplication. Signed-off-by: Nazar Kazakov Reviewed-by: Richard Henderson Reviewed-by: Weiwei Li Si

[PULL 00/65] riscv-to-apply queue

The following changes since commit 03a3a62fbd0aa5227e978eef3c67d3978aec9e5f: Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into staging (2023-09-07 10:29:06 -0400) are available in the Git repository at: https://github.com/alistair23/qemu.git tags/pull-riscv-to-apply-20230908

[PULL 10/65] target/riscv: Remove redundant "cpu_vl == 0" checks

From: Nazar Kazakov Remove the redundant "vl == 0" check which is already included within the vstart >= vl check, when vl == 0. Signed-off-by: Nazar Kazakov Reviewed-by: Weiwei Li Signed-off-by: Max Chou Acked-by: Alistair Francis Message-ID: <20230711165917.2629866-4-max.c...@sifive.com>

[PULL 14/65] target/riscv: Refactor some of the generic vector functionality

From: Kiran Ostrolenk Move some macros out of `vector_helper` and into `vector_internals`. This ensures they can be used by both vector and vector-crypto helpers (latter implemented in proceeding commits). Signed-off-by: Kiran Ostrolenk Reviewed-by: Weiwei Li Signed-off-by: Max Chou Message-I

[PULL 25/65] target/riscv: Fix zfa fleq.d and fltq.d

From: LIU Zhiwei Commit a47842d ("riscv: Add support for the Zfa extension") implemented the zfa extension. However, it has some typos for fleq.d and fltq.d. Both of them misused the fltq.s helper function. Fixes: a47842d ("riscv: Add support for the Zfa extension") Signed-off-by: LIU Zhiwei

[PULL 35/65] target/riscv: Update CSR bits name for svadu extension

From: Weiwei Li The Svadu specification updated the name of the *envcfg bit from HADE to ADUE. Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Daniel Henrique Barboza Message-ID: <20230816141916.66898-1-liwei...@iscas.ac.cn> Signed-off-by: Alistair Francis --- target/risc

[PULL 24/65] target/riscv: Add Zihintntl extension ISA string to DTS

From: Jason Chien RVA23 Profiles states: The RVA23 profiles are intended to be used for 64-bit application processors that will run rich OS stacks from standard binary OS distributions and with a substantial number of third-party binary user applications that will be supported over a considerable

[PULL 27/65] hw/intc: Make rtc variable names consistent

From: Jason Chien The variables whose values are given by cpu_riscv_read_rtc() should be named "rtc". The variables whose value are given by cpu_riscv_read_rtc_raw() should be named "rtc_r". Signed-off-by: Jason Chien Reviewed-by: Alistair Francis Message-ID: <20230728082502.26439-2-jason.ch..

[PULL 07/65] target/riscv: Use existing lookup tables for MixColumns

From: Ard Biesheuvel The AES MixColumns and InvMixColumns operations are relatively expensive 4x4 matrix multiplications in GF(2^8), which is why C implementations usually rely on precomputed lookup tables rather than performing the calculations on demand. Given that we already carry those table

[PULL 11/65] target/riscv: Add Zvbc ISA extension support

From: Lawrence Hunter This commit adds support for the Zvbc vector-crypto extension, which consists of the following instructions: * vclmulh.[vx,vv] * vclmul.[vx,vv] Translation functions are defined in `target/riscv/insn_trans/trans_rvvk.c.inc` and helpers are defined in `target/riscv/vcrypto_

[PULL 36/65] target/riscv: fix satp_mode_finalize() when satp_mode.supported = 0

From: Daniel Henrique Barboza In the same emulated RISC-V host, the 'host' KVM CPU takes 4 times longer to boot than the 'rv64' KVM CPU. The reason is an unintended behavior of riscv_cpu_satp_mode_finalize() when satp_mode.supported = 0, i.e. when cpu_init() does not set satp_mode_max_supported(

[PULL 15/65] target/riscv: Add Zvbb ISA extension support

From: Dickon Hood This commit adds support for the Zvbb vector-crypto extension, which consists of the following instructions: * vrol.[vv,vx] * vror.[vv,vx,vi] * vbrev8.v * vrev8.v * vandn.[vv,vx] * vbrev.v * vclz.v * vctz.v * vcpop.v * vwsll.[vv,vx,vi] Translation functions are defined in `tar

[PULL 23/65] target/riscv: Implement WARL behaviour for mcountinhibit/mcounteren

From: Rob Bradford These are WARL fields - zero out the bits for unavailable counters and special case the TM bit in mcountinhibit which is hardwired to zero. This patch achieves this by modifying the value written so that any use of the field will see the correctly masked bits. Tested by modify

[PULL 39/65] hw/intc/riscv_aplic.c fix non-KVM --enable-debug build

From: Daniel Henrique Barboza Commit 6df0b37e2ab breaks a --enable-debug build in a non-KVM environment with the following error: /usr/bin/ld: libqemu-riscv64-softmmu.fa.p/hw_intc_riscv_aplic.c.o: in function `riscv_kvm_aplic_request': ./qemu/build/../hw/intc/riscv_aplic.c:486: undefined refere

[PULL 17/65] target/riscv: Add Zvknh ISA extension support

From: Kiran Ostrolenk This commit adds support for the Zvknh vector-crypto extension, which consists of the following instructions: * vsha2ms.vv * vsha2c[hl].vv Translation functions are defined in `target/riscv/insn_trans/trans_rvvk.c.inc` and helpers are defined in `target/riscv/vcrypto_helpe

[PULL 19/65] target/riscv: Add Zvkg ISA extension support

From: Nazar Kazakov This commit adds support for the Zvkg vector-crypto extension, which consists of the following instructions: * vgmul.vv * vghsh.vv Translation functions are defined in `target/riscv/insn_trans/trans_rvvk.c.inc` and helpers are defined in `target/riscv/vcrypto_helper.c`. Co-

[PULL 50/65] target/riscv/cpu.c: split non-ratified exts from riscv_cpu_extensions[]

From: Daniel Henrique Barboza Create a new riscv_cpu_experimental_exts[] to store the non-ratified extensions properties. Once they are ratified we'll move them back to riscv_cpu_extensions[]. riscv_cpu_add_user_properties() and riscv_cpu_add_kvm_properties() are changed to keep adding non-ratif

[PULL 57/65] target/riscv: deprecate the 'any' CPU type

From: Daniel Henrique Barboza The 'any' CPU type was introduced in commit dc5bd18fa5725 ("RISC-V CPU Core Definition"), being around since the beginning. It's not an easy CPU to use: it's undocumented and its name doesn't tell users much about what the CPU is supposed to bring. 'git log' doesn't

[PULL 45/65] target/riscv: don't read CSR in riscv_csrrw_do64

From: Nikita Shubin As per ISA: "For CSRRWI, if rd=x0, then the instruction shall not read the CSR and shall not cause any of the side effects that might occur on a CSR read." trans_csrrwi() and trans_csrrw() call do_csrw() if rd=x0, do_csrw() calls riscv_csrrw_do64(), via helper_csrw() passing

[PULL 48/65] target/riscv/cpu.c: split kvm prop handling to its own helper

From: Daniel Henrique Barboza Future patches will split the existing Property arrays even further, and the existing code in riscv_cpu_add_user_properties() will start to scale bad with it because it's dealing with KVM constraints mixed in with TCG constraints. We're going to pay a high price to s

[PULL 08/65] target/riscv: Refactor some of the generic vector functionality

From: Kiran Ostrolenk Take some functions/macros out of `vector_helper` and put them in a new module called `vector_internals`. This ensures they can be used by both vector and vector-crypto helpers (latter implemented in proceeding commits). Signed-off-by: Kiran Ostrolenk Reviewed-by: Weiwei L

[PULL 13/65] target/riscv: Refactor translation of vector-widening instruction

From: Dickon Hood Zvbb (implemented in later commit) has a widening instruction, which requires an extra check on the enabled extensions. Refactor GEN_OPIVX_WIDEN_TRANS() to take a check function to avoid reimplementing it. Signed-off-by: Dickon Hood Reviewed-by: Richard Henderson Reviewed-by

[PULL 53/65] target/riscv/cpu.c: add riscv_cpu_add_kvm_unavail_prop_array()

From: Daniel Henrique Barboza Use a helper in riscv_cpu_add_kvm_properties() to eliminate some of its code repetition. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Andrew Jones Reviewed-by: Alistair Francis Message-ID: <20230901194627.1214811-9-dbarb...@ventanamicro.com> Signed-off-by:

[PULL 40/65] linux-user/riscv: Add new extensions to hwprobe

From: Robbin Ehn This patch adds the new extensions in linux 6.5 to the hwprobe syscall. And fixes RVC check to OR with correct value. The previous variable contains 0 therefore it did work. Signed-off-by: Robbin Ehn Acked-by: Richard Henderson Acked-by: Alistair Francis Message-ID: Signed-

[PULL 05/65] target/riscv/cpu.c: add smepmp isa string

From: Daniel Henrique Barboza The cpu->cfg.epmp extension is still experimental, but it already has a 'smepmp' riscv,isa string. Add it. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Weiwei Li Reviewed-by: Alistair Francis Message-Id: <20230720132424.371132-3-dbarb...@ventanamicro.com>

[PULL 44/65] target/riscv: Align the AIA model to v1.0 ratified spec

From: Tommy Wu According to the new spec, when vsiselect has a reserved value, attempts from M-mode or HS-mode to access vsireg, or from VS-mode to access sireg, should preferably raise an illegal instruction exception. Signed-off-by: Tommy Wu Reviewed-by: Frank Chang Message-ID: <202308160616

[PULL 31/65] target/riscv: Create an KVM AIA irqchip

From: Yong-Xuan Wang We create a vAIA chip by using the KVM_DEV_TYPE_RISCV_AIA and then set up the chip with the KVM_DEV_RISCV_AIA_GRP_* APIs. We also extend KVM accelerator to specify the KVM AIA mode. The "riscv-aia" parameter is passed along with --accel in QEMU command-line. 1) "riscv-aia=emu

[PULL 54/65] target/riscv/cpu.c: limit cfg->vext_spec log message

From: Daniel Henrique Barboza Inside riscv_cpu_validate_v() we're always throwing a log message if the user didn't set a vector version via 'vext_spec'. We're going to include one case with the 'max' CPU where env->vext_ver will be set in the cpu_init(). But that alone will not stop the "vector

[PULL 20/65] crypto: Create sm4_subword

From: Max Chou Allows sharing of sm4_subword between different targets. Signed-off-by: Max Chou Reviewed-by: Frank Chang Reviewed-by: Richard Henderson Signed-off-by: Max Chou Message-ID: <20230711165917.2629866-14-max.c...@sifive.com> Signed-off-by: Alistair Francis --- include/crypto/sm4

[PULL 51/65] target/riscv/cpu.c: split vendor exts from riscv_cpu_extensions[]

From: Daniel Henrique Barboza Our goal is to make riscv_cpu_extensions[] hold only ratified, non-vendor extensions. Create a new riscv_cpu_vendor_exts[] array for them, changing riscv_cpu_add_user_properties() and riscv_cpu_add_kvm_properties() accordingly. Signed-off-by: Daniel Henrique Barboz

[PULL 32/65] target/riscv: update APLIC and IMSIC to support KVM AIA

From: Yong-Xuan Wang KVM AIA can't emulate APLIC only. When "aia=aplic" parameter is passed, APLIC devices is emulated by QEMU. For "aia=aplic-imsic", remove the mmio operations of APLIC when using KVM AIA and send wired interrupt signal via KVM_IRQ_LINE API. After KVM AIA enabled, MSI messages a

[PULL 09/65] target/riscv: Refactor vector-vector translation macro

From: Kiran Ostrolenk Refactor the non SEW-specific stuff out of `GEN_OPIVV_TRANS` into function `opivv_trans` (similar to `opivi_trans`). `opivv_trans` will be used in proceeding vector-crypto commits. Signed-off-by: Kiran Ostrolenk Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis

[PULL 38/65] hw/riscv/virt.c: fix non-KVM --enable-debug build

From: Daniel Henrique Barboza A build with --enable-debug and without KVM will fail as follows: /usr/bin/ld: libqemu-riscv64-softmmu.fa.p/hw_riscv_virt.c.o: in function `virt_machine_init': ./qemu/build/../hw/riscv/virt.c:1465: undefined reference to `kvm_riscv_aia_create' This happens becaus

[PULL 61/65] target/riscv/cpu.c: use cpu_cfg_ext_auto_update() during realize()

From: Daniel Henrique Barboza Let's change the other instances in realize() where we're enabling an extension based on a certain criteria (e.g. it's a dependency of another extension). We're leaving icsr and ifencei being enabled during RVG for later - we'll want to error out in that case. Every

[PULL 63/65] target/riscv: use isa_ext_update_enabled() in init_max_cpu_extensions()

From: Daniel Henrique Barboza Before adding support to detect if an extension was user set we need to handle how we're enabling extensions in riscv_init_max_cpu_extensions(). object_property_set_bool() calls the set() callback for the property, and we're going to use this callback to set the 'mul

[PULL 58/65] target/riscv/cpu.c: use offset in isa_ext_is_enabled/update_enabled

From: Daniel Henrique Barboza We'll have future usage for a function where, given an offset of the struct RISCVCPUConfig, the flag is updated to a certain val. Change all existing callers to use edata->ext_enable_offset instead of 'edata'. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Al

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