Re: [PATCH] hw/riscv: split RAM into low and high memory

Widening Cc to ARM/VFIO. On 4/8/23 11:15, Wu, Fei wrote: On 8/3/2023 11:07 PM, Andrew Jones wrote: On Mon, Jul 31, 2023 at 09:53:17AM +0800, Fei Wu wrote: riscv virt platform's memory started at 0x8000 and straddled the 4GiB boundary. Curiously enough, this choice of a memory layout will p

Re: [PATCH 1/2] tcg: Add gvec compare with immediate and scalar operand

Hi, Richard 在 2023/8/31 上午11:09, Richard Henderson 写道: Signed-off-by: Richard Henderson --- accel/tcg/tcg-runtime.h | 25 ++ include/tcg/tcg-op-gvec-common.h | 6 ++ accel/tcg/tcg-runtime-gvec.c | 26 ++ tcg/tcg-op-gvec.c| 150 +++

Re: [PATCH v3 12/32] target/ppc: Use generic helper to show CPU model names

On 9/7/23 02:35, Gavin Shan wrote: For target/ppc, the CPU type name can be: (1) The combination of the CPU model name and suffix; (2) the type name of the class whose PVR matches with the specified one; (3) alias of the CPU model, plus suffix; (4) MachineClass::default_cpu_type when the CPU mode

[PATCH v7 0/4] Virtio shared dma-buf

v1 link -> https://lists.gnu.org/archive/html/qemu-devel/2023-05/msg00598.html v2 link -> https://lists.gnu.org/archive/html/qemu-devel/2023-05/msg04530.html v3 link -> https://lists.gnu.org/archive/html/qemu-devel/2023-05/msg06126.html v4 link -> https://lists.gnu.org/archive/html/qemu-devel/2023-

[PATCH v7 1/4] uuid: add a hash function

Add hash function to uuid module using the djb2 hash algorithm. Add a couple simple unit tests for the hash function, checking collisions for similar UUIDs. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Albert Esteve --- include/qemu/uuid.h| 2 ++ tests/unit/test-uuid.c | 27

[PATCH v7 4/4] libvhost-user: handle shared_object msg

In the libvhost-user library we need to handle VHOST_USER_GET_SHARED_OBJECT requests, and add helper functions to allow sending messages to interact with the virtio shared objects hash table. Signed-off-by: Albert Esteve --- subprojects/libvhost-user/libvhost-user.c | 120 ++

[PATCH v7 2/4] virtio-dmabuf: introduce virtio-dmabuf

This API manages objects (in this iteration, dmabuf fds) that can be shared along different virtio devices, associated to a UUID. The API allows the different devices to add, remove and/or retrieve the objects by simply invoking the public functions that reside in the virtio-dmabuf file. For vhos

[PATCH v7 3/4] vhost-user: add shared_object msg

Add three new vhost-user protocol `VHOST_USER_BACKEND_SHARED_OBJECT_* messages`. These new messages are sent from vhost-user back-ends to interact with the virtio-dmabuf table in order to add or remove themselves as virtio exporters, or lookup for virtio dma-buf shared objects. The action taken in

[PATCH v5 07/57] target/loongarch: Use gen_helper_gvec_2_ptr for 2OP + env vector instructions

Signed-off-by: Song Gao --- target/loongarch/helper.h | 118 +++--- target/loongarch/vec_helper.c | 161 +++- target/loongarch/insn_trans/trans_vec.c.inc | 129 +--- 3 files changed, 219 insertions(+), 189 deletions(-) diff --gi

[PATCH v5 02/57] target/loongarch: Implement gvec_*_vl functions

Using gvec_*_vl functions hides oprsz. We can use gvec_v* for oprsz 16. and gvec_v* for oprsz 32. Signed-off-by: Song Gao --- target/loongarch/insn_trans/trans_vec.c.inc | 68 + 1 file changed, 44 insertions(+), 24 deletions(-) diff --git a/target/loongarch/insn_trans/trans_

[PATCH v5 08/57] target/loongarch: Use gen_helper_gvec_2 for 2OP vector instructions

Signed-off-by: Song Gao --- target/loongarch/helper.h | 58 - target/loongarch/vec_helper.c | 124 ++-- target/loongarch/insn_trans/trans_vec.c.inc | 16 ++- 3 files changed, 101 insertions(+), 97 deletions(-) diff --git a/target/loongarc

[PATCH v5 09/57] target/loongarch: Use gen_helper_gvec_2i for 2OP + imm vector instructions

Signed-off-by: Song Gao --- target/loongarch/helper.h | 146 +++ target/loongarch/vec_helper.c | 445 +--- target/loongarch/insn_trans/trans_vec.c.inc | 18 +- 3 files changed, 291 insertions(+), 318 deletions(-) diff --git a/target/loongarch/

[PATCH v5 06/57] target/loongarch: Use gen_helper_gvec_3 for 3OP vector instructions

Signed-off-by: Song Gao --- target/loongarch/helper.h | 214 +- target/loongarch/vec_helper.c | 444 +--- target/loongarch/insn_trans/trans_vec.c.inc | 19 +- 3 files changed, 326 insertions(+), 351 deletions(-) diff --git a/target/loongar

[PATCH v5 00/57] Add LoongArch LASX instructions

Hi, This series adds LoongArch LASX instructions. About test: We use RISU test the LoongArch LASX instructions. QEMU: https://github.com/loongson/qemu/tree/tcg-old-abi-support-lasx RISU: https://github.com/loongson/risu/tree/loongarch-suport-lasx Please review, Thanks. Changes for v5:

[PATCH v5 05/57] target/loongarch: Use gen_helper_gvec_3_ptr for 3OP + env vector instructions

Signed-off-by: Song Gao --- target/loongarch/helper.h | 48 +++ target/loongarch/vec_helper.c | 50 target/loongarch/insn_trans/trans_vec.c.inc | 66 + 3 files changed, 91 insertions(+), 73 deletions(-) diff --git a

[PATCH v5 03/57] target/loongarch: Use gen_helper_gvec_4_ptr for 4OP + env vector instructions

Signed-off-by: Song Gao --- target/loongarch/helper.h | 16 +- target/loongarch/vec_helper.c | 12 +++ target/loongarch/insn_trans/trans_vec.c.inc | 35 - 3 files changed, 41 insertions(+), 22 deletions(-) diff --git a/target/loonga

[PATCH v5 04/57] target/loongarch: Use gen_helper_gvec_4 for 4OP vector instructions

Signed-off-by: Song Gao --- target/loongarch/helper.h | 2 +- target/loongarch/vec_helper.c | 11 +-- target/loongarch/insn_trans/trans_vec.c.inc | 22 - 3 files changed, 19 insertions(+), 16 deletions(-) diff --git a/target/loongarch/

[PATCH v5 10/57] target/loongarch: Replace CHECK_SXE to check_vec(ctx, 16)

Intrudce a new function check_vec to replace CHECK_SXE Signed-off-by: Song Gao --- target/loongarch/insn_trans/trans_vec.c.inc | 248 +++- 1 file changed, 192 insertions(+), 56 deletions(-) diff --git a/target/loongarch/insn_trans/trans_vec.c.inc b/target/loongarch/insn_trans/t

[PATCH v5 01/57] target/loongarch: Renamed lsx*.c to vec* .c

Renamed lsx_helper.c to vec_helper.c and trans_lsx.c.inc to trans_vec.c.inc So LASX can used them. Signed-off-by: Song Gao --- target/loongarch/translate.c| 2 +- target/loongarch/{lsx_helper.c => vec_helper.c} | 2 +- .../loongarch/insn_trans/

Re: [PATCH v22 13/20] docs/s390x/cpu topology: document s390x cpu topology

On 01/09/2023 17.58, Nina Schoetterl-Glausch wrote: From: Pierre Morel Add some basic examples for the definition of cpu topology in s390x. Signed-off-by: Pierre Morel Co-developed-by: Nina Schoetterl-Glausch Signed-off-by: Nina Schoetterl-Glausch --- ... diff --git a/docs/devel/s390-cpu-

Re: [PULL 00/14] Block layer patches

Am 06.09.2023 um 17:13 hat Stefan Hajnoczi geschrieben: > test-bdrv-drain is failing. I think my coroutine wrapper patch might > be necessary: > https://gitlab.com/qemu-project/qemu/-/jobs/5029372308#L4907 > > I have dropped this patch series for the time being. Feel free to > remove my patches an

Re: [PATCH v7 2/4] virtio-dmabuf: introduce virtio-dmabuf

On 7/9/23 09:43, Albert Esteve wrote: This API manages objects (in this iteration, dmabuf fds) that can be shared along different virtio devices, associated to a UUID. The API allows the different devices to add, remove and/or retrieve the objects by simply invoking the public functions that res

Re: [PATCH v3 15/32] target/s390x: Use generic helper to show CPU model names

On 07.09.23 02:35, Gavin Shan wrote: For target/s390x, the CPU type name is always the combination of the CPU modle name and suffix. The CPU model names have been correctly shown in s390_print_cpu_model_list_entry() and create_cpu_model_list(). Use generic helper cpu_model_from_type() to show th

Re: [PATCH v5 00/57] Add LoongArch LASX instructions

Please ignore this series. I will resend. Thanks. Song Gao 在 2023/9/7 下午4:08, Song Gao 写道: Hi, This series adds LoongArch LASX instructions. About test: We use RISU test the LoongArch LASX instructions. QEMU: https://github.com/loongson/qemu/tree/tcg-old-abi-support-lasx RISU: http

Re: [PATCH v22 14/20] tests/avocado: s390x cpu topology core

On 01/09/2023 17.58, Nina Schoetterl-Glausch wrote: From: Pierre Morel Introduction of the s390x cpu topology core functions and basic tests. We test the correlation between the command line and the QMP results in query-cpus-fast for various CPU topology. Signed-off-by: Pierre Morel --- MA

Re: [PATCH v3 15/32] target/s390x: Use generic helper to show CPU model names

On 07/09/2023 02.35, Gavin Shan wrote: For target/s390x, the CPU type name is always the combination of the CPU modle name and suffix. The CPU model names have been correctly s/modle/model/ Thomas

[PATCH RESEND v5 11/57] target/loongarch: Add LASX data support

Signed-off-by: Song Gao Reviewed-by: Richard Henderson --- target/loongarch/cpu.h | 24 -- target/loongarch/internals.h| 22 target/loongarch/vec.h | 33 ++ linux-user/loongarch64/signal.c | 1 + target/l

[PATCH RESEND v5 02/57] target/loongarch: Implement gvec_*_vl functions

Using gvec_*_vl functions hides oprsz. We can use gvec_v* for oprsz 16. and gvec_v* for oprsz 32. Signed-off-by: Song Gao --- target/loongarch/insn_trans/trans_vec.c.inc | 68 + 1 file changed, 44 insertions(+), 24 deletions(-) diff --git a/target/loongarch/insn_trans/trans_

[PATCH RESEND v5 05/57] target/loongarch: Use gen_helper_gvec_3_ptr for 3OP + env vector instructions

Signed-off-by: Song Gao --- target/loongarch/helper.h | 48 +++ target/loongarch/vec_helper.c | 50 target/loongarch/insn_trans/trans_vec.c.inc | 66 + 3 files changed, 91 insertions(+), 73 deletions(-) diff --git a

[PATCH RESEND v5 19/57] target/loongarch: Implement xvhaddw/xvhsubw

This patch includes: - XVHADDW.{H.B/W.H/D.W/Q.D/HU.BU/WU.HU/DU.WU/QU.DU}; - XVHSUBW.{H.B/W.H/D.W/Q.D/HU.BU/WU.HU/DU.WU/QU.DU}. Signed-off-by: Song Gao --- target/loongarch/insns.decode | 18 +++ target/loongarch/disas.c| 17 +++ target/loongarch/

[PATCH RESEND v5 23/57] target/loongarch: Implement xvadda

This patch includes: - XVADDA.{B/H/W/D}. Signed-off-by: Song Gao Reviewed-by: Richard Henderson --- target/loongarch/insns.decode | 5 target/loongarch/disas.c| 5 target/loongarch/vec_helper.c | 30 +++-- target/loonga

[PATCH RESEND v5 35/57] target/loongarch: Implement xvsll xvsrl xvsra xvrotr

This patch includes: - XVSLL[I].{B/H/W/D}; - XVSRL[I].{B/H/W/D}; - XVSRA[I].{B/H/W/D}; - XVROTR[I].{B/H/W/D}. Signed-off-by: Song Gao Reviewed-by: Richard Henderson --- target/loongarch/insns.decode | 33 +++ target/loongarch/disas.c| 36 +++

[PATCH RESEND v5 46/57] target/loongarch: Implement LASX fpu arith instructions

This patch includes: - XVF{ADD/SUB/MUL/DIV}.{S/D}; - XVF{MADD/MSUB/NMADD/NMSUB}.{S/D}; - XVF{MAX/MIN}.{S/D}; - XVF{MAXA/MINA}.{S/D}; - XVFLOGB.{S/D}; - XVFCLASS.{S/D}; - XVF{SQRT/RECIP/RSQRT}.{S/D}. Signed-off-by: Song Gao Reviewed-by: Richard Henderson --- target/loongarch/insns.decode

[PATCH RESEND v5 52/57] target/loongarch: Implement xvreplve xvinsve0 xvpickve

This patch includes: - XVREPLVE.{B/H/W/D}; - XVREPL128VEI.{B/H/W/D}; - XVREPLVE0.{B/H/W/D/Q}; - XVINSVE0.{W/D}; - XVPICKVE.{W/D}; - XVBSLL.V, XVBSRL.V. Signed-off-by: Song Gao --- target/loongarch/helper.h | 5 + target/loongarch/insns.decode | 25 ++ target/lo

[PATCH RESEND v5 47/57] target/loongarch: Implement LASX fpu fcvt instructions

This patch includes: - XVFCVT{L/H}.{S.H/D.S}; - XVFCVT.{H.S/S.D}; - XVFRINT[{RNE/RZ/RP/RM}].{S/D}; - XVFTINT[{RNE/RZ/RP/RM}].{W.S/L.D}; - XVFTINT[RZ].{WU.S/LU.D}; - XVFTINT[{RNE/RZ/RP/RM}].W.D; - XVFTINT[{RNE/RZ/RP/RM}]{L/H}.L.S; - XVFFINT.{S.W/D.L}[U]; - X[CVFFINT.S.L, VFFINT{L/H}.D.W. Signed-off

[PATCH RESEND v5 28/57] target/loongarch: Implement xvsat

This patch includes: - XVSAT.{B/H/W/D}[U]. Signed-off-by: Song Gao Reviewed-by: Richard Henderson --- target/loongarch/insns.decode | 9 target/loongarch/disas.c| 9 target/loongarch/vec_helper.c | 48 +++-- target/loon

[PATCH RESEND v5 45/57] target/loongarch: Implement xvfrstp

This patch includes: - XVFRSTP[I].{B/H}. Signed-off-by: Song Gao Reviewed-by: Richard Henderson --- target/loongarch/insns.decode | 5 target/loongarch/disas.c| 5 target/loongarch/vec_helper.c | 32 + target/loonga

[PATCH RESEND v5 29/57] target/loongarch: Implement xvexth

This patch includes: - XVEXTH.{H.B/W.H/D.W/Q.D}; - XVEXTH.{HU.BU/WU.HU/DU.WU/QU.DU}. Signed-off-by: Song Gao Reviewed-by: Richard Henderson --- target/loongarch/insns.decode | 9 ++ target/loongarch/disas.c| 9 ++ target/loongarch/vec_helper.c

[PATCH RESEND v5 39/57] target/loongarch: Implement xvsrlrn xvsrarn

This patch includes: - XVSRLRN.{B.H/H.W/W.D}; - XVSRARN.{B.H/H.W/W.D}; - XVSRLRNI.{B.H/H.W/W.D/D.Q}; - XVSRARNI.{B.H/H.W/W.D/D.Q}. Signed-off-by: Song Gao Reviewed-by: Richard Henderson --- target/loongarch/insns.decode | 16 ++ target/loongarch/disas.c| 16 +

[PATCH RESEND v5 31/57] target/loongarch: Implement xvsigncov

This patch includes: - XVSIGNCOV.{B/H/W/D}. Signed-off-by: Song Gao Reviewed-by: Richard Henderson --- target/loongarch/insns.decode | 5 + target/loongarch/disas.c| 5 + target/loongarch/insn_trans/trans_vec.c.inc | 4 3 files changed, 14 insertio

[PATCH RESEND v5 53/57] target/loongarch: Implement xvpack xvpick xvilv{l/h}

This patch includes: - XVPACK{EV/OD}.{B/H/W/D}; - XVPICK{EV/OD}.{B/H/W/D}; - XVILV{L/H}.{B/H/W/D}. Signed-off-by: Song Gao Reviewed-by: Richard Henderson --- target/loongarch/insns.decode | 27 target/loongarch/disas.c| 27 target/loongarch/vec_help

[PATCH RESEND v5 30/57] target/loongarch: Implement vext2xv

This patch includes: - VEXT2XV.{H/W/D}.B, VEXT2XV.{HU/WU/DU}.BU; - VEXT2XV.{W/D}.B, VEXT2XV.{WU/DU}.HU; - VEXT2XV.D.W, VEXT2XV.DU.WU. Signed-off-by: Song Gao Reviewed-by: Richard Henderson --- target/loongarch/helper.h | 13 ++ target/loongarch/insns.decode

[PATCH RESEND v5 34/57] target/loongarch: Implement LASX logic instructions

This patch includes: - XV{AND/OR/XOR/NOR/ANDN/ORN}.V; - XV{AND/OR/XOR/NOR}I.B. Signed-off-by: Song Gao Reviewed-by: Richard Henderson --- target/loongarch/insns.decode | 12 +++ target/loongarch/disas.c| 12 +++ target/loongarch/vec_helper.c

[PATCH RESEND v5 40/57] target/loongarch: Implement xvssrln xvssran

This patch includes: - XVSSRLN.{B.H/H.W/W.D}; - XVSSRAN.{B.H/H.W/W.D}; - XVSSRLN.{BU.H/HU.W/WU.D}; - XVSSRAN.{BU.H/HU.W/WU.D}; - XVSSRLNI.{B.H/H.W/W.D/D.Q}; - XVSSRANI.{B.H/H.W/W.D/D.Q}; - XVSSRLNI.{BU.H/HU.W/WU.D/DU.Q}; - XVSSRANI.{BU.H/HU.W/WU.D/DU.Q}. Signed-off-by: Song Gao --- target/loonga

[PATCH RESEND v5 21/57] target/loongarch: Implement xavg/xvagr

This patch includes: - XVAVG.{B/H/W/D/}[U]; - XVAVGR.{B/H/W/D}[U]. Signed-off-by: Song Gao --- target/loongarch/insns.decode | 17 target/loongarch/disas.c| 17 target/loongarch/vec_helper.c | 22 +++---

[PATCH RESEND v5 24/57] target/loongarch: Implement xvmax/xvmin

This patch includes: - XVMAX[I].{B/H/W/D}[U]; - XVMIN[I].{B/H/W/D}[U]. Signed-off-by: Song Gao Reviewed-by: Richard Henderson --- target/loongarch/insns.decode | 36 + target/loongarch/disas.c| 34 +++ target/loongarch/vec_he

[PATCH RESEND v5 00/57] Add LoongArch LASX instructions

Hi, This series adds LoongArch LASX instructions. About test: We use RISU test the LoongArch LASX instructions. QEMU: https://github.com/loongson/qemu/tree/tcg-old-abi-support-lasx RISU: https://github.com/loongson/risu/tree/loongarch-suport-lasx Please review, Thanks. Changes for v5:

[PATCH RESEND v5 07/57] target/loongarch: Use gen_helper_gvec_2_ptr for 2OP + env vector instructions

Signed-off-by: Song Gao --- target/loongarch/helper.h | 118 +++--- target/loongarch/vec_helper.c | 161 +++- target/loongarch/insn_trans/trans_vec.c.inc | 129 +--- 3 files changed, 219 insertions(+), 189 deletions(-) diff --gi

[PATCH RESEND v5 16/57] target/loongarch: Implement xvaddi/xvsubi

This patch includes: - XVADDI.{B/H/W/D}U; - XVSUBI.{B/H/W/D}U. Signed-off-by: Song Gao Reviewed-by: Richard Henderson --- target/loongarch/insns.decode | 9 +++ target/loongarch/disas.c| 14 +++ target/loongarch/insn_trans/trans_vec.c.inc | 28

[PATCH RESEND v5 42/57] target/loongarch: Implement xvclo xvclz

This patch includes: - XVCLO.{B/H/W/D}; - XVCLZ.{B/H/W/D}. Signed-off-by: Song Gao Reviewed-by: Richard Henderson --- target/loongarch/insns.decode | 9 + target/loongarch/disas.c| 9 + target/loongarch/vec_helper.c | 3 ++- target

[PATCH RESEND v5 09/57] target/loongarch: Use gen_helper_gvec_2i for 2OP + imm vector instructions

Signed-off-by: Song Gao --- target/loongarch/helper.h | 146 +++ target/loongarch/vec_helper.c | 445 +--- target/loongarch/insn_trans/trans_vec.c.inc | 18 +- 3 files changed, 291 insertions(+), 318 deletions(-) diff --git a/target/loongarch/

[PATCH RESEND v5 33/57] target/loognarch: Implement xvldi

This patch includes: - XVLDI. Signed-off-by: Song Gao Reviewed-by: Richard Henderson --- target/loongarch/insns.decode | 2 ++ target/loongarch/disas.c| 7 +++ target/loongarch/insn_trans/trans_vec.c.inc | 13 ++--- 3 files changed, 15 insertions(

[PATCH RESEND v5 50/57] target/loongarch: Implement xvbitsel xvset

This patch includes: - XVBITSEL.V; - XVBITSELI.B; - XVSET{EQZ/NEZ}.V; - XVSETANYEQZ.{B/H/W/D}; - XVSETALLNEZ.{B/H/W/D}. Signed-off-by: Song Gao Reviewed-by: Richard Henderson --- target/loongarch/helper.h | 16 ++-- target/loongarch/insns.decode | 15 target

[PATCH RESEND v5 10/57] target/loongarch: Replace CHECK_SXE to check_vec(ctx, 16)

Intrudce a new function check_vec to replace CHECK_SXE Signed-off-by: Song Gao --- target/loongarch/insn_trans/trans_vec.c.inc | 248 +++- 1 file changed, 192 insertions(+), 56 deletions(-) diff --git a/target/loongarch/insn_trans/trans_vec.c.inc b/target/loongarch/insn_trans/t

[PATCH RESEND v5 38/57] target/loongarch: Implement xvsrln xvsran

This patch includes: - XVSRLN.{B.H/H.W/W.D}; - XVSRAN.{B.H/H.W/W.D}; - XVSRLNI.{B.H/H.W/W.D/D.Q}; - XVSRANI.{B.H/H.W/W.D/D.Q}. Signed-off-by: Song Gao Reviewed-by: Richard Henderson --- target/loongarch/insns.decode | 16 ++ target/loongarch/disas.c| 16 ++ t

[PATCH RESEND v5 57/57] target/loongarch: CPUCFG support LASX

Signed-off-by: Song Gao Reviewed-by: Richard Henderson --- target/loongarch/cpu.c | 1 + 1 file changed, 1 insertion(+) diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c index a1d3f680d8..fc7f70fbe5 100644 --- a/target/loongarch/cpu.c +++ b/target/loongarch/cpu.c @@ -393,6 +393,7 @@

[PATCH RESEND v5 32/57] target/loongarch: Implement xvmskltz/xvmskgez/xvmsknz

This patch includes: - XVMSKLTZ.{B/H/W/D}; - XVMSKGEZ.B; - XVMSKNZ.B. Signed-off-by: Song Gao Reviewed-by: Richard Henderson --- target/loongarch/insns.decode | 7 ++ target/loongarch/disas.c| 7 ++ target/loongarch/vec_helper.c | 78 +++

[PATCH RESEND v5 48/57] target/loongarch: Implement xvseq xvsle xvslt

This patch includes: - XVSEQ[I].{B/H/W/D}; - XVSLE[I].{B/H/W/D}[U]; - XVSLT[I].{B/H/W/D/}[U]. Signed-off-by: Song Gao Reviewed-by: Richard Henderson --- target/loongarch/insns.decode | 43 target/loongarch/disas.c| 43 target/loongarch/vec_helper.c

[PATCH RESEND v5 17/57] target/loongarch: Implement xvneg

This patch includes: - XVNEG.{B/H/W/D}. Signed-off-by: Song Gao Reviewed-by: Richard Henderson --- target/loongarch/insns.decode | 5 + target/loongarch/disas.c| 10 ++ target/loongarch/insn_trans/trans_vec.c.inc | 15 +++ 3 files chang

[PATCH RESEND v5 04/57] target/loongarch: Use gen_helper_gvec_4 for 4OP vector instructions

Signed-off-by: Song Gao --- target/loongarch/helper.h | 2 +- target/loongarch/vec_helper.c | 11 +-- target/loongarch/insn_trans/trans_vec.c.inc | 22 - 3 files changed, 19 insertions(+), 16 deletions(-) diff --git a/target/loongarch/

[PATCH RESEND v5 14/57] target/loongarch: Implement xvadd/xvsub

This patch includes: - XVADD.{B/H/W/D/Q}; - XVSUB.{B/H/W/D/Q}. Signed-off-by: Song Gao Reviewed-by: Richard Henderson --- target/loongarch/insns.decode | 14 +++ target/loongarch/disas.c| 23 + target/loongarch/translate.c| 4 + target/l

[PATCH RESEND v5 03/57] target/loongarch: Use gen_helper_gvec_4_ptr for 4OP + env vector instructions

Signed-off-by: Song Gao --- target/loongarch/helper.h | 16 +- target/loongarch/vec_helper.c | 12 +++ target/loongarch/insn_trans/trans_vec.c.inc | 35 - 3 files changed, 41 insertions(+), 22 deletions(-) diff --git a/target/loonga

[PATCH RESEND v5 55/57] target/loongarch: Implement xvld xvst

This patch includes: - XVLD[X], XVST[X]; - XVLDREPL.{B/H/W/D}; - XVSTELM.{B/H/W/D}. Signed-off-by: Song Gao --- target/loongarch/insns.decode | 18 +++ target/loongarch/disas.c| 24 target/loongarch/insn_trans/trans_vec.c.inc | 143 ++-- 3

[PATCH RESEND v5 01/57] target/loongarch: Renamed lsx*.c to vec* .c

Renamed lsx_helper.c to vec_helper.c and trans_lsx.c.inc to trans_vec.c.inc So LASX can used them. Signed-off-by: Song Gao --- target/loongarch/translate.c| 2 +- target/loongarch/{lsx_helper.c => vec_helper.c} | 2 +- .../loongarch/insn_trans/

[PATCH RESEND v5 56/57] target/loongarch: Move simply DO_XX marcos togther

Signed-off-by: Song Gao --- target/loongarch/vec.h| 42 ++ target/loongarch/vec_helper.c | 48 --- 2 files changed, 42 insertions(+), 48 deletions(-) diff --git a/target/loongarch/vec.h b/target/loongarch/vec.h index 2f23cae7d7.

[PATCH RESEND v5 44/57] target/loongarch: Implement xvbitclr xvbitset xvbitrev

This patch includes: - XVBITCLR[I].{B/H/W/D}; - XVBITSET[I].{B/H/W/D}; - XVBITREV[I].{B/H/W/D}. Signed-off-by: Song Gao Reviewed-by: Richard Henderson --- target/loongarch/insns.decode | 27 + target/loongarch/disas.c| 25 target/loonga

[PATCH RESEND v5 41/57] target/loongarch: Implement xvssrlrn xvssrarn

This patch includes: - XVSSRLRN.{B.H/H.W/W.D}; - XVSSRARN.{B.H/H.W/W.D}; - XVSSRLRN.{BU.H/HU.W/WU.D}; - XVSSRARN.{BU.H/HU.W/WU.D}; - XVSSRLRNI.{B.H/H.W/W.D/D.Q}; - XVSSRARNI.{B.H/H.W/W.D/D.Q}; - XVSSRLRNI.{BU.H/HU.W/WU.D/DU.Q}; - XVSSRARNI.{BU.H/HU.W/WU.D/DU.Q}. Signed-off-by: Song Gao --- targe

[PATCH RESEND v5 22/57] target/loongarch: Implement xvabsd

This patch includes: - XVABSD.{B/H/W/D}[U]. Signed-off-by: Song Gao Reviewed-by: Richard Henderson --- target/loongarch/insns.decode | 9 + target/loongarch/disas.c| 9 + target/loongarch/insn_trans/trans_vec.c.inc | 8 3 files changed,

[PATCH RESEND v5 37/57] target/loongarch: Implement xvsrlr xvsrar

This patch includes: - XVSRLR[I].{B/H/W/D}; - XVSRAR[I].{B/H/W/D}. Signed-off-by: Song Gao Reviewed-by: Richard Henderson --- target/loongarch/insns.decode | 17 + target/loongarch/disas.c| 18 ++ target/loongarch/vec_helper.c

[PATCH RESEND v5 54/57] target/loongarch: Implement xvshuf xvperm{i} xvshuf4i

This patch includes: - XVSHUF.{B/H/W/D}; - XVPERM.W; - XVSHUF4i.{B/H/W/D}; - XVPERMI.{W/D/Q}; - XVEXTRINS.{B/H/W/D}. Signed-off-by: Song Gao --- target/loongarch/helper.h | 3 + target/loongarch/insns.decode | 21 target/loongarch/disas.c

[PATCH RESEND v5 43/57] target/loongarch: Implement xvpcnt

This patch includes: - VPCNT.{B/H/W/D}. Signed-off-by: Song Gao Reviewed-by: Richard Henderson --- target/loongarch/insns.decode | 5 + target/loongarch/disas.c| 5 + target/loongarch/vec_helper.c | 3 ++- target/loongarch/insn_trans/trans

[PATCH RESEND v5 20/57] target/loongarch: Implement xvaddw/xvsubw

This patch includes: - XVADDW{EV/OD}.{H.B/W.H/D.W/Q.D}[U]; - XVSUBW{EV/OD}.{H.B/W.H/D.W/Q.D}[U]; - XVADDW{EV/OD}.{H.BU.B/W.HU.H/D.WU.W/Q.DU.D}. Signed-off-by: Song Gao --- target/loongarch/insns.decode | 45 target/loongarch/disas.c| 43 +++ targe

[PATCH RESEND v5 26/57] target/loongarch: Implement xvmadd/xvmsub/xvmaddw{ev/od}

This patch includes: - XVMADD.{B/H/W/D}; - XVMSUB.{B/H/W/D}; - XVMADDW{EV/OD}.{H.B/W.H/D.W/Q.D}[U]; - XVMADDW{EV/OD}.{H.BU.B/W.HU.H/D.WU.W/Q.DU.D}. Signed-off-by: Song Gao Reviewed-by: Richard Henderson --- target/loongarch/insns.decode | 34 ++ target/loongarch/disas.c

[PATCH RESEND v5 36/57] target/loongarch: Implement xvsllwil xvextl

This patch includes: - XVSLLWIL.{H.B/W.H/D.W}; - XVSLLWIL.{HU.BU/WU.HU/DU.WU}; - XVEXTL.Q.D, VEXTL.QU.DU. Signed-off-by: Song Gao Reviewed-by: Richard Henderson --- target/loongarch/insns.decode | 9 + target/loongarch/disas.c| 9 + target/loongarch/v

[PATCH RESEND v5 18/57] target/loongarch: Implement xvsadd/xvssub

This patch includes: - XVSADD.{B/H/W/D}[U]; - XVSSUB.{B/H/W/D}[U]. Signed-off-by: Song Gao Reviewed-by: Richard Henderson --- target/loongarch/insns.decode | 18 ++ target/loongarch/disas.c| 17 + target/loongarch/insn_trans/tran

[PATCH RESEND v5 15/57] target/loongarch: Implement xvreplgr2vr

This patch includes: - XVREPLGR2VR.{B/H/W/D}. Signed-off-by: Song Gao Reviewed-by: Richard Henderson --- target/loongarch/insns.decode | 5 target/loongarch/disas.c| 10 +++ target/loongarch/insn_trans/trans_vec.c.inc | 29 - 3 fil

[PATCH RESEND v5 49/57] target/loongarch: Implement xvfcmp

This patch includes: - XVFCMP.cond.{S/D}. Signed-off-by: Song Gao Reviewed-by: Richard Henderson --- target/loongarch/helper.h | 8 +- target/loongarch/insns.decode | 3 + target/loongarch/disas.c| 93 + target/loongarch/

[PATCH RESEND v5 13/57] target/loongarch: Add avail_LASX to check LASX instructions

Signed-off-by: Song Gao Reviewed-by: Richard Henderson --- target/loongarch/translate.h | 1 + 1 file changed, 1 insertion(+) diff --git a/target/loongarch/translate.h b/target/loongarch/translate.h index 89b49a859e..195f53573a 100644 --- a/target/loongarch/translate.h +++ b/target/loongarch/tr

[PATCH RESEND v5 25/57] target/loongarch: Implement xvmul/xvmuh/xvmulw{ev/od}

This patch includes: - XVMUL.{B/H/W/D}; - XVMUH.{B/H/W/D}[U]; - XVMULW{EV/OD}.{H.B/W.H/D.W/Q.D}[U]; - XVMULW{EV/OD}.{H.BU.B/W.HU.H/D.WU.W/Q.DU.D}. Signed-off-by: Song Gao Reviewed-by: Richard Henderson --- target/loongarch/insns.decode | 38 target/loongarch/disas.c

[PATCH RESEND v5 12/57] target/loongarch: check_vec support check LASX instructions

Reviewed-by: Richard Henderson Signed-off-by: Song Gao --- target/loongarch/cpu.h | 2 ++ target/loongarch/cpu.c | 2 ++ target/loongarch/insn_trans/trans_vec.c.inc | 6 ++ 3 files changed, 10 insertions(+) diff --git a/target/loongarch/cpu.h b/targ

[PATCH RESEND v5 27/57] target/loongarch; Implement xvdiv/xvmod

This patch includes: - XVDIV.{B/H/W/D}[U]; - XVMOD.{B/H/W/D}[U]. Signed-off-by: Song Gao Reviewed-by: Richard Henderson --- target/loongarch/insns.decode | 17 + target/loongarch/disas.c| 17 + target/loongarch/vec_helper.c

[PATCH RESEND v5 51/57] target/loongarch: Implement xvinsgr2vr xvpickve2gr

This patch includes: - XVINSGR2VR.{W/D}; - XVPICKVE2GR.{W/D}[U]. Signed-off-by: Song Gao --- target/loongarch/insns.decode | 7 +++ target/loongarch/disas.c| 17 target/loongarch/insn_trans/trans_vec.c.inc | 48 + 3 files changed, 7

[PATCH RESEND v5 06/57] target/loongarch: Use gen_helper_gvec_3 for 3OP vector instructions

Signed-off-by: Song Gao --- target/loongarch/helper.h | 214 +- target/loongarch/vec_helper.c | 444 +--- target/loongarch/insn_trans/trans_vec.c.inc | 19 +- 3 files changed, 326 insertions(+), 351 deletions(-) diff --git a/target/loongar

[PATCH RESEND v5 08/57] target/loongarch: Use gen_helper_gvec_2 for 2OP vector instructions

Signed-off-by: Song Gao --- target/loongarch/helper.h | 58 - target/loongarch/vec_helper.c | 124 ++-- target/loongarch/insn_trans/trans_vec.c.inc | 16 ++- 3 files changed, 101 insertions(+), 97 deletions(-) diff --git a/target/loongarc

[PATCH] disas/riscv: Fix the typo of inverted order of pmpaddr13 and pmpaddr14

Fix the inverted order of pmpaddr13 and pmpaddr14 in csr_name(). Signed-off-by: Alvin Chang --- disas/riscv.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/disas/riscv.c b/disas/riscv.c index 3873a69157..8e89e1d115 100644 --- a/disas/riscv.c +++ b/disas/riscv.c @@ -2116

[PATCH v2] docs/devel: Add cross-compiling doc

Add instructions for how to cross-compile QEMU for RISC-V. The file is named generically because there's no reason not to collect other architectures steps into the same file, especially because several subsections like those for cross-compiling QEMU dependencies using meson and a cross-file could

Re: [PATCH] docs/devel: Add cross-compiling doc

On Thu, Sep 07, 2023 at 01:13:33PM +1000, Alistair Francis wrote: > On Wed, Jul 26, 2023 at 10:08 PM Andrew Jones wrote: > > > > Add instructions for how to cross-compile QEMU for RISC-V. The > > file is named generically because there's no reason not to collect > > other architectures steps into

Re: [PATCH v3 01/32] cpu: Add helper cpu_model_from_type()

On 7/9/23 02:35, Gavin Shan wrote: Add helper cpu_model_from_type() to extract the CPU model name from the CPU type name in two circumstances: (1) The CPU type name is the combination of the CPU model name and suffix. (2) The CPU type name is same to the CPU model name. The helper will be used i

Re: [PATCH v3 0/6] vfio/migration: Block VFIO migration with postcopy and background snapshot

On 9/6/23 17:08, Avihai Horon wrote: Hello, Recently added VFIO migration is not compatible with some of the pre-existing migration features. This was overlooked and today these combinations are not blocked by QEMU. This series fixes it. Postcopy migration: VFIO migration is not compatible with

Re: [PATCH v3 24/32] machine: Constify MachineClass::valid_cpu_types[i]

On 7/9/23 02:35, Gavin Shan wrote: Constify MachineClass::valid_cpu_types[i], as suggested by Richard Henderson. Suggested-by: Richard Henderson Signed-off-by: Gavin Shan --- hw/m68k/q800.c | 2 +- include/hw/boards.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) Reviewed

Re: [PATCH v3 28/32] hw/arm/virt: Check CPU type in machine_run_board_init()

On 7/9/23 02:35, Gavin Shan wrote: Set mc->valid_cpu_types so that the user specified CPU type can be validated in machine_run_board_init(). We needn't to do the check by ourselves. Signed-off-by: Gavin Shan --- hw/arm/virt.c | 21 +++-- 1 file changed, 3 insertions(+), 18 de

Re: [PATCH v22 15/20] tests/avocado: s390x cpu topology polarization

On 01/09/2023 17.58, Nina Schoetterl-Glausch wrote: From: Pierre Morel Polarization is changed on a request from the guest. Let's verify the polarization is accordingly set by QEMU. Signed-off-by: Pierre Morel Co-developed-by: Nina Schoetterl-Glausch Signed-off-by: Nina Schoetterl-Glausch -

Re: [PATCH v3 27/32] machine: Print CPU model name instead of CPU type name

On 7/9/23 02:35, Gavin Shan wrote: The names of supported CPU models instead of CPU types should be printed when the user specified CPU type isn't supported, to be consistent with the output from '-cpu ?'. Correct the error messages to print CPU model names instead of CPU type names. Signed-off

Re: [PATCH v22 16/20] tests/avocado: s390x cpu topology entitlement tests

On 01/09/2023 17.58, Nina Schoetterl-Glausch wrote: From: Pierre Morel Test changes in the entitlement from both a guest and a host point of view, depending on the polarization. Signed-off-by: Pierre Morel Co-developed-by: Nina Schoetterl-Glausch Signed-off-by: Nina Schoetterl-Glausch ---

Re: [PATCH v3 30/32] hw/arm/sbsa-ref: Check CPU type in machine_run_board_init()

On 7/9/23 02:35, Gavin Shan wrote: Set mc->valid_cpu_types so that the user specified CPU type can be validated in machine_run_board_init(). We needn't to do it by ourselves. Signed-off-by: Gavin Shan --- hw/arm/sbsa-ref.c | 21 +++-- 1 file changed, 3 insertions(+), 18 delet

Re: [PATCH v3 0/6] vfio/migration: Block VFIO migration with postcopy and background snapshot

[ ... ] Applied to vfio-next. On that topic I am preparing a PR. Juan, Peter, Leonardo, is it ok for you if these migration changes go through the VFIO tree ? Thanks, C.

Re: [PATCH v3 32/32] hw/riscv/shakti_c: Check CPU type in machine_run_board_init()

On 7/9/23 02:35, Gavin Shan wrote: Set mc->valid_cpu_types so that the user specified CPU type can be validated in machine_run_board_init(). We needn't to do it by ourselves. Signed-off-by: Gavin Shan --- hw/riscv/shakti_c.c | 11 +-- 1 file changed, 5 insertions(+), 6 deletions(-)

Re: [PATCH] hw/riscv: split RAM into low and high memory

Hi, On 9/7/23 09:16, Philippe Mathieu-Daudé wrote: > Widening Cc to ARM/VFIO. > > On 4/8/23 11:15, Wu, Fei wrote: >> On 8/3/2023 11:07 PM, Andrew Jones wrote: >>> On Mon, Jul 31, 2023 at 09:53:17AM +0800, Fei Wu wrote: riscv virt platform's memory started at 0x8000 and straddled the

Re: [PATCH] docs/devel: Add cross-compiling doc

Andrew Jones writes: > Add instructions for how to cross-compile QEMU for RISC-V. The > file is named generically because there's no reason not to collect > other architectures steps into the same file, especially because > several subsections like those for cross-compiling QEMU dependencies >

Re: [PATCH v5 20/20] linux-user/s390x: Add vdso

Richard Henderson writes: > On 9/4/23 08:00, Alex Bennée wrote: >> Due to the b4 dropping the vdso.so in the patch this fails: >>Program build-vdso.sh found: YES >> (/home/alex/lsrc/qemu.git/linux-user/build-vdso.sh) >>../../linux-user/s390x/meson.build:24:0: ERROR: File vdso.so does no

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