On 8/30/23 15:40, Laszlo Ersek wrote:
> Cc: "Michael S. Tsirkin" (supporter:vhost)
> Cc: Eugenio Perez Martin
> Cc: German Maglione
> Cc: Liu Jiang
> Cc: Sergio Lopez Pascual
> Cc: Stefano Garzarella
> Signed-off-by: Laszlo Ersek
> Reviewed-by: Stefano Garzarella
> ---
>
> Notes:
> v2:
On 8/30/23 15:40, Laszlo Ersek wrote:
> In the vhost_user_set_vring_addr() function, we calculate
> "reply_supported" unconditionally, even though we'll only need it if
> "wait_for_reply" is also true.
>
> Restrict the scope of "reply_supported" to the minimum.
>
> This is purely refactoring -- n
在 2023/8/31 上午2:12, Richard Henderson 写道:
On 8/30/23 01:48, Song Gao wrote:
--- a/target/loongarch/vec.h
+++ b/target/loongarch/vec.h
@@ -47,4 +47,7 @@
#define Q(x) Q[x]
#endif /* HOST_BIG_ENDIAN */
+#define DO_ADD(a, b) (a + b)
+#define DO_SUB(a, b) (a - b)
+
Why are these moved?
I w
在 2023/8/31 上午12:09, Richard Henderson 写道:
On 8/30/23 01:48, Song Gao wrote:
This patch includes:
- XVREPLGR2VR.{B/H/W/D}.
Signed-off-by: Song Gao
Reviewed-by: Richard Henderson
---
target/loongarch/insns.decode | 5 +
target/loongarch/disas.c | 10 +
在 2023/8/31 上午2:06, Richard Henderson 写道:
On 8/30/23 01:48, Song Gao wrote:
Use gen_helper_gvec_* series function.
and rename lsx_helper.c to vec_helper.c.
Signed-off-by: Song Gao
---
target/loongarch/helper.h | 642
.../loongarch/{lsx_helper.c => vec_helper.c}
On 8/30/23 15:40, Laszlo Ersek wrote:
> In order to avoid a forward-declaration for "vhost_user_write_sync" in a
> subsequent patch, hoist "vhost_user_write_sync" ->
> "vhost_user_get_features" -> "vhost_user_get_u64" just above
> "vhost_set_vring".
>
> This is purely code movement -- no observabl
Hi,
Yocto Project's CI is noticing a lot of issues with qemu-system-ppc
emulation on loaded systems after we switch glibc to 2.38.
This is manifesting as hangs in the emulated system and for example,
systemd units then timeout and restart. If we have long running
commands running over ssh (e.g. c
Thanks a lot.
On Thu, Aug 31, 2023 at 2:11 PM Philippe Mathieu-Daudé
wrote:
> Hi,
>
> On 31/8/23 05:15, Liu Jaloo wrote:
> > Where actually defined the "PC_MACHINE_CLASS", I can't find it in source
> > code, please help to point out the file.
>
> It is defined in include/hw/i386/pc.h:
>
> OBJECT
On 29/08/2023 16:32, Cédric Le Goater wrote:
to log an error in case of bad configuration of the XIVE tables by the FW.
Signed-off-by: Cédric Le Goater
---
hw/intc/pnv_xive.c | 27 +++
hw/intc/pnv_xive2.c | 27 +++
2 files changed, 46 inse
On 29/08/2023 16:32, Cédric Le Goater wrote:
It will help us model the END triggers on the PowerNV machine, which
can be rerouted to another interrupt controller.
Signed-off-by: Cédric Le Goater
---
diff --git a/hw/intc/xive.c b/hw/intc/xive.c
index 56670b2cac6e..df3ee0496fe7 100644
---
On 8/31/23 09:44, Frederic Barrat wrote:
On 29/08/2023 16:32, Cédric Le Goater wrote:
to log an error in case of bad configuration of the XIVE tables by the FW.
Signed-off-by: Cédric Le Goater
---
hw/intc/pnv_xive.c | 27 +++
hw/intc/pnv_xive2.c | 27 +
On 29/08/2023 16:32, Cédric Le Goater wrote:
The notify page of the interrupt controller can either be used to
receive trigger events from the HW controllers (PHB, PSI) or to
reroute interrupts between Interrupt Controllers. In which case, the
VSD table is used to determine the address of the
On 29/08/2023 16:32, Cédric Le Goater wrote:
The XIVE interrupt contoller maintains various fields on interrupt
targets in a structure called NVT. Each unit has a NVT cache, backed
by RAM.
When the NVT structure is not local (in RAM) to the chip, the XIVE
interrupt controller forwards the mem
Richard Henderson writes:
> On 8/30/23 07:52, Helge Deller wrote:
>> On 8/30/23 00:02, Richard Henderson wrote:
>>> Changes for v5:
>>> * Integrated cross-compile, via new build-vdso.sh and meson rules.
>>> However, keep the binaries in the tree for hosts which do not
>>> have all
On 31/8/23 08:45, Michael S. Tsirkin wrote:
On Thu, Aug 31, 2023 at 08:22:34AM +0200, Philippe Mathieu-Daudé wrote:
Hi Michael,
On 30/8/23 23:48, Michael S. Tsirkin wrote:
current code sets PCI_SEC_LATENCY_TIMER to WO, but for
pcie to pcie bridges it must be RO 0 according to
pci express spec
On 30/8/23 18:14, Alexander Graf wrote:
Recent versions of macOS use clang instead of gcc. The OS_OBJECT_USE_OBJC
define is only necessary when building with gcc. Let's not define it when
building with clang.
With this patch, I can successfully include GCD headers in QEMU when
building with clan
On 30/8/23 18:14, Alexander Graf wrote:
MacOS unconditionally disables interrupts of the physical timer on boot
and then continues to use the virtual one. We don't really want to support
a full physical timer emulation, so let's just ignore those writes.
Signed-off-by: Alexander Graf
---
v1 -
On 29/8/23 10:29, Paolo Bonzini wrote:
Signed-off-by: Paolo Bonzini
---
configure | 11 +--
meson.build | 3 ++-
meson_options.txt | 2 ++
scripts/meson-buildoptions.sh | 3 +++
4 files changed, 8 insertions(+), 11 deletions(-)
On Tue, Aug 29, 2023 at 12:34 PM Daniel P. Berrangé wrote:
> I think I agree wrt to CPUs, but in the case of OS I think
> it is fairly accurate as-is.
Ok, I wanted to leave out the "*intends* to remove support" part,
which is too strong; but I agree that keeping some kind of "support
may go away
HAX is deprecated since commits 73741fda6c ("MAINTAINERS: Abort
HAXM maintenance") and 90c167a1da ("docs/about/deprecated: Mark
HAXM in QEMU as deprecated"), released in v8.0.0.
Per the latest HAXM release (v7.8 [*]), the latest QEMU supported
is v7.2:
Note: Up to this release, HAXM supports QE
kind ping?
On 25/8/23 10:02, Philippe Mathieu-Daudé wrote:
Ping?
On 19/7/23 16:17, Philippe Mathieu-Daudé wrote:
Do not silently ignore the user request of using MSIX.
Remove the TODO. Coverity reported this as CID 1508725.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/usb/hcd-xhci-pci.c |
Cc'ing Markus and Marc-André
On 31/8/23 10:22, Philippe Mathieu-Daudé wrote:
kind ping?
On 25/8/23 10:02, Philippe Mathieu-Daudé wrote:
Ping?
On 19/7/23 16:17, Philippe Mathieu-Daudé wrote:
Do not silently ignore the user request of using MSIX.
Remove the TODO. Coverity reported this as CID
On Tue, Aug 29, 2023 at 7:14 PM Daniel P. Berrangé wrote:
>
> On Tue, Aug 29, 2023 at 10:29:25AM +0200, Paolo Bonzini wrote:
> > The argument of --host-cc is not obeyed when cross compiling. To avoid
> > this issue, place it in a configuration file and pass it to meson
> > with --native-file.
> >
Cc'ing qemu-block@ (I suppose this will go via a block tree)
On 24/8/23 18:47, Peter Maydell wrote:
From: Philippe Mathieu-Daudé
Use autofree heap allocation instead of variable-length array on the
stack.
The codebase has very few VLAs, and if we can get rid of them all we
can make the compil
Hi John,
On 7/8/23 19:37, John Snow wrote:
Apologies again for the delay. I tested it lightly and it seems fine to
me (and in general I trust your commits as they've got meticulous
references to the spec, so it'll be easy to fix if something goes wrong)
It's my fault we'll miss this release
On 8/31/23 09:50, Frederic Barrat wrote:
On 29/08/2023 16:32, Cédric Le Goater wrote:
It will help us model the END triggers on the PowerNV machine, which
can be rerouted to another interrupt controller.
Signed-off-by: Cédric Le Goater
---
diff --git a/hw/intc/xive.c b/hw/intc/xive.c
in
On 31/08/2023 10.20, Philippe Mathieu-Daudé wrote:
HAX is deprecated since commits 73741fda6c ("MAINTAINERS: Abort
HAXM maintenance") and 90c167a1da ("docs/about/deprecated: Mark
HAXM in QEMU as deprecated"), released in v8.0.0.
Per the latest HAXM release (v7.8 [*]), the latest QEMU supported
i
On Wed, Aug 30, 2023 at 10:35:02AM -0300, Daniel Henrique Barboza wrote:
> A build with --enable-debug and without KVM will fail as follows:
>
> /usr/bin/ld: libqemu-riscv64-softmmu.fa.p/hw_riscv_virt.c.o: in function
> `virt_machine_init':
> ./qemu/build/../hw/riscv/virt.c:1465: undefined refere
On Wed, Aug 30, 2023 at 10:35:03AM -0300, Daniel Henrique Barboza wrote:
> Commit 6df0b37e2ab breaks a --enable-debug build in a non-KVM
> environment with the following error:
>
> /usr/bin/ld: libqemu-riscv64-softmmu.fa.p/hw_intc_riscv_aplic.c.o: in
> function `riscv_kvm_aplic_request':
> ./qemu
On Thu, Aug 31, 2023 at 10:20:26AM +0200, Paolo Bonzini wrote:
> On Tue, Aug 29, 2023 at 12:34 PM Daniel P. Berrangé
> wrote:
> > I think I agree wrt to CPUs, but in the case of OS I think
> > it is fairly accurate as-is.
>
> Ok, I wanted to leave out the "*intends* to remove support" part,
> wh
On 2023/08/31 17:12, Philippe Mathieu-Daudé wrote:
On 30/8/23 18:14, Alexander Graf wrote:
Recent versions of macOS use clang instead of gcc. The OS_OBJECT_USE_OBJC
define is only necessary when building with gcc. Let's not define it when
building with clang.
With this patch, I can successfully
On 31.08.23 10:53, Akihiko Odaki wrote:
On 2023/08/31 17:12, Philippe Mathieu-Daudé wrote:
On 30/8/23 18:14, Alexander Graf wrote:
Recent versions of macOS use clang instead of gcc. The
OS_OBJECT_USE_OBJC
define is only necessary when building with gcc. Let's not define it
when
building wi
On 8/31/23 09:57, Frederic Barrat wrote:
On 29/08/2023 16:32, Cédric Le Goater wrote:
The XIVE interrupt contoller maintains various fields on interrupt
targets in a structure called NVT. Each unit has a NVT cache, backed
by RAM.
When the NVT structure is not local (in RAM) to the chip, the X
On Thu, 31 Aug 2023 at 01:57, Stefano Stabellini wrote:
> As Xen is gaining R52 and R82 support, it would be great to be able to
> use QEMU for development and testing there as well, but I don't think
> QEMU can emulate EL2 properly for the Cortex-R architecture. We would
> need EL2 support in the
On Wed, 30 Aug 2023 17:34:12 +1000
Gavin Shan wrote:
> Hi Igor,
>
> On 8/29/23 19:03, Igor Mammedov wrote:
> > On Tue, 29 Aug 2023 16:28:45 +1000
> > Gavin Shan wrote:
> >> On 8/29/23 00:46, Igor Mammedov wrote:
> >>> On Mon, 31 Jul 2023 15:07:30 +1000
> >>> Gavin Shan wrote:
> On 7
On 8/31/23 05:42, Andrew Jones wrote:
On Wed, Aug 30, 2023 at 10:35:02AM -0300, Daniel Henrique Barboza wrote:
A build with --enable-debug and without KVM will fail as follows:
/usr/bin/ld: libqemu-riscv64-softmmu.fa.p/hw_riscv_virt.c.o: in function
`virt_machine_init':
./qemu/build/../hw/r
From: Gerd Hoffmann
Use VIRTIO_GPU_SHM_ID_HOST_VISIBLE as id for virtio-gpu.
Signed-off-by: Antonio Caggiano
Tested-by: Alyssa Ross
Tested-by: Akihiko Odaki
Acked-by: Michael S. Tsirkin
Reviewed-by: Akihiko Odaki
Signed-off-by: Huang Rui
---
This patch is already under review as part of t
From: Antonio Caggiano
The feature can be enabled when a backend wants it.
Signed-off-by: Antonio Caggiano
Signed-off-by: Gurchetan Singh
Tested-by: Alyssa Ross
Tested-by: Akihiko Odaki
Reviewed-by: Marc-André Lureau
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Akihiko Odaki
Signed-of
Configure context init feature flag for virglrenderer.
Originally-by: Antonio Caggiano
Signed-off-by: Huang Rui
---
New patch, result of splitting
[RFC QEMU PATCH 04/18] virtio-gpu: CONTEXT_INIT feature
meson.build | 4
1 file changed, 4 insertions(+)
diff --git a/meson.build b/meson.bu
Patch "virtio-gpu: CONTEXT_INIT feature" has added the context_init
feature flags.
We would like to enable the feature with virglrenderer, so add to create
virgl renderer context with flags using context_id when valid.
Originally-by: Antonio Caggiano
Signed-off-by: Huang Rui
---
New patch, resu
Hi all,
Antonio Caggiano made the venus with QEMU on KVM platform last
September[1]. This series are inherited from his original work to support
the features of context init, hostmem, resource uuid, and blob resources
for venus.
At March of this year, we sent out the V1 version[2] for the review.
From: Xenia Ragiadakou
When the memory region has a different life-cycle from that of her parent,
could be automatically released, once has been unparent and once all of her
references have gone away, via the object's free callback.
However, currently, references to the memory region are held by
From: Antonio Caggiano
Support BLOB resources creation, mapping and unmapping by calling the
new stable virglrenderer 0.10 interface. Only enabled when available and
via the blob config. E.g. -device virtio-vga-gl,blob=true
Signed-off-by: Antonio Caggiano
Signed-off-by: Dmitry Osipenko
Signed-
From: Antonio Caggiano
This adds preparatory functions needed to:
- decode blob cmds
- tracking iovecs
Signed-off-by: Antonio Caggiano
Signed-off-by: Dmitry Osipenko
Signed-off-by: Gurchetan Singh
Tested-by: Alyssa Ross
Tested-by: Emmanouil Pitsidianakis
Tested-by: Akihiko Odaki
Venus in virglrenderer has required render server support.
Signed-off-by: Huang Rui
---
New patch
hw/display/virtio-gpu-virgl.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/display/virtio-gpu-virgl.c b/hw/display/virtio-gpu-virgl.c
index c5a62665bd..1ae3e458e2 100644
From: Antonio Caggiano
Enable resource UUID feature and implement command resource assign UUID.
This is done by introducing a hash table to map resource IDs to their
UUIDs.
Signed-off-by: Antonio Caggiano
Signed-off-by: Huang Rui
---
v1->v2:
- Separate declarations from code.
hw/display/
From: "Dr. David Alan Gilbert"
Define a new capability type 'VIRTIO_PCI_CAP_SHARED_MEMORY_CFG' to allow
defining shared memory regions with sizes and offsets of 2^32 and more.
Multiple instances of the capability are allowed and distinguished
by a device-specific 'id'.
Signed-off-by: Dr. David A
From: Antonio Caggiano
Request Venus when initializing VirGL.
Signed-off-by: Antonio Caggiano
Signed-off-by: Huang Rui
---
v1->v2:
- Rebase to latest version
hw/display/virtio-gpu-virgl.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/hw/display/virtio-gpu-virgl.c b/hw/display/vi
From: Dmitry Osipenko
The udmabuf usage is mandatory when virgl is disabled and blobs feature
enabled in the Qemu machine configuration. If virgl and blobs are enabled,
then udmabuf requirement is optional. Since udmabuf isn't widely supported
by a popular Linux distros today, let's relax the udm
From: Antonio Caggiano
Add support for the Venus capset, which enables Vulkan support through
the Venus Vulkan driver for virtio-gpu.
Signed-off-by: Antonio Caggiano
Signed-off-by: Huang Rui
---
hw/display/virtio-gpu-virgl.c | 21 +
include/standard-headers/l
On 31/8/23 11:32, Huang Rui wrote:
Configure context init feature flag for virglrenderer.
Originally-by: Antonio Caggiano
Signed-off-by: Huang Rui
---
New patch, result of splitting
[RFC QEMU PATCH 04/18] virtio-gpu: CONTEXT_INIT feature
meson.build | 4
1 file changed, 4 insertions(
On 31/8/23 11:32, Huang Rui wrote:
Patch "virtio-gpu: CONTEXT_INIT feature" has added the context_init
feature flags.
We would like to enable the feature with virglrenderer, so add to create
virgl renderer context with flags using context_id when valid.
Originally-by: Antonio Caggiano
Signed-of
Peter Maydell writes:
> On Thu, 31 Aug 2023 at 01:57, Stefano Stabellini
> wrote:
>> As Xen is gaining R52 and R82 support, it would be great to be able to
>> use QEMU for development and testing there as well, but I don't think
>> QEMU can emulate EL2 properly for the Cortex-R architecture.
On Thu, 31 Aug 2023 at 10:53, Alex Bennée wrote:
>
>
> Peter Maydell writes:
>
> > On Thu, 31 Aug 2023 at 01:57, Stefano Stabellini
> > wrote:
> >> As Xen is gaining R52 and R82 support, it would be great to be able to
> >> use QEMU for development and testing there as well, but I don't think
>
W dniu 30.08.2023 o 23:48, Michael S. Tsirkin pisze:
current code sets PCI_SEC_LATENCY_TIMER to WO, but for
pcie to pcie bridges it must be RO 0 according to
pci express spec which says:
This register does not apply to PCI Express. It must be read-only
and hardwired to 00h. For PCI Expr
On 2023/08/31 18:32, Huang Rui wrote:
From: Xenia Ragiadakou
When the memory region has a different life-cycle from that of her parent,
could be automatically released, once has been unparent and once all of her
references have gone away, via the object's free callback.
However, currently, ref
On Fri, Aug 25, 2023 at 10:08:34AM -0300, Daniel Henrique Barboza wrote:
> target/riscv/cpu.c needs to handle all possible accelerators (TCG and
> KVM at this moment) during both init() and realize() time. This forces
> us to resort to a lot of "if tcg" and "if kvm" throughout the code,
> which isn
On Fri, Aug 25, 2023 at 10:08:35AM -0300, Daniel Henrique Barboza wrote:
> riscv_cpu_realize_tcg() was added to allow TCG cpus to have a different
> realize() path during the common riscv_cpu_realize(), making it a good
> choice to start moving TCG exclusive code to tcg-cpu.c.
>
> Rename it to tcg
On 2023/08/31 18:32, Huang Rui wrote:
From: Antonio Caggiano
Support BLOB resources creation, mapping and unmapping by calling the
new stable virglrenderer 0.10 interface. Only enabled when available and
via the blob config. E.g. -device virtio-vga-gl,blob=true
Signed-off-by: Antonio Caggiano
On Fri, Aug 25, 2023 at 10:08:36AM -0300, Daniel Henrique Barboza wrote:
> This function is the core of the RISC-V validations for TCG CPUs, and it
> has a lot going on.
>
> Functions in cpu.c were made public to allow them to be used by the KVM
> accelerator class later on. 'cpu_cfg_ext_get_min_v
On 2023/08/31 18:32, Huang Rui wrote:
From: Antonio Caggiano
Enable resource UUID feature and implement command resource assign UUID.
This is done by introducing a hash table to map resource IDs to their
UUIDs.
The hash table does not seem to be stored during migration.
Signed-off-by: Anto
Hi Peter/Alex,
Appreciate your help. :)
On 31/08/2023 11:03, Peter Maydell wrote:
CAUTION: This message has originated from an External Source. Please use proper
judgment and caution when opening attachments, clicking links, or responding to
this email.
On Thu, 31 Aug 2023 at 10:53, Alex Be
On Fri, Aug 25, 2023 at 10:08:37AM -0300, Daniel Henrique Barboza wrote:
> Move the remaining of riscv_tcg_ops now that we have a working realize()
> implementation.
>
> Signed-off-by: Daniel Henrique Barboza
> ---
> target/riscv/cpu.c | 58 -
> target
Hi Huang,
Thank you for pushing this forward!
On 31/08/2023 11:32, Huang Rui wrote:
From: Antonio Caggiano
Request Venus when initializing VirGL.
Signed-off-by: Antonio Caggiano
Signed-off-by: Huang Rui
---
v1->v2:
- Rebase to latest version
hw/display/virtio-gpu-virgl.c | 2 ++
On 2023/08/31 18:32, Huang Rui wrote:
From: Antonio Caggiano
Add support for the Venus capset, which enables Vulkan support through
the Venus Vulkan driver for virtio-gpu.
Signed-off-by: Antonio Caggiano
Signed-off-by: Huang Rui
---
hw/display/virtio-gpu-virgl.c | 21
From: Richard Henderson
When the cpu support MTE, but the system does not, reduce cpu
support to user instructions at EL0 instead of completely
disabling MTE. If we encounter a cpu implementation which does
something else, we can revisit this setting.
Signed-off-by: Richard Henderson
Reviewed-
From: Richard Henderson
Support all of the easy GM block sizes.
Use direct memory operations, since the pointers are aligned.
While BS=2 (16 bytes, 1 tag) is a legal setting, that requires
an atomic store of one nibble. This is not difficult, but there
is also no point in supporting it until re
From: Richard Henderson
Access to many of the special registers is enabled or disabled
by ACTLR_EL[23], which we implement as constant 0, which means
that all writes outside EL3 should trap.
Signed-off-by: Richard Henderson
Reviewed-by: Peter Maydell
Message-id: 20230811214031.171020-7-richard
From: Richard Henderson
There is only one additional EL1 register modeled, which
also needs to use access_actlr_w.
Signed-off-by: Richard Henderson
Reviewed-by: Peter Maydell
Message-id: 20230811214031.171020-8-richard.hender...@linaro.org
Signed-off-by: Peter Maydell
---
target/arm/tcg/cpu6
The IoTKit, SSE200 and SSE300 all default to 8 MPU regions. The
MPS2/MPS3 FPGA images don't override these except in the case of
AN547, which uses 16 MPU regions.
Define properties on the ARMSSE object for the MPU regions (using the
same names as the documented RTL configuration settings, and
fol
In the aspeed_rtc device we store a difference between two time_t
values in an 'int'. This is not really correct when time_t could
be 64 bits. Enlarge the field to 'int64_t'.
This is a migration compatibility break for the aspeed boards.
While we are changing the vmstate, remove the accidental
dup
From: Richard Henderson
Previously we hard-coded the blocksize with GMID_EL1_BS.
But the value we choose for -cpu max does not match the
value that cortex-a710 uses.
Mirror the way we handle dcz_blocksize.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
Message-id: 20230811214031.
From: Jean-Christophe Dubois
* Add Addr and size definition for all i.MX7 devices in i.MX7 header file.
* Use those newly defined named constants whenever possible.
* Standardize the way we init a familly of unimplemented devices
- SAI
- PWM
- CAN
* Add/rework few comments
Signed-off-by: J
Where architecturally one ARM_FEATURE_X flag implies another
ARM_FEATURE_Y, we allow the CPU init function to only set X, and then
set Y for it. Currently we do this in two places -- we set a few
flags in arm_cpu_post_init() because we need them to decide which
properties to create on the CPU obje
From: Richard Henderson
This feature allows the operating system to set TCR_ELx.HWU*
to allow the implementation to use the PBHA bits from the
block and page descriptors for for IMPLEMENTATION DEFINED
purposes. Since QEMU has no need to use these bits, we may
simply ignore them.
Signed-off-by:
From: Jean-Christophe Dubois
* Add TZASC as unimplemented device.
- Allow bare metal application to access this (unimplemented) device
* Add CSU as unimplemented device.
- Allow bare metal application to access this (unimplemented) device
* Add 4 missing PWM devices
Signed-off-by: Jean-Chris
On 2023/08/31 17:59, Alexander Graf wrote:
On 31.08.23 10:53, Akihiko Odaki wrote:
On 2023/08/31 17:12, Philippe Mathieu-Daudé wrote:
On 30/8/23 18:14, Alexander Graf wrote:
Recent versions of macOS use clang instead of gcc. The
OS_OBJECT_USE_OBJC
define is only necessary when building with
' of https://gitlab.com/stefanha/qemu into
staging (2023-08-30 09:20:27 -0400)
are available in the Git repository at:
https://git.linaro.org/people/pmaydell/qemu-arm.git
tags/pull-target-arm-20230831
for you to fetch changes up to e73b8bb8a3e9a162f70e9ffbf922d4fafc96bbfb:
hw/arm: Se
From: Richard Henderson
This value is only 4 bits wide.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
Reviewed-by: Philippe Mathieu-Daudé
Message-id: 20230811214031.171020-2-richard.hender...@linaro.org
Signed-off-by: Peter Maydell
---
target/arm/cpu.h | 3 ++-
1 file changed,
From: Richard Henderson
Like FEAT_TRF (Self-hosted Trace Extension), suppress tracing
external to the cpu, which is out of scope for QEMU.
Signed-off-by: Richard Henderson
Reviewed-by: Peter Maydell
Message-id: 20230811214031.171020-10-richard.hender...@linaro.org
Signed-off-by: Peter Maydell
M-profile CPUs generally allow configuration of the number of MPU
regions that they have. We don't currently model this, so our
implementations of some of the board models provide CPUs with the
wrong number of regions. RTOSes like Zephyr that hardcode the
expected number of regions may therefore
From: Richard Henderson
Do not hard-code the constants for Neoverse V1.
Signed-off-by: Richard Henderson
Reviewed-by: Peter Maydell
Message-id: 20230811214031.171020-6-richard.hender...@linaro.org
Signed-off-by: Peter Maydell
---
target/arm/tcg/cpu64.c | 48 --
From: Jean-Christophe Dubois
* Add TZASC as unimplemented device.
- Allow bare metal application to access this (unimplemented) device
* Add CSU as unimplemented device.
- Allow bare metal application to access this (unimplemented) device
* Add various memory segments
- OCRAM
- OCRAM EPDC
From: Alex Bennée
This is a mandatory feature for Armv8.1 architectures but we don't
state the feature clearly in our emulation list. Also include
FEAT_CRC32 comment in aarch64_max_tcg_initfn for ease of grepping.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Alex Bennée
Message-id: 20230
In the twl92230 device, use int64_t for the two state fields
sec_offset and alm_sec, because we set these to values that
are either time_t or differences between two time_t values.
These fields aren't saved in vmstate anywhere, so we can
safely widen them.
Signed-off-by: Peter Maydell
Reviewed-b
From: Jean-Christophe Dubois
i.MX7 IOMUX GPR device is not equivalent to i.MX6UL IOMUXC GPR device.
In particular, register 22 is not present on i.MX6UL and this is actualy
The only register that is really emulated in the i.MX7 IOMUX GPR device.
Note: The i.MX6UL code is actually also implementi
From: Jean-Christophe Dubois
* Add Addr and size definition for most i.MX6UL devices in i.MX6UL header file.
* Use those newly defined named constants whenever possible.
* Standardize the way we init a familly of unimplemented devices
- SAI
- PWM
- CAN
* Add/rework few comments
Signed-off-
From: Jean-Christophe Dubois
The SRC device is normally used to start the secondary CPU.
When running Linux directly, QEMU is emulating a PSCI interface that UBOOT
is installing at boot time and therefore the fact that the SRC device is
unimplemented is hidden as Qemu respond directly to PSCI re
In the m48t59 device we almost always use 64-bit arithmetic when
dealing with time_t deltas. The one exception is in set_alarm(),
which currently uses a plain 'int' to hold the difference between two
time_t values. Switch to int64_t instead to avoid any possible
overflow issues.
Signed-off-by: P
The functions qemu_get_timedate() and qemu_timedate_diff() take
and return a time offset as an integer. Coverity points out that
means that when an RTC device implementation holds an offset
as a time_t, as the m48t59 does, the time_t will get truncated.
(CID 1507157, 1517772).
The functions work w
The architecture requires (R_TYTWB) that an attempt to return from EL3
when SCR_EL3.{NSE,NS} are {1,0} is an illegal exception return. (This
enforces that the CPU can't ever be executing below EL3 with the
NSE,NS bits indicating an invalid security state.)
We were missing this check; add it.
Sign
Peter Maydell writes:
> On Thu, 31 Aug 2023 at 10:53, Alex Bennée wrote:
>>
>>
>> Peter Maydell writes:
>>
>> > On Thu, 31 Aug 2023 at 01:57, Stefano Stabellini
>> > wrote:
>> >> As Xen is gaining R52 and R82 support, it would be great to be able to
>> >> use QEMU for development and testin
On Fri, Aug 25, 2023 at 10:08:40AM -0300, Daniel Henrique Barboza wrote:
> All generic CPUs call riscv_cpu_add_user_properties(). The 'max' CPU
> calls riscv_init_max_cpu_extensions(). Both can be moved to a common
> instance_post_init() callback, implemented in riscv_cpu_post_init(),
> called by a
On Fri, Aug 25, 2023 at 10:08:41AM -0300, Daniel Henrique Barboza wrote:
> This CPU only exists if we're compiling with KVM so move it to the kvm
> specific file. While we're at it, change its class_init() to enable the
> user_extensions_flag class property, sparing us from having to execute
> risc
On Fri, Aug 25, 2023 at 10:08:42AM -0300, Daniel Henrique Barboza wrote:
> We'll need to export these arrays to the accelerator classes in the next
> patches. Mark them as 'const' now to minimize changes in the future.
Not to "minimize changes in the future", but "because they should
not be modifi
On Fri, Aug 25, 2023 at 10:08:43AM -0300, Daniel Henrique Barboza wrote:
> We'll introduce the KVM accelerator class with a 'cpu_instance_init'
> implementation that is going to be invoked during the common
> riscv_cpu_post_init() (via accel_cpu_instance_init()). This
> instance_init will execute K
On Fri, Aug 25, 2023 at 10:08:44AM -0300, Daniel Henrique Barboza wrote:
> Add a KVM accelerator class like we did with TCG. The difference is
> that, at least for now, we won't be using a realize() implementation for
> this accelerator.
>
> We'll start by assiging kvm_riscv_cpu_add_kvm_properties
On Fri, Aug 25, 2023 at 10:08:45AM -0300, Daniel Henrique Barboza wrote:
> Move the files to a 'kvm' dir to promote more code separation between
> accelerators and making our lives easier supporting build options such
> as --disable-tcg.
>
> Rename kvm.c to kvm-cpu.c to keep it in line with its TC
On Fri, Aug 25, 2023 at 10:08:46AM -0300, Daniel Henrique Barboza wrote:
> The function is doing way more than just init user properties. We would
> also like to use the 'user_extension_properties' class property, as the
> TCG driver is already using, to decide whether KVM should expose user
> prop
On Thu, 31 Aug 2023 at 11:49, Alex Bennée wrote:
> Peter Maydell writes:
> > All our MPS2/MPS3 boards are M-profile. That means we have the
> > device models for all the interesting devices on the board, but
> > it would be simpler to write the an536 board model separately.
> > (In particular, th
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