On 8/24/23 18:45, Peter Maydell wrote:
We use a variable-length array in inet_get_free_port_multiple().
This is only test code called at the start of a test, so switch to a
heap allocation instead.
The codebase has very few VLAs, and if we can get rid of them all we
can make the compiler error o
On 24/8/23 23:04, del...@kernel.org wrote:
From: Helge Deller
Add two macros which convert priviledge level to/from MMU index:
- PRIV_TO_MMU_IDX(priv)
returns the MMU index for the given priviledge level
- MMU_IDX_TO_PRIV(mmu_idx)
returns the corresponding priviledge level for this
On 24/8/23 23:04, del...@kernel.org wrote:
From: Helge Deller
The hppa CPU has 4 priviledge levels (0-3).
Mention the missing PL1 and PL2 levels, although the Linux kernel
uses only 0 (KERNEL) and 3 (USER). Not sure about HP-UX.
Signed-off-by: Helge Deller
---
target/hppa/cpu.h | 3 +++
1
Gurchetan Singh writes:
> On Wed, Aug 23, 2023 at 4:07 AM Alyssa Ross wrote:
>
>> Gurchetan Singh writes:
>>
>> > - Official "release commits" issued for rutabaga_gfx_ffi,
>> > gfxstream, aemu-base. For example, see crrev.com/c/4778941
>> >
>> > - The release commits can make packaging easie
On 24/8/23 23:04, del...@kernel.org wrote:
From: Helge Deller
Avoid using hardcoded values when calling the tlb_flush*() functions.
Instead define the correct mask (HPPA_MMU_FLUSH_MASK) and use it.
Skip flushing the MMU for physical addresses.
Alternatively:
Instead, define and use HPPA_MM
On 24/8/23 23:04, del...@kernel.org wrote:
From: Helge Deller
Convert hppa_get_physical_address() to use the privilege helper macro.
Signed-off-by: Helge Deller
---
target/hppa/mem_helper.c | 9 +
1 file changed, 5 insertions(+), 4 deletions(-)
Reviewed-by: Philippe Mathieu-Daudé
Ping?
On 5/7/23 13:44, Philippe Mathieu-Daudé wrote:
Hi Alex,
On 17/11/22 18:25, Alex Bennée wrote:
The bullet points are quite long and contain process tips. Move those
bits of the bullet to the relevant sections and link to them. Use a
table for nicer formatting of the checklist.
Signed-off
On 25/8/23 04:32, alloc.yo...@outlook.com wrote:
From: alloc
Convert free to g_free to match g_new and g_malloc functions.
Signed-off-by: alloc
Fixes: cc2b33eab0 ("softmmu/dirtylimit: Implement vCPU dirtyrate
calculation periodically")
Fixes: baa609832e ("softmmu/dirtylimit: Implement vir
On 24/8/23 18:39, Alex Bennée wrote:
This was always NULL so drop it.
Signed-off-by: Alex Bennée
Acked-by: Ilya Leoshkevich
---
gdbstub/gdbstub.c | 16
1 file changed, 8 insertions(+), 8 deletions(-)
Reviewed-by: Philippe Mathieu-Daudé
On 24/8/23 18:39, Alex Bennée wrote:
Try and make the self reported global hack a little less hackish by
providing a query function instead. As gdb_has_xml was always set if
we negotiated XML we can now use the presence of ->target_xml as the
test instead.
Signed-off-by: Alex Bennée
---
gdbst
On 24/8/23 18:39, Alex Bennée wrote:
Use proper kdoc style comments for this API function.
Signed-off-by: Alex Bennée
---
include/exec/gdbstub.h | 10 ++
gdbstub/gdbstub.c | 6 --
2 files changed, 10 insertions(+), 6 deletions(-)
Reviewed-by: Philippe Mathieu-Daudé
On 25.08.23 08:57, ThinerLogoer wrote:
Hello,
At 2023-08-23 23:34:11, "David Hildenbrand" wrote:
For migration purposes, users might want to reuse the default RAM
backend id, but specify a different memory backend.
For example, to reuse "pc.ram" on q35, one has to set
-machine q35,memory-
On Tue Aug 22, 2023 at 10:53 PM AEST, Philippe Mathieu-Daudé wrote:
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> target/ppc/translate.c | 10 +-
> target/ppc/translate/vsx-impl.c.inc | 19 ++-
> 2 files changed, 3 insertions(+), 26 deletions(-)
>
> diff --g
On 24/8/23 18:38, Alex Bennée wrote:
From: Daniel P. Berrangé
The `ccache` tool can be very effective at reducing compilation times
when re-running pipelines with only minor changes each time. For example
a fresh 'build-system-fedora' job will typically take 20 minutes on the
gitlab.com shared
24.08.2023 19:38, Alex Bennée wrote:
From: Daniel P. Berrangé
The `ccache` tool can be very effective at reducing compilation times
when re-running pipelines with only minor changes each time. For example
a fresh 'build-system-fedora' job will typically take 20 minutes on the
gitlab.com shared
On [2023 Aug 24] Thu 16:32:22, Peter Maydell wrote:
> Replace an on-stack variable length array in of_dpa_ig() with
> a g_autofree heap allocation.
>
> The codebase has very few VLAs, and if we can get rid of them all we
> can make the compiler error on new additions. This is a defensive
> measur
On [2023 Aug 24] Thu 16:32:24, Peter Maydell wrote:
> Use a heap allocation instead of a variable length array in
> tap_receive_iov().
>
> The codebase has very few VLAs, and if we can get rid of them all we
> can make the compiler error on new additions. This is a defensive
> measure against sec
On [2023 Aug 24] Thu 16:32:23, Peter Maydell wrote:
> Use a g_autofree heap allocation instead of a variable length
> array in dump_receive_iov().
>
> The codebase has very few VLAs, and if we can get rid of them all we
> can make the compiler error on new additions. This is a defensive
> measure
On Tue Aug 22, 2023 at 10:40 PM AEST, Philippe Mathieu-Daudé wrote:
> This series factor the "byteswap each halfword within a
> 32/64-bit value" code duplication as generic helpers.
>
> Modulo the documentation added, there is a good negative
> diff-stat, so I believe this is a win from a maintaina
Ping?
On 19/7/23 16:17, Philippe Mathieu-Daudé wrote:
Do not silently ignore the user request of using MSIX.
Remove the TODO. Coverity reported this as CID 1508725.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/usb/hcd-xhci-pci.c | 21 -
1 file changed, 16 insertions(+),
On Thu, Aug 24, 2023 at 02:26:42PM -0400, Stefan Hajnoczi wrote:
> I've done most of the audit necessary to understand which AioContext is
> used where. The call graph is large because qio_channel_yield() is used
> internally by qio_channel_readv_full_all_eof(),
> qio_channel_writev_full_all(), and
On 18/8/23 13:00, Philippe Mathieu-Daudé wrote:
ping?
On 10/7/23 11:49, Philippe Mathieu-Daudé wrote:
Similarly to commit e414ed2c47 ("virtio-iommu: Use
target-agnostic qemu_target_page_mask"), Replace the
target-specific TARGET_PAGE_SIZE and TARGET_PAGE_MASK
definitions by a call to the runtim
On Fri, Aug 25, 2023 at 10:46:29AM +0300, Michael Tokarev wrote:
> 24.08.2023 19:38, Alex Bennée wrote:
> > From: Daniel P. Berrangé
> >
> > The `ccache` tool can be very effective at reducing compilation times
> > when re-running pipelines with only minor changes each time. For example
> > a fre
On Mon Aug 21, 2023 at 12:59 PM AEST, Richard Henderson wrote:
> Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1779
> Signed-off-by: Richard Henderson
Should go to qemu-stable I would say? Thanks for fixing.
Reviewed-by: Nicholas Piggin
> ---
> target/ppc/cpu.c | 1 +
> 1 file chan
On Tue Aug 22, 2023 at 2:44 PM AEST, Pavel Dovgalyuk wrote:
> On 11.08.2023 04:47, Nicholas Piggin wrote:
> > RR CPU switching is driven by timers and events so it is deterministic
> > like everything else. Record a CPU switch event and use that to drive
> > the CPU switch on replay.
> >
> > Signe
On 25/8/23 09:46, Michael Tokarev wrote:
24.08.2023 19:38, Alex Bennée wrote:
From: Daniel P. Berrangé
The `ccache` tool can be very effective at reducing compilation times
when re-running pipelines with only minor changes each time. For example
a fresh 'build-system-fedora' job will typically
On 25/08/2023 10.34, Philippe Mathieu-Daudé wrote:
...
__FILE__ is used by assert() family, some DEBUG_PRINTF(), but mainly
by "qapi/error.h", so all error_setg*() calls.
This has been bugging me since quite some time, since if you build
the same QEMU in different paths (usually on different mac
On Wed, 2023-08-23 at 22:00 +0300, Michael Tokarev wrote:
> 23.08.2023 21:38, David Woodhouse wrote:
> > On Wed, 2023-08-23 at 09:53 +0300, Michael Tokarev wrote:
> > >
> > > include/hw/xen/interface/arch-x86/xen-x86_64.h | 2 +-
> > > include/hw/xen/interface/arch-x86/xen.h | 2 +-
> > >
On 2023/08/23 15:09, Manivannan Sadhasivam wrote:
On Fri, Aug 18, 2023 at 10:46:02PM +0900, Shunsuke Mie wrote:
Hi all,
We are proposing to add a new test syste to Linux for PCIe Endpoint. That
can be run on QEMU without real hardware. At present, partially we have
confirmed that pci-epf-test
David Hildenbrand writes:
> On 25.08.23 08:57, ThinerLogoer wrote:
>> Hello,
>>
>> At 2023-08-23 23:34:11, "David Hildenbrand" wrote:
>>> For migration purposes, users might want to reuse the default RAM
>>> backend id, but specify a different memory backend.
>>>
>>> For example, to reuse "pc.r
On 25.08.23 11:10, Markus Armbruster wrote:
David Hildenbrand writes:
On 25.08.23 08:57, ThinerLogoer wrote:
Hello,
At 2023-08-23 23:34:11, "David Hildenbrand" wrote:
For migration purposes, users might want to reuse the default RAM
backend id, but specify a different memory backend.
For
25.08.2023 11:34, Philippe Mathieu-Daudé wrote:
...
__FILE__ is used by assert() family, some DEBUG_PRINTF(), but mainly
by "qapi/error.h", so all error_setg*() calls.
This has been bugging me since quite some time, since if you build
the same QEMU in different paths (usually on different machin
It is true, that there is no problem during runtime
from the first sight, because the memmory is lost just
before qemu exits. Nevertheless, this change is necessary,
because AddressSanitizer is not able to recognize this
situation and produces crash-report (which is
false-positive in fact). Lots of
On Fri Aug 18, 2023 at 1:36 PM AEST, Akihiko Odaki wrote:
> GDB has XML support since 6.7 which was released in 2007.
> It's time to remove support for old GDB versions without XML support.
These 3 patches might be better to go ahead in a preparation series
with "remove support for gdb 6.7" in the
David Hildenbrand writes:
> On 25.08.23 11:10, Markus Armbruster wrote:
>> David Hildenbrand writes:
>>
>>> On 25.08.23 08:57, ThinerLogoer wrote:
Hello,
At 2023-08-23 23:34:11, "David Hildenbrand" wrote:
> For migration purposes, users might want to reuse the default RAM
>>
On 25.08.23 11:56, Markus Armbruster wrote:
David Hildenbrand writes:
On 25.08.23 11:10, Markus Armbruster wrote:
David Hildenbrand writes:
On 25.08.23 08:57, ThinerLogoer wrote:
Hello,
At 2023-08-23 23:34:11, "David Hildenbrand" wrote:
For migration purposes, users might want to reuse
On 23/08/2023 12:58, David Woodhouse wrote:
From: David Woodhouse
Upstream Xen now ignores this flag¹, since the only guest kernel ever to
use it was buggy.
¹ https://xenbits.xen.org/gitweb/?p=xen.git;a=commitdiff;h=19c6cbd909
Signed-off-by: David Woodhouse
---
We do take an argument to emul
On 25.08.23 11:59, David Hildenbrand wrote:
On 25.08.23 11:56, Markus Armbruster wrote:
David Hildenbrand writes:
On 25.08.23 11:10, Markus Armbruster wrote:
David Hildenbrand writes:
On 25.08.23 08:57, ThinerLogoer wrote:
Hello,
At 2023-08-23 23:34:11, "David Hildenbrand" wrote:
For
Am 24.08.23 um 15:38 schrieb Fiona Ebner:
> Fails without the previous commit "hw/ide: reset: cancel async DMA
> operation before reseting state".
>
> I haven't ever written such a test before, but I wanted something to
> expose the problem more easily. It hardcodes the behavior that the
> pending
Executing a program under QEMU's user mode subjects the entire
program, including all library calls, to translation. It's important
to understand that many of these library functions are optimized
specifically for the guest architecture. Therefore, their
translation might not yield the most efficie
This commit implements the -native-bypass support in linux-user. The
native_calls_enabled() function can be true only when the
'-native-bypass' option is given.
Signed-off-by: Yeqi Fu
---
include/native/native.h | 9 +
linux-user/main.c | 38 ++
This commit implements a shared library, where native functions are
rewritten as special instructions. At runtime, user programs load
the shared library, and special instructions are executed when
native functions are called.
Signed-off-by: Yeqi Fu
---
Makefile| 2 +
Since both TCG tests and libnative libraries require cross-building,
the config files for cross-building, config_target_mak, are now saved
in the cross-build directory for sharing. This allows TCG tests and
libnative libraries to use these config files through symbolic links
when cross-building con
Signed-off-by: Yeqi Fu
---
include/qemu/envlist.h| 13 ++
tests/unit/meson.build| 1 +
tests/unit/test-envlist.c | 94 +++
util/envlist.c| 67 +++-
4 files changed, 165 insertions(+), 10 deletions(-)
create mode
This commit introduces support for native library calls on the
i386 target. When encountering special instructions reserved
for native calls, this commit extracts the function name and
generates the corresponding native call.
Signed-off-by: Yeqi Fu
---
configs/targets/i386-linux-user.mak | 1
Signed-off-by: Yeqi Fu
---
docs/user/index.rst| 1 +
docs/user/native_calls.rst | 90 ++
2 files changed, 91 insertions(+)
create mode 100644 docs/user/native_calls.rst
diff --git a/docs/user/index.rst b/docs/user/index.rst
index 782d27cda2..d3fc9b7a
This commit introduces support for native library calls on the
mips target. When encountering special instructions reserved
for native calls, this commit extracts the function name and
generates the corresponding native call.
Signed-off-by: Yeqi Fu
---
configs/targets/mips-linux-user.mak | 1
This commit implements tcg opcodes and helpers for native library
calls. A table is used to store the parameter types and return value
types for each native library function. In terms of types, only three
types are of real concern: the two base sizes int and intptr_t, and
if the value is a pointer,
This commit introduces support for native library calls on the
arm target. When encountering special instructions reserved
for native calls, this commit extracts the function name and
generates the corresponding native call.
Signed-off-by: Yeqi Fu
---
configs/targets/aarch64-linux-user.mak | 1
Introduce a new test for native calls to ensure their functionality.
The process involves cross-compiling the test cases, building them
as dynamically linked binaries, and running these binaries which
necessitates the addition of the appropriate interpreter prefix.
Signed-off-by: Yeqi Fu
---
tes
On 24/8/23 18:23, Michael Tokarev wrote:
24.08.2023 18:31, Alex Bennée wrote:
..
which bisects to:
commit f7eaf9d702efdd02481d5f1c25f7d8e0ffb64c6e (HEAD,
refs/bisect/bad)
Author: Richard Henderson
Date: Tue Aug 1 10:46:03 2023 -0700
accel/tcg: Do not issue misaligned i/o
On 24/8/23 20:31, Richard Henderson wrote:
On 8/24/23 08:31, Alex Bennée wrote:
It's some sort of timing issue, which sometimes goes away when re-run.
I was re-running tests *a lot* in order to get them to go green while
running the 8.1 release.
There is a definite regression point for the tes
On Thu, 24 Aug 2023 13:49:00 -0700
Fan Ni wrote:
> On Mon, Aug 07, 2023 at 09:53:42AM +0100, Jonathan Cameron wrote:
> > On Tue, 25 Jul 2023 18:39:56 +
> > Fan Ni wrote:
> >
> > > From: Fan Ni
> > >
> > > Not all dpa range in the dc regions is valid to access until an extent
> > > coverin
It is true, that there is no problem during runtime
from the first sight, because the memory is lost just
before qemu exits. Nevertheless, this change is necessary,
because AddressSanitizer is not able to recognize this
situation and produces crash-report (which is
false-positive in fact). Lots of
cpu_type_by_name is used to get the cpu type name from the command
line -cpu.
Currently it is only used by parse_cpu_option. In the next patch, it
will be used by other cpu query functions.
Signed-off-by: LIU Zhiwei
---
cpu.c | 31 +++
1 file changed, 19 insertions(+
This API used for output current configuration for one specified CPU.
Currently only RISC-V frontend implements this API.
Signed-off-by: LIU Zhiwei
---
cpu.c | 8
include/exec/cpu-common.h | 1 +
target/riscv/cpu.c| 10 ++
target/riscv/cpu.h
This make the cpu works the similar way like the -device option.
For device option,
"""
./qemu-system-riscv64 -device e1000,help
e1000 options:
acpi-index=- (default: 0)
addr= - Slot and optional function number, example: 06.0 or
06 (default: -1)
autonegotiation= - on/off (de
Some times we want to know what is the really mean of one cpu option.
For example, in RISC-V, we usually specify a cpu in this way:
-cpu rv64,v=on
If we don't look into the source code, we can't get the ISA extensions
of this -cpu command line.
In this patch set, we add one list_cpu_props API for
This patch adds a few unimplemented TZ devices (TZASC and CSU) to
i.MX6UL and i.MX7 processors to avoid bare metal application to
experiment "bus error" when acccessing these devices.
It also adds some internal memory segments (OCRAM) to the i.MX7 to
allow bare metal application to use them.
Last
i.MX7 IOMUX GPR device is not equivalent to i.MX6UL IOMUXC GPR device.
In particular, register 22 is not present on i.MX6UL and this is actualy
The only register that is really emulated in the i.MX7 IOMUX GPR device.
Note: The i.MX6UL code is actually also implementing the IOMUX GPR device
as an u
* Add Addr and size definition for all i.MX7 devices in i.MX7 header file.
* Use those newly defined named constants whenever possible.
* Standardize the way we init a familly of unimplemented devices
- SAI
- PWM
- CAN
* Add/rework few comments
Signed-off-by: Jean-Christophe Dubois
---
hw/
* Add Addr and size definition for most i.MX6UL devices in i.MX6UL header file.
* Use those newly defined named constants whenever possible.
* Standardize the way we init a familly of unimplemented devices
- SAI
- PWM
- CAN
* Add/rework few comments
Signed-off-by: Jean-Christophe Dubois
---
The SRC device is normally used to start the secondary CPU.
When running Linux directly, QEMU is emulating a PSCI interface that UBOOT
is installing at boot time and therefore the fact that the SRC device is
unimplemented is hidden as Qemu respond directly to PSCI requets without
using the SRC dev
* Add TZASC as unimplemented device.
- Allow bare metal application to access this (unimplemented) device
* Add CSU as unimplemented device.
- Allow bare metal application to access this (unimplemented) device
* Add various memory segments
- OCRAM
- OCRAM EPDC
- OCRAM PXP
- OCRAM S
-
* Add TZASC as unimplemented device.
- Allow bare metal application to access this (unimplemented) device
* Add CSU as unimplemented device.
- Allow bare metal application to access this (unimplemented) device
* Add 4 missing PWM devices
Signed-off-by: Jean-Christophe Dubois
Reviewed-by: Phil
25.08.2023 14:58, Dmitry Frolov wrote:
It is true, that there is no problem during runtime
from the first sight, because the memory is lost just
before qemu exits. Nevertheless, this change is necessary,
because AddressSanitizer is not able to recognize this
situation and produces crash-report (w
Based-on: 20230824221440.484675-1-dbarb...@ventanamicro.com
("[PATCH RESEND v8 00/20] riscv: 'max' CPU, detect user choice in TCG")
Hi,
The idea of this work was hinted at during a review [1] where Phil
mentioned that we should handle TCG specific constraints in
AccelCPUClass::cpu_realizefn(). Wh
We'll need to export these arrays to the accelerator classes in the next
patches. Mark them as 'const' now to minimize changes in the future.
Note that 'riscv_cpu_options' will also be exported, but can't be marked
as 'const', because the properties are changed via
qdev_property_add_static().
Sig
The 'max' CPU type is being configured during init() time by enabling
all relevant extensions.
Instead of checking for 'max' CPU to enable all extensions, add a new
CPU cfg flag 'max_features' that can be used by any CPU during its
cpu_init() function. We'll check for it during post_init() time to
riscv_cpu_realize_tcg() was added to allow TCG cpus to have a different
realize() path during the common riscv_cpu_realize(), making it a good
choice to start moving TCG exclusive code to tcg-cpu.c.
Rename it to tcg_cpu_realizefn() and assign it as a implementation of
accel::cpu_realizefn(). tcg_c
The function is doing way more than just init user properties. We would
also like to use the 'user_extension_properties' class property, as the
TCG driver is already using, to decide whether KVM should expose user
properties or not.
Rename kvm_riscv_init_user_properties() to riscv_init_kvm_registe
Move the remaining of riscv_tcg_ops now that we have a working realize()
implementation.
Signed-off-by: Daniel Henrique Barboza
---
target/riscv/cpu.c | 58 -
target/riscv/cpu.h | 4 ---
target/riscv/tcg/tcg-cpu.c | 59
Move the files to a 'kvm' dir to promote more code separation between
accelerators and making our lives easier supporting build options such
as --disable-tcg.
Rename kvm.c to kvm-cpu.c to keep it in line with its TCG counterpart.
Signed-off-by: Daniel Henrique Barboza
---
hw/riscv/virt.c
This property indicates if a CPU supports TCG acceleration. All CPUs but
the 'host' CPU supports it.
The error in tcg_cpu_realizefn() can now be made generic in case more
non-TCG CPUs are added in the future.
Signed-off-by: Daniel Henrique Barboza
---
target/riscv/cpu-qom.h | 1 +
target/r
Add a KVM accelerator class like we did with TCG. The difference is
that, at least for now, we won't be using a realize() implementation for
this accelerator.
We'll start by assiging kvm_riscv_cpu_add_kvm_properties(), renamed to
kvm_cpu_instance_init(), as a 'cpu_instance_init' implementation. Ch
target/riscv/cpu.c needs to handle all possible accelerators (TCG and
KVM at this moment) during both init() and realize() time. This forces
us to resort to a lot of "if tcg" and "if kvm" throughout the code,
which isn't wrong, but can get cluttered over time. Splitting
acceleration specific code f
All code related to MISA TCG properties is also moved.
At this point, all TCG properties handling is done in tcg-cpu.c, all KVM
properties handling is done in kvm-cpu.c.
Signed-off-by: Daniel Henrique Barboza
---
target/riscv/cpu.c | 89 --
target/ris
riscv_cpu_add_misa_properties() is being used to fill the missing KVM
MISA properties but it is a TCG helper that was adapted to do so. We'll
move it to tcg-cpu.c in the next patches, meaning that KVM needs to fill
the remaining MISA properties on its own.
Do not use riscv_cpu_add_misa_properties(
On 25.08.2023 12:29, Dmitry Frolov wrote:
> It is true, that there is no problem during runtime
> from the first sight, because the memmory is lost just
> before qemu exits. Nevertheless, this change is necessary,
> because AddressSanitizer is not able to recognize this
> situation and produces cra
Priv spec validation is TCG specific. Move it to the TCG accel class.
Signed-off-by: Daniel Henrique Barboza
---
target/riscv/cpu.c | 39 --
target/riscv/cpu.h | 2 --
target/riscv/tcg/tcg-cpu.c | 39 ++
3 f
This function is the core of the RISC-V validations for TCG CPUs, and it
has a lot going on.
Functions in cpu.c were made public to allow them to be used by the KVM
accelerator class later on. 'cpu_cfg_ext_get_min_version()' is notably
hard to move it to another file due to its dependency with isa
This follows the same idea of 'tcg_support' property added in the
previous patch. Note that we're now implementing the 'cpu_realizefn' for
the KVMAccel class since this verification is done in realize() time.
Supporting vendor CPUs with KVM is not possible. We rely on the
extension support of the
We'll introduce the KVM accelerator class with a 'cpu_instance_init'
implementation that is going to be invoked during the common
riscv_cpu_post_init() (via accel_cpu_instance_init()). This
instance_init will execute KVM exclusive code that TCG doesn't care
about, such as adding KVM specific proper
All generic CPUs call riscv_cpu_add_user_properties(). The 'max' CPU
calls riscv_init_max_cpu_extensions(). Both can be moved to a common
instance_post_init() callback, implemented in riscv_cpu_post_init(),
called by all CPUs. The call order then becomes:
riscv_cpu_init() -> cpu_init() of each CPU
tcg_cpu_instance_init() will be the 'cpu_instance_init' impl for the TCG
accelerator. It'll be called from within riscv_cpu_post_init(), via
accel_cpu_instance_init(), similar to what happens with KVM. In fact, to
preserve behavior, the implementation will be similar to what
riscv_cpu_post_init() a
We want to use a post_init hook to call the cpu_instance_init callback
from each accelerator, moving repetitive code from the cpu_init()
functions to be handled by the accelerator class. But first we need to
ensure that we don't change behavior - vendor CPUs shouldn't expose user
properties, generi
This CPU only exists if we're compiling with KVM so move it to the kvm
specific file. While we're at it, change its class_init() to enable the
user_extensions_flag class property, sparing us from having to execute
riscv_cpu_add_user_properties() by hand and letting the post_init() hook
do the work.
This array will be read by the TCG accel class, allowing it to handle
priv spec verifications on its own. The array will remain here in cpu.c
because it's also used by the riscv,isa string function.
To export it we'll make it constant and finish it with an empty element
since ARRAY_SIZE() won't wo
Having multiple vhost devices, some filtering out fd-less memslots and
some not, can mess up the "used_memslot" accounting. Consequently our
"free memslot" checks become unreliable and we might run out of free
memslots at runtime later.
An example sequence which can trigger a potential issue that
Let's track how many memslots are required by plugged memory devices and
how many are currently actually getting used by plugged memory
devices.
"required - used" is the number of reserved memslots. For now, the number
of used and required memslots is always equal, and there are no
reservations. T
Let's allow for marking memory regions unmergeable, to teach
flatview code and vhost to not merge adjacent aliases to the same memory
region into a larger memory section; instead, we want separate aliases to
stay separate such that we can atomically map/unmap aliases without
affecting other aliases
Quoting from patch #14:
Having large virtio-mem devices that only expose little memory to a VM
is currently a problem: we map the whole sparse memory region into the
guest using a single memslot, resulting in one gigantic memslot in KVM.
KVM allocates metadata for the whole memslot
We really only care about the RAM memory region not being mapped into
an address space yet as long as we're still setting up the
RamDiscardManager. Once mapped into an address space, memory notifiers
would get notified about such a region and any attempts to modify the
RamDiscardManager would be wr
Checking whether the memory regions are equal is sufficient: if they are
equal, then most certainly the contained fd is equal.
The whole vhost-user memslot handling is suboptimal and overly
complicated. We shouldn't have to lookup a RAM memory regions we got
notified about in vhost_user_get_mr_dat
We want to place non-qmp stubs in there, so let's rename it. While at
it, put it into the MAINTAINERS file under "Memory devices".
Signed-off-by: David Hildenbrand
---
MAINTAINERS| 1 +
stubs/{qmp_memory_device.c => memory_device.c} | 0
stubs/meson.build
Let's return the number of free slots instead of only checking if there
is a free slot. While at it, check all address spaces, which will also
consider SMM under x86 correctly.
Make the stub return UINT_MAX, such that we can call the function
unconditionally.
This is a preparation for memory devi
Let's return the number of free slots instead of only checking if there
is a free slot. Required to support memory devices that consume multiple
memslots.
This is a preparation for memory devices that consume multiple memslots.
Signed-off-by: David Hildenbrand
---
hw/mem/memory-device.c| 2
Having large virtio-mem devices that only expose little memory to a VM
is currently a problem: we map the whole sparse memory region into the
guest using a single memslot, resulting in one gigantic memslot in KVM.
KVM allocates metadata for the whole memslot, which can result in quite
some memory w
We want to support memory devices that have a memory region container as
device memory region that maps multiple RAM memory regions. Let's start
by supporting memory devices that statically map multiple RAM memory
regions and, thereby, consume multiple memslots.
We already have one device that use
We want to support memory devices that have a dynamically managed memory
region container as device memory region. This device memory region maps
multiple RAM memory subregions (e.g., aliases to the same RAM memory
region), whereby these subregions can be (un)mapped on demand.
Each RAM subregion w
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