Re: [PATCH 2/2] riscv: zicond: make default

On Thu, Aug 10, 2023 at 02:07:17PM -0400, Alistair Francis wrote: > On Tue, Aug 8, 2023 at 6:10 PM Vineet Gupta wrote: > > > > > > > > On 8/8/23 14:06, Daniel Henrique Barboza wrote: > > > (CCing Alistair and other reviewers) > > > > > > On 8/8/23 15:17, Vineet Gupta wrote: > > >> Again this helps

[PATCH 2/3] virtio-net: added replay blocker for guest_announce

From: Pavel Dovgalyuk This patch blocks record/replay when guest_announce is enabled, because this flag breaks loading the snapshots in deterministic execution mode. Signed-off-by: Pavel Dovgalyuk --- hw/net/virtio-net.c | 4 1 file changed, 4 insertions(+) diff --git a/hw/net/virtio-net

[PATCH 0/3] Record/replay patches

From: Pavel Dovgalyuk The set of patches include the following modifications: - fix for allowing record/replay with virtio-net - fix of the record/replay test Pavel Dovgalyuk (3): replay: improve determinism of virtio-net virtio-net: added replay blocker for guest_announce tests/avocado:

[PATCH 3/3] tests/avocado: fix waiting for vm shutdown in replay_linux

From: Pavel Dovgalyuk This patch fixes the race condition in waiting for shutdown of the replay linux test. Signed-off-by: Pavel Dovgalyuk Suggested-by: John Snow --- tests/avocado/replay_linux.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tests/avocado/replay_linux.p

[PATCH 1/3] replay: improve determinism of virtio-net

From: Pavel Dovgalyuk virtio-net device uses bottom halves for callbacks. These callbacks should be deterministic, because they affect VM state. This patch replaces BH invocations with corresponding replay functions, making them deterministic in record/replay mode. Signed-off-by: Pavel Dovgalyuk

Re: [QEMU PATCH v4 0/1] S3 support

Hi all, Please forgive me for asking. Do you have any other comments on my latest version patches about virtio-gpu S3 on Xen? Looking forward to your reply. On 2023/7/20 20:08, Jiqian Chen wrote: > v4: > > Hi all, > Thanks for Gerd Hoffmann's advice. V4 makes below changes: > * Use enum for fre

Re: [PATCH v5 08/11] target/loongarch: Reject la64-only instructions in la32 mode

Hi, Jiajie 在 2023/8/9 下午4:26, Jiajie Chen 写道: LoongArch64-only instructions are marked with regard to the instruction manual Table 2. LSX instructions are not marked for now for lack of public manual. Signed-off-by: Jiajie Chen --- target/loongarch/insn_trans/trans_arith.c.inc | 30

Re: [PATCH] disas/riscv: Further correction to LUI disassembly

On Thu, Aug 10, 2023 at 06:27:50PM +0200, Andrew Jones wrote: > On Thu, Aug 10, 2023 at 09:12:42AM -0700, Palmer Dabbelt wrote: > > On Thu, 10 Aug 2023 08:31:46 PDT (-0700), ajo...@ventanamicro.com wrote: > > > On Mon, Jul 31, 2023 at 11:33:20AM -0700, Richard Bagley wrote: > > > > The recent commi

Re: [PATCH] hw/pci-host: Allow extended config space access for Designware PCIe host

On Thu, 10 Aug 2023 at 18:51, Michael S. Tsirkin wrote: > > On Wed, Aug 09, 2023 at 10:22:50AM +, Jason Chien wrote: > > In pcie_bus_realize(), a root bus is realized as a PCIe bus and a non-root > > bus is realized as a PCIe bus if its parent bus is a PCIe bus. However, > > the child bus "dw-

Re: [PATCH v2 1/4] hw/i2c/aspeed: Fix I2CD_POOL_CTRL register bit field defination

Hello Hang, It is good practice to send a cover letter giving a quick summary of the changes. On 8/11/23 07:42, Hang Yu wrote: Fixed inconsistency between the regisiter bit field defination in headfile Fixed inconsistency between the register bit field definition header file and the ast2600

[PATCH v2 5/8] target/loongarch: Add avail_LSPW to check LSPW instructions

Signed-off-by: Song Gao --- target/loongarch/insn_trans/trans_privileged.c.inc | 8 target/loongarch/translate.h | 1 + 2 files changed, 9 insertions(+) diff --git a/target/loongarch/insn_trans/trans_privileged.c.inc b/target/loongarch/insn_trans/trans_privileged.

[PATCH v2 7/8] target/loongarch: Add avail_LSX to check LSX instructions

Signed-off-by: Song Gao --- target/loongarch/insn_trans/trans_lsx.c.inc | 1482 ++- target/loongarch/translate.h|2 + 2 files changed, 823 insertions(+), 661 deletions(-) diff --git a/target/loongarch/insn_trans/trans_lsx.c.inc b/target/loongarch/insn_trans/t

[PATCH v2 4/8] target/loongarch: Add avail_FP/FP_SP/FP_DP to check fpu instructions

Signed-off-by: Song Gao --- .../loongarch/insn_trans/trans_farith.c.inc | 96 --- target/loongarch/insn_trans/trans_fcmp.c.inc | 8 ++ target/loongarch/insn_trans/trans_fcnv.c.inc | 56 +-- .../loongarch/insn_trans/trans_fmemory.c.inc | 32 +++ target/loongarch/i

[PATCH v2 1/8] target/loongarch: Fix loongarch_la464_initfn() misses setting LSPW.

Reviewed-by: Richard Henderson Signed-off-by: Song Gao --- target/loongarch/cpu.c | 1 + 1 file changed, 1 insertion(+) diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c index dd1cd7d7d2..95e00a044c 100644 --- a/target/loongarch/cpu.c +++ b/target/loongarch/cpu.c @@ -391,6 +391,7 @@

[PATCH v2 0/8] Add some checks before translating instructions

Based-on: https://patchew.org/QEMU/20230809083258.1787464-...@jia.je/ Hi, This series adds some checks before translating instructions This includes: CPUCFG[1].IOCSR CPUCFG[2].FP CPUCFG[2].FP_SP CPUCFG[2].FP_DP CPUCFG[2].LSPW CPUCFG[2].LAM CPUCFG[2].LSX V2: - Add a check parameter to the TRAN

[PATCH v2 8/8] target/loongarch: Add avail_IOCSR to check iocsr instructions

Signed-off-by: Song Gao --- .../loongarch/insn_trans/trans_privileged.c.inc | 16 target/loongarch/translate.h | 2 +- 2 files changed, 9 insertions(+), 9 deletions(-) diff --git a/target/loongarch/insn_trans/trans_privileged.c.inc b/target/loongarch/insn_

[PATCH v2 2/8] target/loongarch: Add a check parameter to the TRANS macro

The default check parmeter is ALL, remove TRANS_64 marco. Suggested-by: Richard Henderson Signed-off-by: Song Gao --- target/loongarch/insn_trans/trans_arith.c.inc | 84 +- .../loongarch/insn_trans/trans_atomic.c.inc | 80 +- target/loongarch/insn_trans/trans_bit.c.inc | 56 +- .../lo

[PATCH v2 3/8] target/loongarch: Add avail_64 to check la64-only instructions

The la32 manual from [1], and it is not the final version. [1]: https://www.loongson.cn/uploads/images/2023041918122813624.%E9%BE%99%E8%8A%AF%E6%9E%B6%E6%9E%8432%E4%BD%8D%E7%B2%BE%E7%AE%80%E7%89%88%E5%8F%82%E8%80%83%E6%89%8B%E5%86%8C_r1p03.pdf Co-authored-by: Jiajie Chen Signed-off-by: Song Gao

[PATCH v2 6/8] target/loongarch: Add avail_LAM to check atomic instructions

Signed-off-by: Song Gao --- target/loongarch/insn_trans/trans_atomic.c.inc | 12 target/loongarch/translate.h | 1 + 2 files changed, 13 insertions(+) diff --git a/target/loongarch/insn_trans/trans_atomic.c.inc b/target/loongarch/insn_trans/trans_atomic.c.inc ind

Re: [PATCH v2 4/4] hw/i2c/aspeed: Add support for BUFFER ORGANIZATION in new register mode

On 8/11/23 07:42, Hang Yu wrote: Added support for the BUFFER ORGANIZATION option in reg I2CC_POOL_CTRL, BUFFER ORGANIZATION could be lower case when set to 1,The buffer is split into two parts: Lower 16 bytes for Tx and higher 16 bytes for Rx. Signed-off-by: Hang Yu --- hw/i2c/aspeed_i2c

Re: [PATCH 17/24] tcg/i386: Merge tcg_out_brcond{32,64}

On Tue, 8 Aug 2023 at 04:12, Richard Henderson wrote: > > Pass a rexw parameter instead of duplicating the functions. > > Signed-off-by: Richard Henderson > --- > tcg/i386/tcg-target.c.inc | 110 +- > 1 file changed, 49 insertions(+), 61 deletions(-) Reviewed

Re: [PATCH 18/24] tcg/i386: Merge tcg_out_setcond{32,64}

On Tue, 8 Aug 2023 at 04:14, Richard Henderson wrote: > > Pass a rexw parameter instead of duplicating the functions. > > Signed-off-by: Richard Henderson > --- Reviewed-by: Peter Maydell thanks -- PMM

Re: [PATCH 19/24] tcg/i386: Merge tcg_out_movcond{32,64}

On Tue, 8 Aug 2023 at 04:16, Richard Henderson wrote: > > Pass a rexw parameter instead of duplicating the functions. > > Signed-off-by: Richard Henderson > --- Reviewed-by: Peter Maydell thanks -- PMM

Re: [PATCH 20/24] tcg/i386: Add cf parameter to tcg_out_cmp

On Tue, 8 Aug 2023 at 04:13, Richard Henderson wrote: > > Add the parameter to avoid TEST and pass along to tgen_arithi. > All current users pass false. > > Signed-off-by: Richard Henderson > --- > tcg/i386/tcg-target.c.inc | 16 > 1 file changed, 8 insertions(+), 8 deletions(-)

Re: [PATCH for-8.2 v3 1/6] vfio/migration: Move from STOP_COPY to STOP in vfio_save_cleanup()

On 8/8/23 08:23, Avihai Horon wrote: On 07/08/2023 18:53, Cédric Le Goater wrote: External email: Use caution opening links or attachments [ Adding Juan and Peter for their awareness ] On 8/2/23 10:14, Avihai Horon wrote: Changing the device state from STOP_COPY to STOP can take time as the

Re: [PATCH 20/24] tcg/i386: Add cf parameter to tcg_out_cmp

On Fri, 11 Aug 2023 at 11:26, Peter Maydell wrote: > > On Tue, 8 Aug 2023 at 04:13, Richard Henderson > wrote: > > > > Add the parameter to avoid TEST and pass along to tgen_arithi. > > All current users pass false. > > > > Signed-off-by: Richard Henderson > > --- > > tcg/i386/tcg-target.c.inc

[PATCH trivial] qemu-img: omit errno value in error message

I'm getting io-qcow2-244 test failure on mips* due to output mismatch: Take an internal snapshot: -qemu-img: Could not create snapshot 'test': -95 (Operation not supported) +qemu-img: Could not create snapshot 'test': -122 (Operation not supported) No errors were found on the image. This is

Re: [PATCH 2/2] riscv: zicond: make default

On 8/10/23 15:07, Alistair Francis wrote: On Tue, Aug 8, 2023 at 6:10 PM Vineet Gupta wrote: On 8/8/23 14:06, Daniel Henrique Barboza wrote: (CCing Alistair and other reviewers) On 8/8/23 15:17, Vineet Gupta wrote: Again this helps with better testing and something qemu has been doing

Re: [PATCH] target/riscv/kvm.c: fix mvendorid size in vcpu_set_machine_ids()

On 8/10/23 14:01, Alistair Francis wrote: On Wed, Aug 9, 2023 at 6:17 PM Daniel Henrique Barboza wrote: Drew, On 8/3/23 09:05, Andrew Jones wrote: On Thu, Aug 03, 2023 at 08:36:57AM -0300, Daniel Henrique Barboza wrote: On 8/3/23 06:29, Andrew Jones wrote: On Wed, Aug 02, 2023 at 03:0

Re: [PATCH] disas/riscv: Further correction to LUI disassembly

On Fri, Aug 11, 2023 at 10:25:52AM +0200, Andrew Jones wrote: > On Thu, Aug 10, 2023 at 06:27:50PM +0200, Andrew Jones wrote: > > On Thu, Aug 10, 2023 at 09:12:42AM -0700, Palmer Dabbelt wrote: > > > On Thu, 10 Aug 2023 08:31:46 PDT (-0700), ajo...@ventanamicro.com wrote: > > > > On Mon, Jul 31, 20

Re: [PATCH 21/24] tcg/i386: Use CMP+SBB in tcg_out_setcond

On Tue, 8 Aug 2023 at 04:16, Richard Henderson wrote: > > Use the carry bit to optimize some forms of setcond. > > Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell thanks -- PMM

Re: [PATCH 22/24] tcg/i386: Clear dest first in tcg_out_setcond if possible

On Tue, 8 Aug 2023 at 04:16, Richard Henderson wrote: > > Using XOR first is both smaller and more efficient, > though cannot be applied if it clobbers an input. > > Signed-off-by: Richard Henderson > --- Reviewed-by: Peter Maydell thanks -- PMM

Re: [PATCH 23/24] tcg/i386: Use shift in tcg_out_setcond

On Tue, 8 Aug 2023 at 04:13, Richard Henderson wrote: > > For LT/GE vs zero, shift down the sign bit. > > Signed-off-by: Richard Henderson > --- Reviewed-by: Peter Maydell thanks -- PMM

Re: [PATCH 24/24] tcg/i386: Implement negsetcond_*

On Tue, 8 Aug 2023 at 04:15, Richard Henderson wrote: > > Signed-off-by: Richard Henderson > --- > tcg/i386/tcg-target.h | 4 ++-- > tcg/i386/tcg-target.c.inc | 27 +++ > 2 files changed, 21 insertions(+), 10 deletions(-) > Reviewed-by: Peter Maydell thanks -- PMM

Re: [PATCH 16/24] tcg/sparc64: Implement negsetcond_*

On Tue, 8 Aug 2023 at 04:14, Richard Henderson wrote: > > Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell thanks -- PMM

Re: [PATCH] virtio: don't zero out memory region cache for indirect descriptors

On 8/9/23 04:37, Jason Wang wrote: > On Tue, Aug 8, 2023 at 6:28 AM Ilya Maximets wrote: >> >> Lots of virtio functions that are on a hot path in data transmission >> are initializing indirect descriptor cache at the point of stack >> allocation. It's a 112 byte structure that is getting zeroed o

Re: [PATCH] virtio: don't zero out memory region cache for indirect descriptors

On 8/10/23 17:50, Stefan Hajnoczi wrote: > On Tue, Aug 08, 2023 at 12:28:47AM +0200, Ilya Maximets wrote: >> Lots of virtio functions that are on a hot path in data transmission >> are initializing indirect descriptor cache at the point of stack >> allocation. It's a 112 byte structure that is get

RFC: guest INTEL GDS mitigation status on patched host

Hi folks on the list: I'm testing the latest Downfall cpu vulnerability mitigation. what I notice is when both host and guest are using patched kernel + microcode eg kernel 5.15.125 + intel-microcode 20230808 on affected server eg Icelake server. The mitigation status inside guest is: Vulnerabi

[PATCH 3/4] target/i386: Format feature_word_info.c.inc

Harmonize the formatting: Use trailing commas, fix indentation and empty line usage, define "cpuid" fields one per line, unwind index- assignment in arrays, and remove comments. The information in the comments is preserved in the xml file. Signed-off-by: Tim Wiederhake --- target/i386/feature_wo

[PATCH 0/4] Generate x86 cpu features

Synchronizing the list of cpu features and models with qemu is a recurring task in libvirt. For x86, this is done by reading qom-list-properties for max-x86_64-cpu and manually filtering out everthing that does not look like a feature name, as well as parsing target/i386/cpu.c for cpu models. This

[PATCH 1/4] target/i386: Split out feature_word_info

The isolated part will be generated by a script. Signed-off-by: Tim Wiederhake --- target/i386/cpu.c | 677 +--- target/i386/feature_word_info.c.inc | 676 +++ 2 files changed, 677 insertions(+), 676 deletions(-) create mode 1006

[PATCH 4/4] target/i386: Autogenerate feature_word_info.c.inc

This introduces no semantic changes to the file. Signed-off-by: Tim Wiederhake --- target/i386/feature_word_info.c.inc | 2 + target/i386/feature_word_info.py| 110 target/i386/feature_word_info.xml | 3 + 3 files changed, 115 insertions(+) create mode 100

[PATCH 2/4] target/i386: Translate feature_word_info to xml

This is the data file that will be used to generate the C code. All information, including the comments, is preserved. Signed-off-by: Tim Wiederhake --- target/i386/feature_word_info.xml | 1607 + 1 file changed, 1607 insertions(+) create mode 100644 target/i386/feat

Re: CXL volatile memory is not listed

On Fri, 11 Aug 2023 08:04:26 +0530 Maverickk 78 wrote: > Jonathan, > > > More generally for the flow that would bring the memory up as system ram > > you would typically need the bios to have done the CXL enumeration or > > a bunch of scripts in the kernel to have done it. In general it can't >

Re: [PATCH] virtio: don't zero out memory region cache for indirect descriptors

On Fri, Aug 11, 2023, 08:50 Ilya Maximets wrote: > On 8/10/23 17:50, Stefan Hajnoczi wrote: > > On Tue, Aug 08, 2023 at 12:28:47AM +0200, Ilya Maximets wrote: > >> Lots of virtio functions that are on a hot path in data transmission > >> are initializing indirect descriptor cache at the point of

Re: [PATCH] hw/pci-host: Allow extended config space access for Designware PCIe host

On Fri, 11 Aug 2023 at 10:55, Peter Maydell wrote: > > On Thu, 10 Aug 2023 at 18:51, Michael S. Tsirkin wrote: > > > > On Wed, Aug 09, 2023 at 10:22:50AM +, Jason Chien wrote: > > > In pcie_bus_realize(), a root bus is realized as a PCIe bus and a non-root > > > bus is realized as a PCIe bus

Re: [PATCH 1/3] linux-user: Fix the build on systems without SOL_ALG

On 10/8/23 23:51, Ilya Leoshkevich wrote: Building QEMU on CentOS 7 fails, because there SOL_ALG is not defined. There already exists #if defined(SOL_ALG) in do_setsockopt(); add it to target_to_host_cmsg() as well. Does including "crypto/afalgpriv.h" help? Fixes: 27404b6c15c1 ("linux-user: I

Re: [PATCH v2] linux-user/riscv: Use abi type for target_ucontext

On 11/8/23 07:54, LIU Zhiwei wrote: We should not use types dependend on host arch for target_ucontext. This bug is found when run rv32 applications. Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson Reviewed-by: Daniel Henrique Barboza --- v2: - Use abi_ptr instead of abi_ulong for uc

Re: [PATCH] virtio: don't zero out memory region cache for indirect descriptors

On 8/11/23 15:58, Stefan Hajnoczi wrote: > > > On Fri, Aug 11, 2023, 08:50 Ilya Maximets > wrote: > > On 8/10/23 17:50, Stefan Hajnoczi wrote: > > On Tue, Aug 08, 2023 at 12:28:47AM +0200, Ilya Maximets wrote: > >> Lots of virtio functions that are on a ho

Re: Re: Re: [PATCH v1 1/3] softmmu/physmem: fallback to opening guest RAM file as readonly in a MAP_PRIVATE mapping

On Fri, Aug 11, 2023 at 01:49:52PM +0800, ThinerLogoer wrote: > At 2023-08-11 05:24:43, "Peter Xu" wrote: > >On Fri, Aug 11, 2023 at 01:06:12AM +0800, ThinerLogoer wrote: > >> >I think we have the following options (there might be more) > >> > > >> >1) This patch. > >> > > >> >2) New flag for memo

[PATCH v2] virtio: don't zero out memory region cache for indirect descriptors

Lots of virtio functions that are on a hot path in data transmission are initializing indirect descriptor cache at the point of stack allocation. It's a 112 byte structure that is getting zeroed out on each call adding unnecessary overhead. It's going to be correctly initialized later via special

Re: [PATCH v2] linux-user/riscv: Use abi type for target_ucontext

On Fri, Aug 11, 2023 at 1:57 AM LIU Zhiwei wrote: > > We should not use types dependend on host arch for target_ucontext. > This bug is found when run rv32 applications. > > Signed-off-by: LIU Zhiwei > Reviewed-by: Richard Henderson > Reviewed-by: Daniel Henrique Barboza Thanks! Applied to ri

Re: [PATCH v7 0/5] Add RISC-V KVM AIA Support

On Thu, Jul 27, 2023 at 7:49 AM Yong-Xuan Wang wrote: > > This series adds support for KVM AIA in RISC-V architecture. > > In order to test these patches, we require Linux with KVM AIA support which > can > be found in the riscv_kvm_aia_hwaccel_v1 branch at > https://github.com/avpatel/linux.git

Re: [PATCH] hw/riscv: virt: Fix riscv,pmu DT node path

On Thu, Jul 27, 2023 at 10:37 AM Conor Dooley wrote: > > From: Conor Dooley > > On a dtb dumped from the virt machine, dt-validate complains: > soc: pmu: {'riscv,event-to-mhpmcounters': [[1, 1, 524281], [2, 2, 524284], > [65561, 65561, 524280], [65563, 65563, 524280], [65569, 65569, 524280]], >

[RFC PATCH 0/2] Vhost-vdpa Shadow Virtqueue Hash calculation Support

This series enables shadowed CVQ to intercept VIRTIO_NET_CTRL_MQ_HASH_CONFIG command through shadowed CVQ, update the virtio NIC device model so qemu send it in a migration, and the restore of that Hash calculation state in the destination. Note that this patch should be based on patch "vdpa: Send

Re: [PATCH 3/8] target/riscv/cpu.c: introduce cpu_cfg_ext_auto_update()

On Fri, Jul 28, 2023 at 9:22 AM Daniel Henrique Barboza wrote: > > During realize() time we're activating a lot of extensions based on some > criteria, e.g.: > > if (cpu->cfg.ext_zk) { > cpu->cfg.ext_zkn = true; > cpu->cfg.ext_zkr = true; > cpu->cfg.ext_zkt = true; >

[RFC PATCH 1/2] vdpa: Restore hash calculation state

This patch introduces vhost_vdpa_net_load_rss() to restore the hash calculation state at device's startup. Note that vhost_vdpa_net_load_rss() has `do_rss` argument, which allows future code to reuse this function to restore the receive-side scaling state when the VIRTIO_NET_F_RSS feature is enabl

Re: [PATCH 4/8] target/riscv/cpu.c: use cpu_cfg_ext_auto_update() during realize()

On Fri, Jul 28, 2023 at 10:08 AM Daniel Henrique Barboza wrote: > > Let's change the other instances in realize() where we're enabling an > extension based on a certain criteria (e.g. it's a dependency of another > extension). > > We're leaving icsr and ifencei being enabled during RVG for later -

Re: [PATCH] hw/riscv: virt: Fix riscv,pmu DT node path

On Thu, Jul 27, 2023 at 10:37 AM Conor Dooley wrote: > > From: Conor Dooley > > On a dtb dumped from the virt machine, dt-validate complains: > soc: pmu: {'riscv,event-to-mhpmcounters': [[1, 1, 524281], [2, 2, 524284], > [65561, 65561, 524280], [65563, 65563, 524280], [65569, 65569, 524280]], >

pci: Fix the update of interrupt disable bit in PCI_COMMAND register

The PCI_COMMAND register is located at offset 4 within the PCI configuration space and occupies 2 bytes. The interrupt disable bit is at the 10th bit, which corresponds to the byte at offset 5 in the PCI configuration space. In our testing environment, the guest driver may directly updates the by

[RFC PATCH 2/2] vdpa: Allow VIRTIO_NET_F_HASH_REPORT in SVQ

Enable SVQ with VIRTIO_NET_F_HASH_REPORT feature. Signed-off-by: Hawkins Jiawei --- net/vhost-vdpa.c | 1 + 1 file changed, 1 insertion(+) diff --git a/net/vhost-vdpa.c b/net/vhost-vdpa.c index bd51020771..a13b267250 100644 --- a/net/vhost-vdpa.c +++ b/net/vhost-vdpa.c @@ -118,6 +118,7 @@ stati

Re: [PATCH v1 1/3] softmmu/physmem: fallback to opening guest RAM file as readonly in a MAP_PRIVATE mapping

On 10.08.23 23:24, Peter Xu wrote: On Fri, Aug 11, 2023 at 01:06:12AM +0800, ThinerLogoer wrote: I think we have the following options (there might be more) 1) This patch. 2) New flag for memory-backend-file. We already have "readonly" and "share=". I'm having a hard time coming up with a good

Re: [PATCH 5/8] target/riscv/cpu.c: introduce RISCVCPUMultiExtConfig

On Fri, Jul 28, 2023 at 10:06 AM Daniel Henrique Barboza wrote: > > If we want to make better decisions when auto-enabling extensions during > realize() we need a way to tell if an user set an extension manually. > The RISC-V KVM driver has its own solution via a KVMCPUConfig struct > that has an

Re: [PATCH 6/8] target/riscv: use isa_ext_update_enabled() in init_max_cpu_extensions()

On Fri, Jul 28, 2023 at 9:51 AM Daniel Henrique Barboza wrote: > > Before adding support to detect if an extension was user set we need to > handle how we're enabling extensions in riscv_init_max_cpu_extensions(). > object_property_set_bool() calls the set() callback for the property, > and we're

Re: [PATCH 7/8] target/riscv/cpu.c: honor user choice in cpu_cfg_ext_auto_update()

On Fri, Jul 28, 2023 at 10:32 AM Daniel Henrique Barboza wrote: > > Add a new cpu_cfg_ext_is_user_set() helper to check if an extension was > set by the user in the command line. Use it inside > cpu_cfg_ext_auto_update() to verify if the user set a certain extension > and, if that's the case, do n

Re: [PATCH 8/8] target/riscv/cpu.c: consider user option with RVG

On Fri, Jul 28, 2023 at 9:39 AM Daniel Henrique Barboza wrote: > > Enabling RVG will enable a set of extensions that we're not checking if > the user was okay enabling or not. And in this case we want to error > out, instead of ignoring, otherwise we will be inconsistent enabling RVG > without all

Re: [PATCH 20/24] tcg/i386: Add cf parameter to tcg_out_cmp

On 8/11/23 03:45, Peter Maydell wrote: On Fri, 11 Aug 2023 at 11:26, Peter Maydell wrote: On Tue, 8 Aug 2023 at 04:13, Richard Henderson wrote: Add the parameter to avoid TEST and pass along to tgen_arithi. All current users pass false. Signed-off-by: Richard Henderson --- tcg/i386/tcg-

[PATCH v3 06/10] migration: Consolidate return path closing code

We'll start calling the await_return_path_close_on_source() function from other parts of the code, so move all of the related checks and tracepoints into it. Signed-off-by: Fabiano Rosas --- migration/migration.c | 29 ++--- 1 file changed, 14 insertions(+), 15 deletions(

[PATCH v3 07/10] migration: Replace the return path retry logic

Replace the return path retry logic with finishing and restarting the thread. This fixes a race when resuming the migration that leads to a segfault. Currently when doing postcopy we consider that an IO error on the return path file could be due to a network intermittency. We then keep the thread

[PATCH v3 01/10] migration: Fix possible race when setting rp_state.error

We don't need to set the rp_state.error right after a shutdown because qemu_file_shutdown() always sets the QEMUFile error, so the return path thread would have seen it and set the rp error itself. Setting the error outside of the thread is also racy because the thread could clear it after we set

[PATCH v3 00/10] Fix segfault on migration return path

I decided to fix the issues with the shutdown instead of complaining about them. First 5 patches address all of the possible races I found. The only problem left to figure out is the -EIO on shutdown which will need more thought. Patches 6 & 7 fix the original segfault. Patches 8-10 make the clea

[PATCH v3 04/10] migration: Fix possible race when shutting down to_dst_file

It's not safe to call qemu_file_shutdown() on the to_dst_file without first checking for the file's presence under the lock. The cleanup of this file happens at postcopy_pause() and migrate_fd_cleanup() which are not necessarily running in the same thread as migrate_fd_cancel(). Signed-off-by: Fab

[PATCH v3 02/10] migration: Fix possible race when shutting return path

We cannot call qemu_file_shutdown() on the return path file without taking the file lock. The return path thread could be running it's cleanup code and have just cleared the pointer. This was caught by inspection, it should be rare, but the next patches will start calling this code from other plac

[PATCH v3 03/10] migration: Fix possible race when checking to_dst_file for errors

Checking ms->to_dst_file for errors when cleaning up the return path could race with migrate_fd_cleanup() which clears the pointer. Since migrate_fd_cleanup() is reachable via qmp_migrate(), which is issued by the user, it is safer if we take the lock when reading ms->to_dst_file. Signed-off-by:

[PATCH v3 05/10] migration: Remove redundant cleanup of postcopy_qemufile_src

This file is owned by the return path thread which is already doing cleanup. Signed-off-by: Fabiano Rosas --- migration/migration.c | 6 -- 1 file changed, 6 deletions(-) diff --git a/migration/migration.c b/migration/migration.c index 5e6a766235..195726eb4a 100644 --- a/migration/migration

[PATCH v3 08/10] migration: Move return path cleanup to main migration thread

Now that the return path thread is allowed to finish during a paused migration, we can move the cleanup of the QEMUFiles to the main migration thread. Signed-off-by: Fabiano Rosas --- migration/migration.c | 11 ++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/migration/

[PATCH v3 09/10] migration: Be consistent about shutdown of source shared files

When doing cleanup, we currently close() some of the shared migration files and shutdown() + close() others. Be consistent by always calling shutdown() before close(). Do this only for the source files for now because the source runs multiple threads which could cause races between the two calls.

[PATCH v3 10/10] migration: Add a wrapper to cleanup migration files

We currently have a pattern for cleaning up a migration QEMUFile: qemu_mutex_lock(&s->qemu_file_lock); file = s->file_name; s->file_name = NULL; qemu_mutex_unlock(&s->qemu_file_lock); migration_ioc_unregister_yank_from_file(file); qemu_file_shutdown(file); qemu_fclose(file); There

Re: [PATCH v5 08/11] target/loongarch: Reject la64-only instructions in la32 mode

On 8/11/23 01:12, gaosong wrote: +TRANS_64(sra_d, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, gen_sra_d)   TRANS(rotr_w, gen_rrr, EXT_ZERO, EXT_NONE, EXT_SIGN, gen_rotr_w) TRANS_64(rotr_w, ...) ...   TRANS(rotri_w, gen_rri_v, EXT_NONE, EXT_NONE, gen_rotr_w) TRANS_64(rotri_w, ...) I see the manual

Re: [PATCH v2 2/8] target/loongarch: Add a check parameter to the TRANS macro

On 8/11/23 03:02, Song Gao wrote: The default check parmeter is ALL, remove TRANS_64 marco. Suggested-by: Richard Henderson Signed-off-by: Song Gao If you're going to remove TRANS_64, you should simply drop the patch that added it, and be careful about the final patch ordering such that the

Re: [PATCH v1 1/3] softmmu/physmem: fallback to opening guest RAM file as readonly in a MAP_PRIVATE mapping

On 11.08.23 16:59, David Hildenbrand wrote: On 10.08.23 23:24, Peter Xu wrote: On Fri, Aug 11, 2023 at 01:06:12AM +0800, ThinerLogoer wrote: I think we have the following options (there might be more) 1) This patch. 2) New flag for memory-backend-file. We already have "readonly" and "share=".

[RFC PATCH 1/3] vdpa: Add SetSteeringEBPF method for NetClientState

At present, to enable the VIRTIO_NET_F_RSS feature, eBPF must be loaded for the vhost backend. Given that vhost-vdpa is one of the vhost backend, we need to implement the SetSteeringEBPF method to support RSS for vhost-vdpa, even if vhost-vdpa calculates the rss hash in the hardware device instead

[RFC PATCH 2/3] vdpa: Restore receive-side scaling state

This patch reuses vhost_vdpa_net_load_rss() with some refactorings to restore the receive-side scaling state at device's startup. Signed-off-by: Hawkins Jiawei --- net/vhost-vdpa.c | 53 1 file changed, 35 insertions(+), 18 deletions(-) diff --gi

[RFC PATCH 0/3] Vhost-vdpa Shadow Virtqueue RSS Support

This series enables shadowed CVQ to intercept RSS command through shadowed CVQ, update the virtio NIC device model so qemu send it in a migration, and the restore of that RSS state in the destination. Note that this patch should be based on patch "Vhost-vdpa Shadow Virtqueue Hash calculation Suppo

[RFC PATCH 3/3] vdpa: Allow VIRTIO_NET_F_RSS in SVQ

Enable SVQ with VIRTIO_NET_F_RSS feature. Signed-off-by: Hawkins Jiawei --- net/vhost-vdpa.c | 1 + 1 file changed, 1 insertion(+) diff --git a/net/vhost-vdpa.c b/net/vhost-vdpa.c index 7870cbe142..eb08530396 100644 --- a/net/vhost-vdpa.c +++ b/net/vhost-vdpa.c @@ -119,6 +119,7 @@ static const

Re: [PATCH v1 1/3] softmmu/physmem: fallback to opening guest RAM file as readonly in a MAP_PRIVATE mapping

On Fri, Aug 11, 2023 at 04:59:56PM +0200, David Hildenbrand wrote: > On 10.08.23 23:24, Peter Xu wrote: > > On Fri, Aug 11, 2023 at 01:06:12AM +0800, ThinerLogoer wrote: > > > > I think we have the following options (there might be more) > > > > > > > > 1) This patch. > > > > > > > > 2) New flag

Re: [PATCH v2 3/8] target/loongarch: Add avail_64 to check la64-only instructions

On 8/11/23 03:02, Song Gao wrote: The la32 manual from [1], and it is not the final version. [1]: https://www.loongson.cn/uploads/images/2023041918122813624.%E9%BE%99%E8%8A%AF%E6%9E%B6%E6%9E%8432%E4%BD%8D%E7%B2%BE%E7%AE%80%E7%89%88%E5%8F%82%E8%80%83%E6%89%8B%E5%86%8C_r1p03.pdf I really hope t

[PATCH for-8.1 1/1] hw/riscv/virt.c: change 'aclint' TCG check

The 'aclint' property is being conditioned with tcg acceleration in virt_machine_class_init(). But acceleration code starts later than the class init of the board, meaning that tcg_enabled() will be always be false during class_init(), and the option is never being declared even when declaring TCG

[PATCH for-8.1 0/1] hw/riscv/virt.c: fix 'aclint' prop regression

Richard, Alistair, I came across this gitlab bug earlier today. The bug itself was opened yesterday: https://gitlab.com/qemu-project/qemu/-/issues/1823 And turns out that this is a regression in the 'aclint' option that was introduced in 8.1. I'm aware that we're already in rc3 and kind of late

Re: [RFC v1 0/3] Initial support for SPDM

On Thu, Aug 10, 2023 at 6:18 AM Jonathan Cameron wrote: > > On Wed, 9 Aug 2023 12:45:35 -0400 > Alistair Francis wrote: > > > On Wed, Aug 9, 2023 at 8:11 AM Jonathan Cameron > > wrote: > > > > > > On Tue, 8 Aug 2023 11:51:21 -0400 > > > Alistair Francis wrote: > > > > > > > The Security Protoc

Re: [PATCH v2 4/8] target/loongarch: Add avail_FP/FP_SP/FP_DP to check fpu instructions

On 8/11/23 03:02, Song Gao wrote: Signed-off-by: Song Gao --- .../loongarch/insn_trans/trans_farith.c.inc | 96 --- target/loongarch/insn_trans/trans_fcmp.c.inc | 8 ++ target/loongarch/insn_trans/trans_fcnv.c.inc | 56 +-- .../loongarch/insn_trans/trans_fmemory.

Re: [PATCH v2 5/8] target/loongarch: Add avail_LSPW to check LSPW instructions

On 8/11/23 03:02, Song Gao wrote: Signed-off-by: Song Gao --- target/loongarch/insn_trans/trans_privileged.c.inc | 8 target/loongarch/translate.h | 1 + 2 files changed, 9 insertions(+) Reviewed-by: Richard Henderson r~

Re: pci: Fix the update of interrupt disable bit in PCI_COMMAND register

On Fri, Aug 11, 2023 at 10:46:51PM +0800, Guoyi Tu wrote: > The PCI_COMMAND register is located at offset 4 within > the PCI configuration space and occupies 2 bytes. The > interrupt disable bit is at the 10th bit, which corresponds > to the byte at offset 5 in the PCI configuration space. > > In

Re: [PATCH v2 6/8] target/loongarch: Add avail_LAM to check atomic instructions

On 8/11/23 03:02, Song Gao wrote: Signed-off-by: Song Gao --- target/loongarch/insn_trans/trans_atomic.c.inc | 12 target/loongarch/translate.h | 1 + 2 files changed, 13 insertions(+) diff --git a/target/loongarch/insn_trans/trans_atomic.c.inc b/target/loon

Re: [PATCH v2 7/8] target/loongarch: Add avail_LSX to check LSX instructions

On 8/11/23 03:02, Song Gao wrote: Signed-off-by: Song Gao --- target/loongarch/insn_trans/trans_lsx.c.inc | 1482 ++- target/loongarch/translate.h|2 + 2 files changed, 823 insertions(+), 661 deletions(-) Reviewed-by: Richard Henderson r~

Re: [PATCH v1 1/3] softmmu/physmem: fallback to opening guest RAM file as readonly in a MAP_PRIVATE mapping

On Fri, Aug 11, 2023 at 05:26:24PM +0200, David Hildenbrand wrote: > I just started looking into the origins of "-mem-path". > > Originally c902760fb2 ("Add option to use file backed guest memory"): > > * Without MAP_POPULATE support, we use MAP_PRIVATE > * With MAP_POPULATE support we use MAP_PR

Re: [PATCH v1 1/3] softmmu/physmem: fallback to opening guest RAM file as readonly in a MAP_PRIVATE mapping

On 11.08.23 18:16, Peter Xu wrote: On Fri, Aug 11, 2023 at 05:26:24PM +0200, David Hildenbrand wrote: I just started looking into the origins of "-mem-path". Originally c902760fb2 ("Add option to use file backed guest memory"): * Without MAP_POPULATE support, we use MAP_PRIVATE * With MAP_POPU

Re: [PATCH v2 8/8] target/loongarch: Add avail_IOCSR to check iocsr instructions

On 8/11/23 03:02, Song Gao wrote: Signed-off-by: Song Gao --- .../loongarch/insn_trans/trans_privileged.c.inc | 16 target/loongarch/translate.h | 2 +- 2 files changed, 9 insertions(+), 9 deletions(-) Reviewed-by: Richard Henderson r~

[PULL 0/2] pci: last minute bugfixes

The following changes since commit 15b11a1da6a4b7c6b8bb37883f52b544dee2b8fd: cryptodev: Handle unexpected request to avoid crash (2023-08-03 16:16:17 -0400) are available in the Git repository at: https://git.kernel.org/pub/scm/virt/kvm/mst/qemu.git tags/for_upstream for you to fetch chang

[PULL 1/2] hw/pci-host: Allow extended config space access for Designware PCIe host

From: Jason Chien In pcie_bus_realize(), a root bus is realized as a PCIe bus and a non-root bus is realized as a PCIe bus if its parent bus is a PCIe bus. However, the child bus "dw-pcie" is realized before the parent bus "pcie" which is the root PCIe bus. Thus, the extended configuration space

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