Re: [PATCH 03/24] target/alpha: Use tcg_gen_movcond_i64 in gen_fold_mzero

On Tue, 8 Aug 2023 at 04:14, Richard Henderson wrote: > > The setcond + neg + and sequence is a complex method of > performing a conditional move. > > Signed-off-by: Richard Henderson > --- > target/alpha/translate.c | 7 +++ > 1 file changed, 3 insertions(+), 4 deletions(-) > > diff --git a

Re: [PATCH 04/24] target/arm: Use tcg_gen_negsetcond_*

On Tue, 8 Aug 2023 at 04:15, Richard Henderson wrote: > > Signed-off-by: Richard Henderson > --- > target/arm/tcg/translate-a64.c | 22 +- > target/arm/tcg/translate.c | 12 > 2 files changed, 13 insertions(+), 21 deletions(-) > > diff --git a/target/arm/tcg/

Re: [PATCH 05/24] target/m68k: Use tcg_gen_negsetcond_*

On Tue, 8 Aug 2023 at 04:17, Richard Henderson wrote: > > Signed-off-by: Richard Henderson > --- > target/m68k/translate.c | 24 ++-- > 1 file changed, 10 insertions(+), 14 deletions(-) > Reviewed-by: Peter Maydell thanks -- PMM

Re: [PATCH 06/24] target/openrisc: Use tcg_gen_negsetcond_*

On Tue, 8 Aug 2023 at 04:13, Richard Henderson wrote: > > Signed-off-by: Richard Henderson > --- > target/openrisc/translate.c | 6 ++ > 1 file changed, 2 insertions(+), 4 deletions(-) Reviewed-by: Peter Maydell thanks -- PMM

Re: [PATCH 7/8] gdbstub: more fixes for client Ctrl-C handling

On 8/10/23 08:36, Alex Bennée wrote: The original fix caused problems with spurious characters on other system emulation. So: - instead of spamming output make the warning a trace point - ensure we only allow a stop reply if it was 0x3 Suggested-by: Matheus Tavares Bernardino Signed-off-b

Re: [PATCH] disas/riscv: Further correction to LUI disassembly

On Thu, Aug 10, 2023 at 09:12:42AM -0700, Palmer Dabbelt wrote: > On Thu, 10 Aug 2023 08:31:46 PDT (-0700), ajo...@ventanamicro.com wrote: > > On Mon, Jul 31, 2023 at 11:33:20AM -0700, Richard Bagley wrote: > > > The recent commit 36df75a0a9 corrected one aspect of LUI disassembly > > > by recoveri

Re: [PATCH 08/24] target/sparc: Use tcg_gen_movcond_i64 in gen_edge

On Tue, 8 Aug 2023 at 04:14, Richard Henderson wrote: > > The setcond + neg + or sequence is a complex method of > performing a conditional move. > > Signed-off-by: Richard Henderson > --- > target/sparc/translate.c | 17 - > 1 file changed, 4 insertions(+), 13 deletions(-) > > d

Re: [PATCH 0/8] some testing and gdbstub fixes

On 8/10/23 08:58, Peter Maydell wrote: On Thu, 10 Aug 2023 at 16:36, Alex Bennée wrote: This is mostly gdbstub focused but I cleaned up some bits while I was in the testing makefiles. This is mostly to make the "check-tcg" output as clean as possible without ugly line wraps. I tried to elimina

Re: [PATCH 0/8] some testing and gdbstub fixes

Peter Maydell writes: > On Thu, 10 Aug 2023 at 16:36, Alex Bennée wrote: >> >> This is mostly gdbstub focused but I cleaned up some bits while I was >> in the testing makefiles. This is mostly to make the "check-tcg" >> output as clean as possible without ugly line wraps. I tried to >> elimina

Re:Re: [PATCH v1 0/3] softmmu/physmem: file_ram_open() readonly improvements

At 2023-08-10 19:11:03, "Philippe Mathieu-Daudé" wrote: >Hi, > >On 8/8/23 19:26, ThinerLogoer wrote: >> >> At 2023-08-08 03:07:31, "David Hildenbrand" wrote: > >>> Instead of handling it inside file_ram_open(), handle it in the caller >>> and only fallback to readonly in a MAP_PRIVATE mapping. >

Re: [PATCH 12/24] tcg/aarch64: Implement negsetcond_*

On Tue, 8 Aug 2023 at 04:13, Richard Henderson wrote: > > Trivial, as aarch64 has an instruction for this: CSETM. > > Signed-off-by: Richard Henderson > --- > tcg/aarch64/tcg-target.h | 4 ++-- > tcg/aarch64/tcg-target.c.inc | 12 > 2 files changed, 14 insertions(+), 2 deletion

Re: [PATCH 01/24] tcg: Introduce negsetcond opcodes

On 8/10/23 09:12, Peter Maydell wrote: +ctx->s_mask = -1; Do we not also need to set z_mask to something here (presumably -1)? (I'm not very familiar with the optimizer internals.) It is set to -1 by default before folding all operations. r~

Re: [PATCH-for-8.2] target/arm/cpu: Allow logging disabled CPU features at UNIMP level

Philippe Mathieu-Daudé writes: > Some CPU features aren't strictly required to run guest code (such > debugging features), so we don't model them. To prevent the guest > to access non-existent system registers, we disable the feature bit > in the ID registers (see commit 7d8c283e10 "target/arm:

Re: [PATCH 13/24] tcg/arm: Implement negsetcond_i32

On Tue, 8 Aug 2023 at 04:14, Richard Henderson wrote: > > Trivial, as we simply need to load a different constant > in the conditional move. > > Signed-off-by: Richard Henderson > --- > tcg/arm/tcg-target.h | 2 +- > tcg/arm/tcg-target.c.inc | 9 + > 2 files changed, 10 insertions(+)

Re: [PATCH 0/8] some testing and gdbstub fixes

On 8/10/23 09:35, Alex Bennée wrote: So 7 and 8? I would argue for 6 as well given that's a foot gun just waiting to happen. Yes, the timing issues with 6 are nasty. r~

Re: [PATCH-for-8.2] target/arm/cpu: Allow logging disabled CPU features at UNIMP level

On Thu, 10 Aug 2023 at 17:13, Philippe Mathieu-Daudé wrote: > > Some CPU features aren't strictly required to run guest code (such > debugging features), so we don't model them. To prevent the guest > to access non-existent system registers, we disable the feature bit > in the ID registers (see co

Re: [PATCH 12/24] tcg/aarch64: Implement negsetcond_*

On 8/10/23 09:39, Peter Maydell wrote: +case INDEX_op_negsetcond_i32: +a2 = (int32_t)a2; +/* FALLTHRU */ I see this is what we already do for setcond and movcond, but how does it work when the 2nd input is a register? Or is reg-reg guaranteed to always use the _i64 op? For

Re: [PATCH] target/riscv/kvm.c: fix mvendorid size in vcpu_set_machine_ids()

On Wed, Aug 2, 2023 at 2:02 PM Daniel Henrique Barboza wrote: > > cpu->cfg.mvendorid is a 32 bit field and kvm_set_one_reg() always write > a target_ulong val, i.e. a 64 bit field in a 64 bit host. > > Given that we're passing a pointer to the mvendorid field, the reg is > reading 64 bits starting

Re: [PATCH 12/24] tcg/aarch64: Implement negsetcond_*

On Thu, 10 Aug 2023 at 17:55, Richard Henderson wrote: > > On 8/10/23 09:39, Peter Maydell wrote: > >> +case INDEX_op_negsetcond_i32: > >> +a2 = (int32_t)a2; > >> +/* FALLTHRU */ > > > > I see this is what we already do for setcond and movcond, > > but how does it work when the

Re: [PATCH] target/riscv/kvm.c: fix mvendorid size in vcpu_set_machine_ids()

On Wed, Aug 2, 2023 at 2:02 PM Daniel Henrique Barboza wrote: > > cpu->cfg.mvendorid is a 32 bit field and kvm_set_one_reg() always write > a target_ulong val, i.e. a 64 bit field in a 64 bit host. > > Given that we're passing a pointer to the mvendorid field, the reg is > reading 64 bits starting

Re: [PATCH] target/riscv/kvm.c: fix mvendorid size in vcpu_set_machine_ids()

On Wed, Aug 9, 2023 at 6:17 PM Daniel Henrique Barboza wrote: > > Drew, > > On 8/3/23 09:05, Andrew Jones wrote: > > On Thu, Aug 03, 2023 at 08:36:57AM -0300, Daniel Henrique Barboza wrote: > >> > >> > >> On 8/3/23 06:29, Andrew Jones wrote: > >>> On Wed, Aug 02, 2023 at 03:00:58PM -0300, Daniel H

Re: CXL volatile memory is not listed

On Wed, Aug 09, 2023 at 04:21:47AM +0530, Maverickk 78 wrote: > Hello, > > I am running qemu-system-x86_64 > > qemu-system-x86_64 --version > QEMU emulator version 8.0.92 (v8.1.0-rc2-80-g0450cf0897) > > qemu-system-x86_64 \ > -m 2G,slots=4,maxmem=4G \ > -smp 4 \ > -machine type=q35,accel=kvm,cxl=on

Re: [PATCH 12/24] tcg/aarch64: Implement negsetcond_*

On 8/10/23 09:58, Peter Maydell wrote: On Thu, 10 Aug 2023 at 17:55, Richard Henderson wrote: On 8/10/23 09:39, Peter Maydell wrote: +case INDEX_op_negsetcond_i32: +a2 = (int32_t)a2; +/* FALLTHRU */ I see this is what we already do for setcond and movcond, but how does i

Re: [PATCH] target/riscv: Implement WARL behaviour for mcountinhibit/mcounteren

On Wed, Aug 2, 2023 at 8:50 AM Rob Bradford wrote: > > These are WARL fields - zero out the bits for unavailable counters and > special case the TM bit in mcountinhibit which is hardwired to zero. > This patch achieves this by modifying the value written so that any use > of the field will see the

Re: [PATCH 5/5] target/arm: Implement cortex-a710

On 8/10/23 08:49, Peter Maydell wrote: On Thu, 10 Aug 2023 at 03:36, Richard Henderson wrote: The cortex-a710 is a first generation ARMv9.0-A processor. Signed-off-by: Richard Henderson --- docs/system/arm/virt.rst | 1 + hw/arm/virt.c| 1 + target/arm/tcg/cpu64.c | 167

Re:Re: [PATCH v1 1/3] softmmu/physmem: fallback to opening guest RAM file as readonly in a MAP_PRIVATE mapping

At 2023-08-10 22:19:45, "David Hildenbrand" wrote: >>> Most importantly, we won't be corrupting/touching the original file in any >>> case, because it is R/O. >>> >>> If we really want to be careful, we could clue that behavior to compat >>> machines. I'm not really sure yet if we really have to g

Re: [PATCH] target/riscv: Implement WARL behaviour for mcountinhibit/mcounteren

On Wed, Aug 2, 2023 at 8:50 AM Rob Bradford wrote: > > These are WARL fields - zero out the bits for unavailable counters and > special case the TM bit in mcountinhibit which is hardwired to zero. > This patch achieves this by modifying the value written so that any use > of the field will see the

Re: [PATCH 6/8] tests/tcg: ensure system-mode gdb tests start stopped

On 8/10/23 08:36, Alex Bennée wrote: Without -S we run into potential races with tests starting before the gdbstub attaches. We don't need to worry about user-mode as enabling the gdbstub implies we wait for the initial connection. Signed-off-by: Alex Bennée --- tests/guest-debug/run-test.py |

Re: [PATCH 5/8] tests/tcg: clean-up gdb confirm/pagination settings

On 8/10/23 08:36, Alex Bennée wrote: We can do this all in the run-test.py script so remove the extraneous bits from the individual tests which got copied from the original non-CI gdb tests. Signed-off-by: Alex Bennée --- tests/guest-debug/run-test.py | 2 ++ tests/tcg

Re: [PATCH] linux-user/elfload: Set V in ELF_HWCAP for RISC-V

On Tue, Aug 8, 2023 at 2:37 AM Michael Tokarev wrote: > > 03.08.2023 16:14, Nathan Egge wrote: > > From: "Nathan Egge" > > > > Set V bit for hwcap if misa is set. > > > > Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1793 > > Signed-off-by: Nathan Egge > > --- > > linux-user/elfload.

Re: [PATCH 4/8] tests: remove test-gdbstub.py

On 8/10/23 08:36, Alex Bennée wrote: This isn't directly called by our CI and because it doesn't run via our run-test.py script does things slightly differently. Lets remove it as we have plenty of working in-tree tests now for various aspects of gdbstub. Signed-off-by: Alex Bennée --- tests/g

Re: [PATCH 5/5] target/arm: Implement cortex-a710

On Thu, 10 Aug 2023 at 18:05, Richard Henderson wrote: > > On 8/10/23 08:49, Peter Maydell wrote: > > On Thu, 10 Aug 2023 at 03:36, Richard Henderson > > wrote: > >> > >> The cortex-a710 is a first generation ARMv9.0-A processor. > >> > >> Signed-off-by: Richard Henderson > >> --- > >> docs/sy

Re: [PATCH 1/2] riscv: zicond: make non-experimental

On Tue, Aug 8, 2023 at 5:16 PM Palmer Dabbelt wrote: > > On Tue, 08 Aug 2023 14:10:54 PDT (-0700), dbarb...@ventanamicro.com wrote: > > > > > > On 8/8/23 17:52, Palmer Dabbelt wrote: > >> On Tue, 08 Aug 2023 11:45:49 PDT (-0700), Vineet Gupta wrote: > >>> > >>> > >>> On 8/8/23 11:29, Richard Hende

Re: [PATCH 1/2] riscv: zicond: make non-experimental

On Tue, Aug 8, 2023 at 2:18 PM Vineet Gupta wrote: > > zicond is now codegen supported in both llvm and gcc. > > This change allows seamless enabling/testing of zicond in downstream > projects. e.g. currently riscv-gnu-toolchain parses elf attributes > to create a cmdline for qemu but fails short

Re: [RESEND PATCH v3 1/1] target/riscv: Add Zihintntl extension ISA string to DTS

On Wed, Jul 26, 2023 at 3:42 AM Jason Chien wrote: > > RVA23 Profiles states: > The RVA23 profiles are intended to be used for 64-bit application > processors that will run rich OS stacks from standard binary OS > distributions and with a substantial number of third-party binary user > application

Re: [PATCH] hw/pci-host: Allow extended config space access for Designware PCIe host

As far as I know, the order issue is caused by nested device realization. In this case, realizing TYPE_DESIGNWARE_PCIE_HOST will also realize TYPE_DESIGNWARE_PCIE_ROOT(see designware_pcie_host_realize()). device_set_realized() is the function that realizing a device must go through, and this functi

Re: [PATCH] target/riscv: Fix zfa fleq.d and fltq.d

On Thu, Jul 27, 2023 at 8:50 PM LIU Zhiwei wrote: > > Commit a47842d ("riscv: Add support for the Zfa extension") implemented the > zfa extension. > However, it has some typos for fleq.d and fltq.d. Both of them misused the > fltq.s > helper function. > > Signed-off-by: LIU Zhiwei Thanks! App

Re: [PATCH 1/8] target/riscv/cpu.c: use offset in isa_ext_is_enabled/update_enabled

On Fri, Jul 28, 2023 at 9:18 AM Daniel Henrique Barboza wrote: > > We'll have future usage for a function where, given an offset of the > struct RISCVCPUConfig, the flag is updated to a certain val. > > Change all existing callers to use edata->ext_enable_offset instead of > 'edata'. > > Signed-of

Re: [PATCH 2/8] target/riscv: make CPUCFG() macro public

On Fri, Jul 28, 2023 at 9:20 AM Daniel Henrique Barboza wrote: > > The RISC-V KVM driver uses a CPUCFG() macro that calculates the offset > of a certain field in the struct RISCVCPUConfig. We're going to use this > macro in target/riscv/cpu.c as well in the next patches. Make it public. > > Rename

Re: [PATCH 0/8] some testing and gdbstub fixes

On 8/10/23 09:43, Richard Henderson wrote: On 8/10/23 09:35, Alex Bennée wrote: So 7 and 8? I would argue for 6 as well given that's a foot gun just waiting to happen. Yes, the timing issues with 6 are nasty. I'm going to queue 6-8 to tcg-next, along with the %x change Phil suggested for log

[PATCH v5 09/17] nbd/server: Support 64-bit block status

The NBD spec states that if the client negotiates extended headers, the server must avoid NBD_REPLY_TYPE_BLOCK_STATUS and instead use NBD_REPLY_TYPE_BLOCK_STATUS_EXT which supports 64-bit lengths, even if the reply does not need more than 32 bits. As of this patch, client->mode is still never NBD_

[PATCH v5 16/17] nbd/server: Prepare for per-request filtering of BLOCK_STATUS

The next commit will add support for the optional extension NBD_CMD_FLAG_PAYLOAD during NBD_CMD_BLOCK_STATUS, where the client can request that the server only return a subset of negotiated contexts, rather than all contexts. To make that task easier, this patch populates the list of contexts to r

[PATCH v5 00/17] qemu patches for 64-bit NBD extensions

v4 was here: https://lists.gnu.org/archive/html/qemu-devel/2023-06/msg01898.html (1-8/24 of that series made it into 8.1; this is the rest) v5 addresses Vladimir's review comments; and the amount of change is smaller, so this is probably ready to merge in once 8.1 is out the door and the remaining

[PATCH v5 05/17] nbd/server: Refactor handling of command sanity checks

Upcoming additions to support NBD 64-bit effect lengths will add a new command flag NBD_CMD_FLAG_PAYLOAD_LEN that needs to be considered in our sanity checks of the client's messages (that is, more than just CMD_WRITE have the potential to carry a client payload when extended headers are in effect)

[PATCH v5 03/17] nbd: Add types for extended headers

Add the constants and structs necessary for later patches to start implementing the NBD_OPT_EXTENDED_HEADERS extension in both the client and server, matching recent upstream nbd.git (through commit e6f3b94a934). This patch does not change any existing behavior, but merely sets the stage for upcom

[PATCH v5 10/17] nbd/server: Enable initial support for extended headers

Time to start supporting clients that request extended headers. Now we can finally reach the code added across several previous patches. Even though the NBD spec has been altered to allow us to accept NBD_CMD_READ larger than the max payload size (provided our response is a hole or broken up over

[PATCH v5 17/17] nbd/server: Add FLAG_PAYLOAD support to CMD_BLOCK_STATUS

Allow a client to request a subset of negotiated meta contexts. For example, a client may ask to use a single connection to learn about both block status and dirty bitmaps, but where the dirty bitmap queries only need to be performed on a subset of the disk; forcing the server to compute that info

[PATCH v5 15/17] nbd/server: Refactor list of negotiated meta contexts

Peform several minor refactorings of how the list of negotiated meta contexts is managed, to make upcoming patches easier: Promote the internal type NBDExportMetaContexts to the public opaque type NBDMetaContexts, and mark exp const. Use a shorter member name in NBDClient. Hoist calls to nbd_chec

Re: [PATCH v6 03/12] target/riscv/cpu.c: split kvm prop handling to its own helper

On Thu, Jul 27, 2023 at 6:39 PM Daniel Henrique Barboza wrote: > > Future patches will split the existing Property arrays even further, and > the existing code in riscv_cpu_add_user_properties() will start to scale > bad with it because it's dealing with KVM constraints mixed in with TCG > constra

[PATCH v5 01/17] nbd: Replace bool structured_reply with mode enum

The upcoming patches for 64-bit extensions requires various points in the protocol to make decisions based on what was negotiated. While we could easily add a 'bool extended_headers' alongside the existing 'bool structured_reply', this does not scale well if more modes are added in the future. Be

Re: [PATCH] hw/pci-host: Allow extended config space access for Designware PCIe host

On Fri, Aug 11, 2023 at 01:22:08AM +0800, Jason Chien wrote: > As far as I know, the order issue is caused by nested device realization. In > this case, realizing TYPE_DESIGNWARE_PCIE_HOST will also > realize TYPE_DESIGNWARE_PCIE_ROOT(see designware_pcie_host_realize()). > device_set_realized() is

[PATCH v5 02/17] nbd/client: Pass mode through to nbd_send_request

Once the 64-bit headers extension is enabled, the data layout we send over the wire for a client request depends on the mode negotiated with the server. Rather than adding a parameter to nbd_send_request, we can add a member to struct NBDRequest, since it already does not reflect on-wire format.

[PATCH v5 14/17] nbd/client: Request extended headers during negotiation

All the pieces are in place for a client to finally request extended headers. Note that we must not request extended headers when qemu-nbd is used to connect to the kernel module (as nbd.ko does not expect them, but expects us to do the negotiation in userspace before handing the socket over to th

[PATCH v5 13/17] nbd/client: Accept 64-bit block status chunks

Once extended mode is enabled, we need to accept 64-bit status replies (even for replies that don't exceed a 32-bit length). It is easier to normalize narrow replies into wide format so that the rest of our code only has to handle one width. Although a server is non-compliant if it sends a 64-bit

[PATCH v5 06/17] nbd/server: Support a request payload

Upcoming additions to support NBD 64-bit effect lengths allow for the possibility to distinguish between payload length (capped at 32M) and effect length (64 bits, although we generally assume 63 bits because of off_t limitations). Without that extension, only the NBD_CMD_WRITE request has a paylo

[PATCH v5 12/17] nbd/client: Initial support for extended headers

Update the client code to be able to send an extended request, and parse an extended header from the server. Note that since we reject any structured reply with a too-large payload, we can always normalize a valid header back into the compact form, so that the caller need not deal with two branche

[PATCH v5 08/17] nbd/server: Prepare to send extended header replies

Although extended mode is not yet enabled, once we do turn it on, we need to reply with extended headers to all messages. Update the low level entry points necessary so that all other callers automatically get the right header based on the current mode. Signed-off-by: Eric Blake Reviewed-by: Vla

[PATCH v5 04/17] nbd: Prepare for 64-bit request effect lengths

Widen the length field of NBDRequest to 64-bits, although we can assert that all current uses are still under 32 bits: either because of NBD_MAX_BUFFER_SIZE which is even smaller (and where size_t can still be appropriate, even on 32-bit platforms), or because nothing ever puts us into NBD_MODE_EXT

[PATCH v5 11/17] nbd/client: Plumb errp through nbd_receive_replies

Instead of ignoring the low-level error just to refabricate our own message to pass to the caller, we can just plumb the caller's errp down to the low level. Signed-off-by: Eric Blake --- v5: set errp on more failure cases [Vladimir], typo fix v4: new patch [Vladimir] --- block/nbd.c | 18

[PATCH v5 07/17] nbd/server: Prepare to receive extended header requests

Although extended mode is not yet enabled, once we do turn it on, we need to accept extended requests for all messages. Previous patches have already taken care of supporting 64-bit lengths, now we just need to read it off the wire. Note that this implementation will block indefinitely on a buggy

Re: [PATCH] hw/pci-host: Allow extended config space access for Designware PCIe host

the patch link: https://lists.gnu.org/archive/html/qemu-devel/2021-11/msg02162.html On Fri, Aug 11, 2023 at 1:44 AM Michael S. Tsirkin wrote: > On Fri, Aug 11, 2023 at 01:22:08AM +0800, Jason Chien wrote: > > As far as I know,

Re: [PATCH v6 04/12] target/riscv/cpu.c: del DEFINE_PROP_END_OF_LIST() from riscv_cpu_extensions

On Thu, Jul 27, 2023 at 6:20 PM Daniel Henrique Barboza wrote: > > This last blank element is used by the 'for' loop to check if a property > has a valid name. > > Remove it and use ARRAY_SIZE() instead like riscv_cpu_options is already > using. All future arrays will also do the same and we'll ab

Re: [PATCH] hw/pci-host: Allow extended config space access for Designware PCIe host

On Wed, Aug 09, 2023 at 10:22:50AM +, Jason Chien wrote: > In pcie_bus_realize(), a root bus is realized as a PCIe bus and a non-root > bus is realized as a PCIe bus if its parent bus is a PCIe bus. However, > the child bus "dw-pcie" is realized before the parent bus "pcie" which is > the root

Re: [PATCH v6 12/12] target/riscv: deprecate the 'any' CPU type

On Thu, Jul 27, 2023 at 6:39 PM Daniel Henrique Barboza wrote: > > The 'any' CPU type was introduced in commit dc5bd18fa5725 ("RISC-V CPU > Core Definition"), being around since the beginning. It's not an easy > CPU to use: it's undocumented and its name doesn't tell users much about > what the CP

Re: [PATCH v4 9/9] docs/system: add basic virtio-gpu documentation

On Wed, Aug 9, 2023 at 11:55 PM Akihiko Odaki wrote: > On 2023/08/10 10:11, Gurchetan Singh wrote: > > > > > > On Tue, Aug 8, 2023 at 10:18 PM Akihiko Odaki > > wrote: > > > > On 2023/08/09 11:11, Gurchetan Singh wrote: > > > This adds basic documentation

Re: [PATCH v6 09/12] target/riscv/cpu.c: limit cfg->vext_spec log message

On Thu, Jul 27, 2023 at 6:22 PM Daniel Henrique Barboza wrote: > > Inside riscv_cpu_validate_v() we're always throwing a log message if the > user didn't set a vector version via 'vext_spec'. > > We're going to include one case with the 'max' CPU where env->vext_ver > will be set in the cpu_init()

Re: [PATCH v6 10/12] target/riscv: add 'max' CPU type

On Thu, Jul 27, 2023 at 6:53 PM Daniel Henrique Barboza wrote: > > The 'max' CPU type is used by tooling to determine what's the most > capable CPU a current QEMU version implements. Other archs such as ARM > implements this type. Let's add it to RISC-V. > > What we consider "most capable CPU" in

Re: [PATCH v6 11/12] avocado, risc-v: add opensbi tests for 'max' CPU

On Thu, Jul 27, 2023 at 6:33 PM Daniel Henrique Barboza wrote: > > Add smoke tests to ensure that we'll not break the 'max' CPU type when > adding new ratified extensions to be enabled. > > Signed-off-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Alistair > --- > tests/avocado/ri

Re: [PATCH v2] gdbstub: fixes cases where wrong threads were reported to GDB on SIGINT

Matheus Branco Borella writes: > Alex Bennée writes: >> Can gdb switch which packet sequence it uses to halt and restart >> threads? > > Yes, but the way it does it does not trigger the behavior I was concerned > about. GDB falls back to the old sequence when either (1) the target does not >

Re: [PATCH 2/2] riscv: zicond: make default

On Tue, Aug 8, 2023 at 6:10 PM Vineet Gupta wrote: > > > > On 8/8/23 14:06, Daniel Henrique Barboza wrote: > > (CCing Alistair and other reviewers) > > > > On 8/8/23 15:17, Vineet Gupta wrote: > >> Again this helps with better testing and something qemu has been doing > >> with newer features anyw

[PULL 0/4] tcg/gdbstub late fixes

s/pull-tcg-20230810 for you to fetch changes up to f1b0f894c8c25f7ed24197ff130c7acb6b9fd6e7: gdbstub: don't complain about preemptive ACK chars (2023-08-10 11:04:34 -0700) accel/tcg: Avoid reading too much in load_atom_{2,4} te

[PULL 2/4] tests/tcg: ensure system-mode gdb tests start stopped

From: Alex Bennée Without -S we run into potential races with tests starting before the gdbstub attaches. We don't need to worry about user-mode as enabling the gdbstub implies we wait for the initial connection. Signed-off-by: Alex Bennée Reviewed-by: Richard Henderson Reviewed-by: Philippe M

[PULL 4/4] gdbstub: don't complain about preemptive ACK chars

From: Alex Bennée When starting a remote connection GDB sends an '+': /* Ack any packet which the remote side has already sent. */ remote_serial_write ("+", 1); which gets flagged as a garbage character in the gdbstub state machine. As gdb does send it out lets be permissive about the hand

[PULL 1/4] accel/tcg: Avoid reading too much in load_atom_{2,4}

When load_atom_extract_al16_or_al8 is inexpensive, we want to use it early, in order to avoid the overhead of required_atomicity. However, we must not read past the end of the page. If there are more than 8 bytes remaining, then both the "aligned 16" and "aligned 8" paths align down so that the re

[PULL 3/4] gdbstub: more fixes for client Ctrl-C handling

From: Alex Bennée The original fix caused problems with spurious characters on other system emulation. So: - instead of spamming output make the warning a trace point - ensure we only allow a stop reply if it was 0x3 Suggested-by: Matheus Tavares Bernardino Signed-off-by: Alex Bennée Mess

Re: [PATCH v5 17/17] nbd/server: Add FLAG_PAYLOAD support to CMD_BLOCK_STATUS

On Thu, Aug 10, 2023 at 12:37:04PM -0500, Eric Blake wrote: > Allow a client to request a subset of negotiated meta contexts. For > example, a client may ask to use a single connection to learn about > both block status and dirty bitmaps, but where the dirty bitmap > queries only need to be perfor

Re: [PATCH 1/2] hw/intc: Fix upper/lower mtime write calculation

On Fri, Jul 28, 2023 at 5:13 AM Jason Chien wrote: > > When writing the upper mtime, we should keep the original lower mtime > whose value is given by cpu_riscv_read_rtc() instead of > cpu_riscv_read_rtc_raw(). The same logic applies to writes to lower mtime. > > Signed-off-by: Jason Chien Revie

Re: [PATCH 2/2] hw/intc: Make rtc variable names consistent

On Fri, Jul 28, 2023 at 4:57 AM Jason Chien wrote: > > The variables whose values are given by cpu_riscv_read_rtc() should be named > "rtc". The variables whose value are given by cpu_riscv_read_rtc_raw() > should be named "rtc_r". > > Signed-off-by: Jason Chien Reviewed-by: Alistair Francis A

Re: [PATCH QEMU v2 0/3] provide a smooth upgrade solution for multi-queues disk

On Thu, Aug 10, 2023 at 07:07:09AM +, ~hyman wrote: > Ping, > > This version is a copy of version 1 and is rebased > on the master. No functional changes. > > A 1:1 virtqueue:vCPU mapping implementation for virtio-*-pci disk > introduced since qemu >= 5.2.0, which improves IO performance > re

Re: [PATCH v3] target/riscv: Clearing the CSR values at reset and syncing the MPSTATE with the host

On Mon, Jul 24, 2023 at 2:26 AM liguang.zhang <18622748...@163.com> wrote: > > From: "liguang.zhang" > > Fix the guest reboot error when using KVM > There are two issues when rebooting a guest using KVM > 1. When the guest initiates a reboot the host is unable to stop the vcpu > 2. When running a

Re: Re: [PATCH] target/riscv: Clearing the CSR values at reset and syncing the MPSTATE with the host

On Mon, Jul 24, 2023 at 2:06 AM liguang.zhang <18622748...@163.com> wrote: > > > On Tue, Jul 18, 2023 at 10:22 PM liguang.zhang <18622748...@163.com> wrote: > > > > > > From: "liguang.zhang" > > > > > > Fix the guest reboot error when using KVM > > > There are two issues when rebooting a guest usi

Re: [PATCH 2/5] target/arm: Reduce dcz_blocksize to uint8_t

On 8/10/23 07:09, Peter Maydell wrote: On Thu, 10 Aug 2023 at 03:37, Richard Henderson wrote: This value is only 4 bits wide. True. Any particular reason to change the type, though? To save space. r~ Signed-off-by: Richard Henderson --- target/arm/cpu.h | 3 ++- 1 file changed, 2

Re: [PATCH 4/5] target/arm: Support more GM blocksizes

On 8/10/23 07:23, Peter Maydell wrote: +case 4: +/* 64 bytes -> 4 tags -> 16 result bits */ +ret = cpu_to_le16(*(uint16_t *)tag_mem); Does this really make a difference compared to ldw_le_p() ? ldw_le_p uses memcpy, though only mips and sparc hosts do not have unaligned re

[PATCH v2 0/8] Xilinx Versal CFI support

Hi, This series adds support for the Configuration Frame Unit (CFU) and the Configuration Frame controllers (CFRAME) to the Xilinx Versal machine ([1], chapter 21) for emulaing bitstream loading and readback. The series starts by introducing the Xilinx CFI interface that is thereafter used by the

[PATCH v2 1/8] hw/misc: Introduce the Xilinx CFI interface

Introduce the Xilinx Configuration Frame Interface (CFI) for transmitting CFI data packets between the Xilinx Configuration Frame Unit models (CFU_APB, CFU_FDRO and CFU_SFR), the Xilinx CFRAME controller (CFRAME_REG) and the Xilinx CFRAME broadcast controller (CFRAME_BCAST_REG) models (when emulati

[PATCH v2 2/8] hw/misc: Introduce a model of Xilinx Versal's CFU_APB

Introduce a model of the software programming interface (CFU_APB) of Xilinx Versal's Configuration Frame Unit. Signed-off-by: Francisco Iglesias --- MAINTAINERS | 2 + hw/misc/meson.build | 1 + hw/misc/xlnx-versal-cfu.c | 380 +

[PATCH v2 4/8] hw/misc/xlnx-versal-cfu: Introduce a model of Xilinx Versal's CFU_SFR

Introduce a model of Xilinx Versal's Configuration Frame Unit's Single Frame Read port (CFU_SFR). Signed-off-by: Francisco Iglesias --- hw/misc/xlnx-versal-cfu.c | 87 +++ include/hw/misc/xlnx-versal-cfu.h | 15 ++ 2 files changed, 102 insertions(+) diff

[PATCH v2 6/8] hw/misc: Introduce a model of Xilinx Versal's CFRAME_BCAST_REG

Introduce a model of Xilinx Versal's Configuration Frame broadcast controller (CFRAME_BCAST_REG). Signed-off-by: Francisco Iglesias --- hw/misc/xlnx-versal-cframe-reg.c | 161 +++ include/hw/misc/xlnx-versal-cframe-reg.h | 17 +++ 2 files changed, 178 insertions(+)

[PATCH v2 7/8] hw/arm/xlnx-versal: Connect the CFU_APB, CFU_FDRO and CFU_SFR

Connect the Configuration Frame Unit (CFU_APB, CFU_FDRO and CFU_SFR) to the Versal machine. Signed-off-by: Francisco Iglesias Acked-by: Edgar E. Iglesias Reviewed-by: Peter Maydell --- hw/arm/xlnx-versal.c | 42 include/hw/arm/xlnx-versal.h | 16 +++

[PATCH v2 8/8] hw/arm/versal: Connect the CFRAME_REG and CFRAME_BCAST_REG

Connect the Configuration Frame controller (CFRAME_REG) and the Configuration Frame broadcast controller (CFRAME_BCAST_REG) to the Versal machine. Signed-off-by: Francisco Iglesias --- hw/arm/xlnx-versal.c | 113 ++- include/hw/arm/xlnx-versal.h | 69

[PATCH v2 3/8] hw/misc/xlnx-versal-cfu: Introduce a model of Xilinx Versal CFU_FDRO

Introduce a model of Xilinx Versal's Configuration Frame Unit's data out port (CFU_FDRO). Signed-off-by: Francisco Iglesias --- hw/misc/xlnx-versal-cfu.c | 96 +++ include/hw/misc/xlnx-versal-cfu.h | 12 2 files changed, 108 insertions(+) diff --git a/hw

[PATCH v2 5/8] hw/misc: Introduce a model of Xilinx Versal's CFRAME_REG

Introduce a model of Xilinx Versal's Configuration Frame controller (CFRAME_REG). Signed-off-by: Francisco Iglesias --- MAINTAINERS | 2 + hw/misc/meson.build | 1 + hw/misc/xlnx-versal-cframe-reg.c | 753 +++ incl

Re: [PATCH v1 3/8] hw/misc/xlnx-versal-cfu: Introduce a model of Xilinx Versal CFU_FDRO

Hi Peter, On 2023-08-03 15:48, Peter Maydell wrote: On Mon, 10 Jul 2023 at 15:03, Francisco Iglesias wrote: Introduce a model of Xilinx Versal's Configuration Frame Unit's data out port (CFU_FDRO). Signed-off-by: Francisco Iglesias --- hw/misc/xlnx-versal-cfu.c | 105 +

Re: [PULL 0/4] tcg/gdbstub late fixes

https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20230810 for you to fetch changes up to f1b0f894c8c25f7ed24197ff130c7acb6b9fd6e7: gdbstub: don't complain about preemptive ACK chars (2023-08-10 11:04:34 -0700) accel/tcg

Re: [PULL 1/1] target/openrisc: Set EPCR to next PC on FPE exceptions

On Thu, Aug 10, 2023 at 09:35:18AM +0300, Michael Tokarev wrote: > 09.08.2023 23:34, Stafford Horne пишет: > > The architecture specification calls for the EPCR to be set to "Address > > of next not executed instruction" when there is a floating point > > exception (FPE). This was not being done,

Re: Re: [PATCH v1 1/3] softmmu/physmem: fallback to opening guest RAM file as readonly in a MAP_PRIVATE mapping

On Fri, Aug 11, 2023 at 01:06:12AM +0800, ThinerLogoer wrote: > >I think we have the following options (there might be more) > > > >1) This patch. > > > >2) New flag for memory-backend-file. We already have "readonly" and > >"share=". I'm having a hard time coming up with a good name that really

Re: [PATCH] thunk: Delete checks for old host definitions

On 2023/08/10 19:56, Philippe Mathieu-Daudé wrote: Helge and myself sometime run the tests on a HPPA host (testing the QEMU tools). I guess remember John Paul also runs some on Alpha (so Cc'ing him). Helge, what is your take on this? This file is only used in userspace emulation so it's not a

Re: [PATCH for-8.1 v10 10/14] util/selfmap: Rewrite using qemu/interval-tree.h

On Mon, 2023-08-07 at 11:17 -0700, Richard Henderson wrote: > On 8/7/23 09:37, Richard Henderson wrote: > > We will want to be able to search the set of mappings. > > For this patch, the two users iterate the tree in order. > > > > Signed-off-by: Richard Henderson > > --- > >   include/qemu/selfm

Re: [PATCH] thunk: Delete checks for old host definitions

On 8/10/23 23:29, Akihiko Odaki wrote: On 2023/08/10 19:56, Philippe Mathieu-Daudé wrote: Helge and myself sometime run the tests on a HPPA host I think we mix up HOST and TARGET here I run HPPA target (=guest) on x86-64 host. That means, both qemu-hppa-user and qemu-hppa-system does run f

[PATCH 2/3] linux-user: Fix the build on systems without MAP_SHARED_VALIDATE

CentOS 7 does not define MAP_SHARED_VALIDATE. Use a definition provided by the QEMU's copy of linux/mman.h. Fixes: 4b840f96096d ("linux-user: Populate more bits in mmap_flags_tbl") Signed-off-by: Ilya Leoshkevich --- linux-user/syscall.c | 1 + 1 file changed, 1 insertion(+) diff --git a/linux-

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