Hi Igor Mammedov:
On 7/28/23 9:21 PM, Igor Mammedov wrote:
On Thu, 20 Jul 2023 15:15:10 +0800
xianglai li wrote:
1.Add CPU topology related functions
2.Add CPU hot-plug related hook functions
3.Update the in-place CPU creation process at machine initialization
patch is to large, split it at
On 2023/8/9 03:26, Richard Henderson wrote:
On 8/7/23 18:54, Jiajie Chen wrote:
+static void loongarch_la464_initfn(Object *obj)
+{
+ LoongArchCPU *cpu = LOONGARCH_CPU(obj);
+ CPULoongArchState *env = &cpu->env;
+
+ loongarch_cpu_initfn_common(env);
+
+ cpu->dtb_compatible = "loong
On Wed, Aug 09, 2023 at 10:11:00AM +0800, Gurchetan Singh wrote:
> From: "Dr. David Alan Gilbert"
>
> Define a new capability type 'VIRTIO_PCI_CAP_SHARED_MEMORY_CFG' to allow
> defining shared memory regions with sizes and offsets of 2^32 and more.
> Multiple instances of the capability are allow
With the release of version 12 on June 10, 2023, Debian 10 is
not supported anymore. Modify the cross compiler container to
build on a newer version.
Signed-off-by: Paolo Bonzini
---
tests/docker/dockerfiles/debian-tricore-cross.docker | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff
The tricore tools are not detected when they are installed in
the host system, only if they are taken from an external
container. For this reason the build-tricore-softmmu job
was not running the TCG tests.
In addition the container provides all tools, not just as/ld/gcc,
so there is no need to s
Add is_la64 function to check if the current cpucfg[1].arch equals to
2(LA64).
Signed-off-by: Jiajie Chen
Co-authored-by: Richard Henderson
Reviewed-by: Richard Henderson
---
target/loongarch/cpu.h | 10 ++
1 file changed, 10 insertions(+)
diff --git a/target/loongarch/cpu.h b/target/
LoongArch64-only instructions are marked with regard to the instruction
manual Table 2. LSX instructions are not marked for now for lack of
public manual.
Signed-off-by: Jiajie Chen
---
target/loongarch/insn_trans/trans_arith.c.inc | 30
.../loongarch/insn_trans/trans_atomic.c.inc | 7
This patch series allow qemu-system-loongarch64 to emulate a LoongArch32
machine. A new CPU model (la132) is added for loongarch32, however due
to lack of public documentation, details will need to be added in the
future. Initial GDB support is added.
At the same time, VA32(32-bit virtual address)
Add object class for future loongarch32 cpus. It is derived from the
loongarch64 object class.
Signed-off-by: Jiajie Chen
---
target/loongarch/cpu.c | 19 +++
target/loongarch/cpu.h | 1 +
2 files changed, 20 insertions(+)
diff --git a/target/loongarch/cpu.c b/target/loongarch/
GPRs and PC are 32-bit wide in loongarch32 mode.
Signed-off-by: Jiajie Chen
Reviewed-by: Richard Henderson
---
configs/targets/loongarch64-softmmu.mak | 2 +-
gdb-xml/loongarch-base32.xml| 45 +
target/loongarch/cpu.c | 10 +-
target/loo
LA32 uses a different encoding for CSR.DMW and a new direct mapping
mechanism.
Signed-off-by: Jiajie Chen
Reviewed-by: Richard Henderson
---
target/loongarch/cpu-csr.h| 7 +++
target/loongarch/tlb_helper.c | 26 +++---
2 files changed, 26 insertions(+), 7 deletions(
VPPN of TLBEHI/TLBREHI is limited to 19 bits in LA32.
Signed-off-by: Jiajie Chen
Reviewed-by: Richard Henderson
---
target/loongarch/cpu-csr.h| 6 --
target/loongarch/tlb_helper.c | 23 ++-
2 files changed, 22 insertions(+), 7 deletions(-)
diff --git a/target/loong
Add la132 as a loongarch32 cpu type and allow virt machine to be used
with la132 instead of la464.
Due to lack of public documentation of la132, it is currently a
synthetic loongarch32 cpu model. Details need to be added in the future.
Signed-off-by: Jiajie Chen
---
hw/loongarch/virt.c| 5
Add LA64 and VA32(32-bit Virtual Address) to DisasContext to allow the
translator to reject doubleword instructions in LA32 mode for example.
Signed-off-by: Jiajie Chen
Reviewed-by: Richard Henderson
---
target/loongarch/cpu.h | 13 +
target/loongarch/translate.c | 3 +++
tar
The TLB entry of LA32 lacks NR, NX and RPLV and they are hardwired to
zero in LoongArch32.
Signed-off-by: Jiajie Chen
Reviewed-by: Richard Henderson
---
target/loongarch/cpu-csr.h| 9 +
target/loongarch/tlb_helper.c | 17 -
2 files changed, 17 insertions(+), 9 delet
In VA32 mode, BL, JIRL and PC* instructions should sign-extend the low
32 bit result to 64 bits.
Signed-off-by: Jiajie Chen
---
target/loongarch/insn_trans/trans_arith.c.inc | 2 +-
target/loongarch/insn_trans/trans_branch.c.inc | 4 ++--
target/loongarch/translate.c | 8 +
When running in VA32 mode(!LA64 or VA32L[1-3] matching PLV), virtual
address is truncated to 32 bits before address mapping.
Signed-off-by: Jiajie Chen
Co-authored-by: Richard Henderson
---
target/loongarch/cpu.c| 16
target/loongarch/cpu.h
Yeqi Fu writes:
> Introduce a new test for native calls to ensure their functionality.
> The process involves cross-compiling the test cases, building them
> as dynamically linked binaries, and running these binaries which
> necessitates the addition of the appropriate interpreter prefix.
>
> S
Paolo Bonzini writes:
> With the release of version 12 on June 10, 2023, Debian 10 is
> not supported anymore. Modify the cross compiler container to
> build on a newer version.
>
> Signed-off-by: Paolo Bonzini
> ---
> tests/docker/dockerfiles/debian-tricore-cross.docker | 2 +-
> 1 file cha
Acked-by: Nicholas Piggin
On Tue Aug 8, 2023 at 1:02 PM AEST, Richard Henderson wrote:
> Signed-off-by: Richard Henderson
> ---
> tcg/ppc/tcg-target.c.inc | 6 +++---
> 1 file changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc
> index 5
On 8/8/23 19:08, Stefan Hajnoczi wrote:
> On Mon, Jul 31, 2023 at 05:33:38PM -0300, Fabiano Rosas wrote:
>> We can fail the blk_insert_bs() at init_blk_migration(), leaving the
>> BlkMigDevState without a dirty_bitmap and BlockDriverState. Account
>> for the possibly missing elements when doing cle
On Tue Aug 8, 2023 at 1:02 PM AEST, Richard Henderson wrote:
> PADDI can load 34-bit immediates and 34-bit pc-relative addresses.
>
Reviewed-by: Nicholas Piggin
> Reviewed-by: Jordan Niethe
> Signed-off-by: Richard Henderson
> ---
> tcg/ppc/tcg-target.c.inc | 51 ++
On 8/8/23 17:40, Alex Williamson wrote:
> On Tue, 8 Aug 2023 16:59:16 +0200
> Laszlo Ersek wrote:
>
>> The Solarflare Communications SFC9220 NIC's physical function (PF) appears
>> to expose an expansion ROM with the following characteristics:
>>
>> (1) Single-image ROM, with only a legacy BIOS
Richard Henderson writes:
> Rather than using a zero tuple to end the table, use a macro
> to apply ARRAY_SIZE and pass that on to the convert functions.
>
> This fixes two bugs in which the conversion functions required
> that both the target and host masks be non-zero in order to
> continue,
Richard Henderson writes:
> New function that rejects unsupported map types and flags.
> In 4b840f96 we should not have accepted MAP_SHARED_VALIDATE
> without actually validating the rest of the flags.
>
> Fixes: 4b840f96 ("linux-user: Populate more bits in mmap_flags_tbl")
> Signed-off-by: Ric
Hi Peter!
-fd = file_ram_open(mem_path, memory_region_name(mr), readonly, &created,
- errp);
+fd = file_ram_open(mem_path, memory_region_name(mr), readonly, &created);
+if (fd == -EACCES && !(ram_flags & RAM_SHARED) && !readonly) {
+/*
+ * We can
On Tue Aug 8, 2023 at 1:52 PM AEST, Pavel Dovgalyuk wrote:
> On 08.08.2023 06:09, Nicholas Piggin wrote:
> > On Sun Aug 6, 2023 at 9:46 PM AEST, Nicholas Piggin wrote:
> >> On Fri Aug 4, 2023 at 6:50 PM AEST, Pavel Dovgalyuk wrote:
> >>> BTW, there is a function qemu_register_reset_nosnapshotload t
Move the matching between the "absent" array and dep_specs[0] inside
the loop, preparing for the possibility of having multiple canaries
among the installed packages.
Signed-off-by: Paolo Bonzini
---
python/scripts/mkvenv.py | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a
We would like to place all Python dependencies in the same file, so that
we can add more information without having long and complex command lines.
The plan is to have a TOML file with one entry per package, for example
[avocado]
avocado-framework = {
accepted = "(>=88.1, <93.0)",
inst
This brings in a newer version of the pipewire mapping, so rename it.
Python 3.9 and 3.10 do not seem to work in OpenSUSE LEAP 15.5 (weird,
because 3.9 persisted from 15.3 to 15.4) so bump the Python runtime
version to 3.11.
Signed-off-by: Paolo Bonzini
---
.../dockerfiles/debian-amd64-cross.do
This reverts commit e8e4298feadae7924cf7600bb3bcc5b0a8d7cbe9.
ensuregroup allows to specify both the acceptable versions of avocado,
and a locked version to be used when avocado is not installed as a system
pacakge. This lets us install avocado in pyvenv/ using "mkvenv.py" and
reuse the distro pa
This series introduce a new installation command for mkvenv.py that
retrieves the packages to be installed from a TOML file. This allows
being more flexible in using the system version of a package, while at
the same time using a known-good version when installing the package.
This is important for
Debian only introduced tomli in the bookworm release. Use a
vendored wheel to avoid requiring a package that is only in
bullseye-backports and is also absent in Ubuntu 20.04.
While at it, fix an issue in the vendor.py scripts which does
not add a newline after each package and hash.
Signed-off-b
Instead of having CI pick tomli from the vendored wheel at configure
time, place it in the containers.
Signed-off-by: Paolo Bonzini
---
.gitlab-ci.d/cirrus/freebsd-13.vars | 2 +-
.gitlab-ci.d/cirrus/macos-12.vars | 2 +-
tests/docker/dockerfiles/centos8.docker
Introduce a new subcommand that retrieves the packages to be installed
from a TOML file. This allows being more flexible in using the system
version of a package, while at the same time using a known-good version
when installing the package. This is important for packages that
sometimes have backw
Since there is a vendored copy, there is no point in choosing online
operation.
Signed-off-by: Paolo Bonzini
---
configure | 6 --
1 file changed, 6 deletions(-)
diff --git a/configure b/configure
index f2bd8858d6c..f13f0662b98 100755
--- a/configure
+++ b/configure
@@ -1018,13 +1018,7 @@ f
Using the new ensuregroup command, the desired versions of meson and
sphinx can be placed in pythondeps.toml rather than configure.
The meson.install entry in pythondeps.toml matches the version that is
found in python/wheels. This ensures that mkvenv.py uses the bundled
wheel even if PyPI is ena
ppce500_reset_device_tree is registered for system reset, but after
c4b075318eb1 this function rerandomizes rng-seed via
qemu_guest_getrandom_nofail. And when loading a snapshot, it tries to read
EVENT_RANDOM that doesn't exist, so we have an error:
qemu-system-ppc: Missing random event in the r
The legacy topology enumerated by CPUID.1.EBX[23:16] is defined in SDM
Vol2:
Bits 23-16: Maximum number of addressable IDs for logical processors in
this physical package.
When launching the VM with -smp 256, the value written to EBX[23:16] is
0 because of data overflow. If the guest only support
In pcie_bus_realize(), a root bus is realized as a PCIe bus and a non-root
bus is realized as a PCIe bus if its parent bus is a PCIe bus. However,
the child bus "dw-pcie" is realized before the parent bus "pcie" which is
the root PCIe bus. Thus, the extended configuration space is not accessible
on
On Tue, Aug 08, 2023 at 05:16:12PM +0200, Klaus Jensen wrote:
> From: Klaus Jensen
>
> Fix two potential accesses to null pointers.
>
> Klaus Jensen (2):
> hw/nvme: fix null pointer access in directive receive
> hw/nvme: fix null pointer access in ruh update
>
> hw/nvme/ctrl.c | 10 +++
On Tue, 2023-08-08 at 16:49 -0700, Richard Henderson wrote:
> This test fails when host page size != guest page size,
> because qemu may not be able to directly map the file.
>
> Fixes: a6341482695 ("tests/tcg: Add a test for info proc mappings")
> Signed-off-by: Richard Henderson
> ---
> tests/
On Tue Aug 8, 2023 at 1:02 PM AEST, Richard Henderson wrote:
> When the offset is out of range of the non-prefixed insn, but
> fits the 34-bit immediate of the prefixed insn, use that.
>
The switch will fall through in some cases (at least opi == 0).
Should it have a default: break; to make that o
On Wed, 9 Aug 2023 18:27:32 +0800
Qian Wen wrote:
> The legacy topology enumerated by CPUID.1.EBX[23:16] is defined in SDM
> Vol2:
>
> Bits 23-16: Maximum number of addressable IDs for logical processors in
> this physical package.
>
> When launching the VM with -smp 256, the value written to
On Tue Aug 8, 2023 at 1:02 PM AEST, Richard Henderson wrote:
> The prefixed instruction has a pc-relative form to use here.
I don't understand this code very well but going by existing
relocs it looks okay.
Reviewed-by: Nicholas Piggin
>
> Signed-off-by: Richard Henderson
> ---
> tcg/ppc/tcg-
On Tue Aug 8, 2023 at 1:02 PM AEST, Richard Henderson wrote:
> With Power v3.1, we have pc-relative addressing and so
> do not require a register holding the current TB.
>
Acked-by: Nicholas Piggin
> Signed-off-by: Richard Henderson
> ---
> tcg/ppc/tcg-target.c.inc | 2 +-
> 1 file changed, 1
On Tue Aug 8, 2023 at 1:02 PM AEST, Richard Henderson wrote:
> When a direct branch is out of range, we can load the destination for
> the indirect branch using PLA (for 16GB worth of buffer) and PLD from
> the TranslationBlock for everything larger.
>
> This means the patch affects exactly one ins
On 8/8/23 17:40, Alex Williamson wrote:
> On Tue, 8 Aug 2023 16:59:16 +0200
> Laszlo Ersek wrote:
>
>> The Solarflare Communications SFC9220 NIC's physical function (PF) appears
>> to expose an expansion ROM with the following characteristics:
>>
>> (1) Single-image ROM, with only a legacy BIOS
On Tue, 8 Aug 2023 11:51:21 -0400
Alistair Francis wrote:
> The Security Protocol and Data Model (SPDM) Specification defines
> messages, data objects, and sequences for performing message exchanges
> over a variety of transport and physical media.
> -
> https://www.dmtf.org/sites/default/file
In realm state, stage-2 translation tables are fetched from the realm
physical address space (R_PGRQD).
Signed-off-by: Jean-Philippe Brucker
Reviewed-by: Peter Maydell
---
target/arm/ptw.c | 26 ++
1 file changed, 18 insertions(+), 8 deletions(-)
diff --git a/target/arm
At the moment we only handle Secure and Nonsecure security spaces for
the AT instructions. Add support for Realm and Root.
For AArch64, arm_security_space() gives the desired space. ARM DDI0487J
says (R_NYXTL):
If EL3 is implemented, then when an address translation instruction
that applies t
GPC checks are not performed on the output address for AT instructions,
as stated by ARM DDI 0487J in D8.12.2:
When populating PAR_EL1 with the result of an address translation
instruction, granule protection checks are not performed on the final
output address of a successful translation.
When FEAT_RME is implemented, these bits override the value of
CNT[VP]_CTL_EL0.IMASK in Realm and Root state. Move the IRQ state update
into a new gt_update_irq() function and test those bits every time we
recompute the IRQ state.
Since we're removing the IRQ state from some trace events, add a ne
A few patches to fix RME support and allow booting a realm guest, based
on "[PATCH v2 00/15] target/arm/ptw: Cleanups and a few bugfixes"
https://lore.kernel.org/all/20230807141514.19075-1-peter.mayd...@linaro.org/
Since v2:
* Updated the comment in patch 5. I also removed the check for FEAT_RME,
When HCR_EL2.E2H is enabled, TLB entries are formed using the EL2&0
translation regime, instead of the EL2 translation regime. The TLB VAE2*
instructions invalidate the regime that corresponds to the current value
of HCR_EL2.E2H.
At the moment we only invalidate the EL2 translation regime. This ca
The AT instruction is UNDEFINED if the {NSE,NS} configuration is
invalid. Add a function to check this on all AT instructions that apply
to an EL lower than 3.
Suggested-by: Peter Maydell
Signed-off-by: Jean-Philippe Brucker
---
target/arm/helper.c | 38 +++---
1
This patch needs a detailed commit message, since it's not obvious why
these changes are made at all. It'd also be helpful for reviewing.
General style comment for shell scripts: Always put curly braces around
variables even if they are unnecessary. a $source_path could become
$source_pathPREF
On Tue, 08 Aug 2023 16:17, Yeqi Fu wrote:
+arm and aarch64
+---
+HLT is an invalid instruction for userspace and usefully has 16
+bits of spare immeadiate data which we can stuff data in.
s/immeadiate/immediate
With that fix, you can add
Reviewed-by: Emmanouil Pitsidianakis
Hello Nick,
On 8/8/23 06:19, Nicholas Piggin wrote:
TCG does not maintain the DEC reigster in the SPR array, so it does get
migrated. TCG also needs to re-start the decrementer timer on the
destination machine.
Load and store the decrementer into the SPR when migrating. This works
for the level
> On 8/2/23 06:08, Mikhail Tyutin wrote:
> > The fix is to clear TLB_INVALID_MASK bit in tlb_addr, as it happens in
> > other places e.g.
> > load_helper().
> >
> > Signed-off-by: Dmitriy Solovev
> > Signed-off-by: Mikhail Tyutin
> > ---
> > accel/tcg/cputlb.c | 2 +-
> > 1 file changed, 1 in
On 8/9/2023 7:14 PM, Igor Mammedov wrote:
> On Wed, 9 Aug 2023 18:27:32 +0800
> Qian Wen wrote:
>
>> The legacy topology enumerated by CPUID.1.EBX[23:16] is defined in SDM
>> Vol2:
>>
>> Bits 23-16: Maximum number of addressable IDs for logical processors in
>> this physical package.
>>
>> When l
From: Klaus Jensen
Hi,
The following changes since commit a8fc5165aab02f328ccd148aafec1e59fd1426eb:
Merge tag 'nvme-next-pull-request' of https://gitlab.com/birkelund/qemu into
staging (2023-08-08 16:39:20 -0700)
are available in the Git repository at:
https://gitlab.com/birkelund/qemu.g
On Mon, 7 Aug 2023 22:31:35 +0800
Zhao Liu wrote:
> Hi Igor,
>
> On Mon, Aug 07, 2023 at 12:11:29PM +0200, Igor Mammedov wrote:
> > Date: Mon, 7 Aug 2023 12:11:29 +0200
> > From: Igor Mammedov
> > Subject: Re: [PATCH v2 2/3] hw/smbios: Fix thread count in type4
> > X-Mailer: Claws Mail 4.1.1 (G
From: Klaus Jensen
The Reclaim Unit Update operation in I/O Management Receive does not
verify the presence of a configured endurance group prior to accessing
it.
Fix this.
Cc: qemu-sta...@nongnu.org
Fixes: 73064edfb864 ("hw/nvme: flexible data placement emulation")
Reviewed-by: Jesper Wendel D
From: Klaus Jensen
nvme_directive_receive() does not check if an endurance group has been
configured (set) prior to testing if flexible data placement is enabled
or not.
Fix this.
Cc: qemu-sta...@nongnu.org
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1815
Fixes: 73064edfb864 ("hw/nv
On Wed, 9 Aug 2023 21:20:48 +0800
"Wen, Qian" wrote:
> On 8/9/2023 7:14 PM, Igor Mammedov wrote:
> > On Wed, 9 Aug 2023 18:27:32 +0800
> > Qian Wen wrote:
> >
> >> The legacy topology enumerated by CPUID.1.EBX[23:16] is defined in SDM
> >> Vol2:
> >>
> >> Bits 23-16: Maximum number of address
On Wed, Aug 09, 2023 at 10:29:44AM +0200, Paolo Bonzini wrote:
> The tricore tools are not detected when they are installed in
> the host system, only if they are taken from an external
> container. For this reason the build-tricore-softmmu job
> was not running the TCG tests.
>
> In addition the
On Wed, Aug 09, 2023 at 03:49:01PM +0200, Bastian Koppelmann wrote:
> On Wed, Aug 09, 2023 at 10:29:44AM +0200, Paolo Bonzini wrote:
> > The tricore tools are not detected when they are installed in
> > the host system, only if they are taken from an external
> > container. For this reason the bui
On Wed, Aug 09, 2023 at 10:29:45AM +0200, Paolo Bonzini wrote:
> With the release of version 12 on June 10, 2023, Debian 10 is
> not supported anymore. Modify the cross compiler container to
> build on a newer version.
>
> Signed-off-by: Paolo Bonzini
> ---
> tests/docker/dockerfiles/debian-tri
On Sun, Aug 06, 2023 at 02:31:43PM +0800, Yong Huang wrote:
> On Sat, Aug 5, 2023 at 2:05 AM Markus Armbruster wrote:
>
> > Andrei Gudkov writes:
> >
> > > Introduces alternative argument calc-time-ms, which is the
> > > the same as calc-time but accepts millisecond value.
> > > Millisecond gran
On Wed, Aug 9, 2023 at 3:53 PM Bastian Koppelmann
wrote:
> > diff --git a/tests/docker/dockerfiles/debian-tricore-cross.docker
> > b/tests/docker/dockerfiles/debian-tricore-cross.docker
> > index 269bfa8d423..5bd1963fb55 100644
> > --- a/tests/docker/dockerfiles/debian-tricore-cross.docker
> > ++
On 8/9/23 06:17, Mikhail Tyutin wrote:
Would not be better to get back to initial v1 approach when we clean
TLB_INVALID_MASK flag in
tlb_plugin_lookup()? It works well for those regions.
You're just as likely to get invalid data.
r~
On 8/9/23 01:26, Jiajie Chen wrote:
Add object class for future loongarch32 cpus. It is derived from the
loongarch64 object class.
Signed-off-by: Jiajie Chen
---
target/loongarch/cpu.c | 19 +++
target/loongarch/cpu.h | 1 +
2 files changed, 20 insertions(+)
Reviewed-by: R
Yeqi Fu writes:
> Signed-off-by: Yeqi Fu
> ---
> configure | 57 +--
> 1 file changed, 34 insertions(+), 23 deletions(-)
>
> diff --git a/configure b/configure
> index 2b41c49c0d..a076583141 100755
> --- a/configure
> +++ b/configure
> @@ -1
Hello Joel,
So we're re-using the same xscom ops as on P8. A quick look at the
definition of those 4 registers on P8 (0xb0020) and on P9/P10
(0x00090040) seem to show they are not the same though. Am i missing
something?
Fred
On 08/08/2023 10:34, Joel Stanley wrote:
From P9 on the LPC
On 8/9/23 01:26, Jiajie Chen wrote:
LoongArch64-only instructions are marked with regard to the instruction
manual Table 2. LSX instructions are not marked for now for lack of
public manual.
I would expect LSX not to be affected by CPUCFG.1.ARCH, but only by
CPUCFG.2.LSX.
Note that there appe
On Sun, Aug 06, 2023 at 02:16:34PM +0800, Yong Huang wrote:
> On Fri, Aug 4, 2023 at 11:03 PM Andrei Gudkov
> wrote:
>
> > Introduces alternative argument calc-time-ms, which is the
> > the same as calc-time but accepts millisecond value.
> > Millisecond granularity allows to make predictions whe
On 8/9/23 01:26, Jiajie Chen wrote:
When running in VA32 mode(!LA64 or VA32L[1-3] matching PLV), virtual
address is truncated to 32 bits before address mapping.
Signed-off-by: Jiajie Chen
Co-authored-by: Richard Henderson
---
target/loongarch/cpu.c| 16
target
On 8/9/23 01:26, Jiajie Chen wrote:
In VA32 mode, BL, JIRL and PC* instructions should sign-extend the low
32 bit result to 64 bits.
Signed-off-by: Jiajie Chen
---
target/loongarch/insn_trans/trans_arith.c.inc | 2 +-
target/loongarch/insn_trans/trans_branch.c.inc | 4 ++--
target/loongarch
Fix a crash in qemu-user when running
cat /proc/self/maps
in a chroot, where /proc isn't mounted.
The problem was introduced by commit 3ce3dd8ca965 ("util/selfmap:
Rewrite using qemu/interval-tree.h") where in open_self_maps_1() the
function read_self_maps() is called and which returns NULL
On 8/9/23 01:26, Jiajie Chen wrote:
Add la132 as a loongarch32 cpu type and allow virt machine to be used
with la132 instead of la464.
Due to lack of public documentation of la132, it is currently a
synthetic loongarch32 cpu model. Details need to be added in the future.
Signed-off-by: Jiajie C
On Wed, Aug 09, 2023 at 11:20:11AM +0200, David Hildenbrand wrote:
> Hi Peter!
Hi, David,
>
> > > -fd = file_ram_open(mem_path, memory_region_name(mr), readonly,
> > > &created,
> > > - errp);
> > > +fd = file_ram_open(mem_path, memory_region_name(mr), readonly,
>
On 8/9/23 08:11, Helge Deller wrote:
Fix a crash in qemu-user when running
cat /proc/self/maps
in a chroot, where /proc isn't mounted.
The problem was introduced by commit 3ce3dd8ca965 ("util/selfmap:
Rewrite using qemu/interval-tree.h") where in open_self_maps_1() the
function read_self_
Yeqi Fu writes:
> This commit implements a shared library, where native functions are
> rewritten as special instructions. At runtime, user programs load
> the shared library, and special instructions are executed when
> native functions are called.
>
> Signed-off-by: Yeqi Fu
> ---
> Makefile
On 2023-07-31 at 12:21:57 -0400, Xiaoyao Li wrote:
> From: Chao Peng
>
> Currently only KVM_MEMORY_EXIT_FLAG_PRIVATE in flags is valid when
> KVM_EXIT_MEMORY_FAULT happens. It indicates userspace needs to do
> the memory conversion on the RAMBlock to turn the memory into desired
> attribute, i.e.
Alex Bennée writes:
> Yeqi Fu writes:
>
>> Signed-off-by: Yeqi Fu
>> ---
>> configure | 57 +--
>> 1 file changed, 34 insertions(+), 23 deletions(-)
>>
>> diff --git a/configure b/configure
>> index 2b41c49c0d..a076583141 100755
>> --- a/co
On Wed, Aug 09, 2023 at 06:02:52PM +0300, gudkov.and...@huawei.com wrote:
> > Not for the patch, I'm just curious about how the predication
> > decides the network throughput, I mean QEMU predicts
> > if migration will converge based on how fast it sends the data,
> > not the actual bandwidth of th
From: Hyman Huang(黄勇)
The dirty limit feature has been introduced since the 8.1
QEMU release but has not reflected in the document, add a
section for that.
Signed-off-by: Hyman Huang(黄勇)
---
docs/devel/migration.rst | 70
1 file changed, 70 insertions(+
On 8/8/23 07:17, Yeqi Fu wrote:
+#define native_bypass_enabled() native_lib_path ? true : false
Need parenthesis for the expression, and possibly better as
(native_lib_path != NULL)
rather than ternary expression.
+#if defined(CONFIG_NATIVE_CALL)
+/* Set the library for native bypas
On 8/8/23 07:17, Yeqi Fu wrote:
Signed-off-by: Yeqi Fu
---
include/qemu/envlist.h| 13 ++
tests/unit/meson.build| 1 +
tests/unit/test-envlist.c | 94 +++
util/envlist.c| 71 -
4 files changed, 169 ins
Yeqi Fu writes:
> Signed-off-by: Yeqi Fu
> ---
> include/qemu/envlist.h| 13 ++
> tests/unit/meson.build| 1 +
> tests/unit/test-envlist.c | 94 +++
> util/envlist.c| 71 -
> 4 files changed, 169 insertio
Yeqi Fu writes:
> This commit implements the -native-bypass support in linux-user. The
> native_calls_enabled() function can be true only when the
> '-native-bypass' option is given.
>
> Signed-off-by: Yeqi Fu
> ---
> include/native/native.h | 9 +
> linux-user/main.c | 38
On 8/9/23 17:23, Richard Henderson wrote:
On 8/9/23 08:11, Helge Deller wrote:
Fix a crash in qemu-user when running
cat /proc/self/maps
in a chroot, where /proc isn't mounted.
The problem was introduced by commit 3ce3dd8ca965 ("util/selfmap:
Rewrite using qemu/interval-tree.h") where in
On 8/8/23 07:17, Yeqi Fu wrote:
+char *new_env_value = NULL;
+size_t new_env_len = strlen(entry->ev_var) + strlen(eq_sign)
++ strlen(separator) + 1;
+new_env_value = g_malloc(new_env_len);
+strcpy(new_env_value, entry->ev_var);
+strcat(new_env_v
On 8/8/23 07:17, Yeqi Fu wrote:
+#if defined(i386) || defined(x86_64)
+/*
+ * An unused instruction is utilized to mark a native call.
+ */
+#define __CALL_EXPR ".byte 0x0f, 0xff;"
+#endif
This is 2 of the 3 (or more) bytes of the UD0 instruction.
At minimum you should include a third byte for
On 8/8/23 07:17, Yeqi Fu wrote:
This commit addresses the need to parse symbols of native libraries.
The base address of a shared library is determined by the dynamic
linker. To simplify the process, we focus on the last three digits,
which reside within the same page and remain unaffected by the
On 8/9/23 08:53, Helge Deller wrote:
On 8/9/23 17:23, Richard Henderson wrote:
On 8/9/23 08:11, Helge Deller wrote:
Fix a crash in qemu-user when running
cat /proc/self/maps
in a chroot, where /proc isn't mounted.
The problem was introduced by commit 3ce3dd8ca965 ("util/selfmap:
Rewrite
On 8/8/23 07:17, Yeqi Fu wrote:
This commit introduces support for native library calls on the
i386 target. When special instructions reserved for native calls
are encountered, the code now performs address translation and
generates the corresponding native call.
Signed-off-by: Yeqi Fu
---
co
On Wed, Aug 09, 2023 at 04:33:37PM +0200, Paolo Bonzini wrote:
> On Wed, Aug 9, 2023 at 3:53 PM Bastian Koppelmann
> wrote:
> > > diff --git a/tests/docker/dockerfiles/debian-tricore-cross.docker
> > > b/tests/docker/dockerfiles/debian-tricore-cross.docker
> > > index 269bfa8d423..5bd1963fb55 100
On Wed, Aug 9, 2023 at 8:11 AM Jonathan Cameron
wrote:
>
> On Tue, 8 Aug 2023 11:51:21 -0400
> Alistair Francis wrote:
>
> > The Security Protocol and Data Model (SPDM) Specification defines
> > messages, data objects, and sequences for performing message exchanges
> > over a variety of transpor
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