On 7/14/23 16:46, Peter Maydell wrote:
For an Unsupported Atomic Update fault where the stage 1 translation
table descriptor update can't be done because it's to an unsupported
memory type, this is a stage 1 abort (per the Arm ARM R_VSXXT). This
means we should not set fi->s1ptw, because this wi
This series enables shadowed CVQ to intercept VLAN commands
through shadowed CVQ, update the virtio NIC device model
so qemu send it in a migration, and the restore of that
VLAN state in the destination.
ChangeLog
=
v2:
- remove the extra line pointed out by Eugenio in patch 3
"vdpa: Rest
vhost-vdpa shadowed CVQ needs to know the maximum number of
vlans supported by the virtio-net device, so QEMU can restore
the VLAN state in a migration.
Co-developed-by: Eugenio Pérez
Signed-off-by: Eugenio Pérez
Signed-off-by: Hawkins Jiawei
---
hw/net/virtio-net.c| 2 --
include/
From: Eugenio Pérez
This function is called after virtio_load, so all vlan configuration is
lost in migration case.
Just allow all the vlan-tagged packets if vlan is not configured, and
trust device reset to clear all filtered vlans.
Fixes: 0b1eaa8803 ("virtio-net: Do not filter VLANs without F
Enable SVQ with VIRTIO_NET_F_CTRL_VLAN feature.
Co-developed-by: Eugenio Pérez
Signed-off-by: Eugenio Pérez
Signed-off-by: Hawkins Jiawei
---
net/vhost-vdpa.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/net/vhost-vdpa.c b/net/vhost-vdpa.c
index 347241796d..73e9063fa0 100644
--- a/net/v
This patch introduces vhost_vdpa_net_load_single_vlan()
and vhost_vdpa_net_load_vlan() to restore the vlan
filtering state at device's startup.
Co-developed-by: Eugenio Pérez
Signed-off-by: Eugenio Pérez
Signed-off-by: Hawkins Jiawei
---
v2:
- remove the extra line pointed out by Eugenio
v1:
From: Bin Meng
Upgrade OpenSBI from v1.3 to v1.3.1 and the pre-built bios images
which fixes the boot failure seen when using QEMU to do a direct
kernel boot with Microchip Icicle Kit board machine.
The v1.3.1 release includes the following commits:
0907de3 lib: sbi: fix comment indent
eb736a5
v-to-apply-20230723-3
for you to fetch changes up to dcaaf2bf9bfd2c664dbeff0069fcab3d75c924d3:
roms/opensbi: Upgrade from v1.3 to v1.3.1 (2023-07-23 19:32:02 +1000)
Fifth RISC-V PR for 8.1
* roms/opensbi: Upgrade from v1.3
On 7/14/23 16:46, Peter Maydell wrote:
In S1_ptw_translate() we set up the ARMMMUFaultInfo if the attempt to
translate the page descriptor address into a physical address fails.
This used to only be possible if we are doing a stage 2 ptw for that
descriptor address, and so the code always sets fi
On 2023/7/23 17:26, Hawkins Jiawei wrote:
> From: Eugenio Pérez
There was a wrong "From" line by mistake, I will send the v3 patch to
fix this.
Thanks!
>
> This function is called after virtio_load, so all vlan configuration is
> lost in migration case.
>
> Just allow all the vlan-tagged packe
On 7/14/23 16:46, Peter Maydell wrote:
The s1ns bit in ARMMMUFaultInfo is documented as "true if
we faulted on a non-secure IPA while in secure state". Both the
places which look at this bit only do so after having confirmed
that this is a stage 2 fault and we're dealing with Secure EL2,
which le
On 7/14/23 16:46, Peter Maydell wrote:
In commit 6d2654ffacea813916176 we created the S1Translate struct and
used it to plumb through various arguments that we were previously
passing one-at-a-time to get_phys_addr_v5(), get_phys_addr_v6(), and
get_phys_addr_lpae(). Extend that pattern to get_ph
On 7/14/23 16:46, Peter Maydell wrote:
Plumb the ARMSecurityState through to regime_translation_disabled()
rather than just a bool is_secure.
Signed-off-by: Peter Maydell
---
target/arm/ptw.c | 15 ---
1 file changed, 8 insertions(+), 7 deletions(-)
Reviewed-by: Richard Henderso
On 21/07/2023 15:09, Cédric Le Goater wrote:
External email: Use caution opening links or attachments
On 7/16/23 10:15, Avihai Horon wrote:
Now that P2P support has been added to VFIO migration, allow migration
of multiple devices if all of them support P2P migration.
Single device migratio
On 21/07/2023 14:48, Cédric Le Goater wrote:
External email: Use caution opening links or attachments
On 7/16/23 10:15, Avihai Horon wrote:
VFIO migration uAPI defines an optional intermediate P2P quiescent
state. While in the P2P quiescent state, P2P DMA transactions cannot be
initiated by
This series enables shadowed CVQ to intercept VLAN commands
through shadowed CVQ, update the virtio NIC device model
so qemu send it in a migration, and the restore of that
VLAN state in the destination.
ChangeLog
=
v3:
- remove the extra "From" line in patch 1
"virtio-net: do not reset v
This function is called after virtio_load, so all vlan configuration is
lost in migration case.
Just allow all the vlan-tagged packets if vlan is not configured, and
trust device reset to clear all filtered vlans.
Fixes: 0b1eaa8803 ("virtio-net: Do not filter VLANs without F_CTRL_VLAN")
Signed-of
Enable SVQ with VIRTIO_NET_F_CTRL_VLAN feature.
Co-developed-by: Eugenio Pérez
Signed-off-by: Eugenio Pérez
Signed-off-by: Hawkins Jiawei
---
net/vhost-vdpa.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/net/vhost-vdpa.c b/net/vhost-vdpa.c
index 347241796d..73e9063fa0 100644
--- a/net/v
This patch introduces vhost_vdpa_net_load_single_vlan()
and vhost_vdpa_net_load_vlan() to restore the vlan
filtering state at device's startup.
Co-developed-by: Eugenio Pérez
Signed-off-by: Eugenio Pérez
Signed-off-by: Hawkins Jiawei
---
v2:
- remove the extra line pointed out by Eugenio
v1:
vhost-vdpa shadowed CVQ needs to know the maximum number of
vlans supported by the virtio-net device, so QEMU can restore
the VLAN state in a migration.
Co-developed-by: Eugenio Pérez
Signed-off-by: Eugenio Pérez
Signed-off-by: Hawkins Jiawei
---
hw/net/virtio-net.c| 2 --
include/
On 7/21/23 19:13, BALATON Zoltan wrote:
The board firmware handles this correctly following the Open Firmware
standard which we missed. This fixes 64 bit BARs when using VOF.
Signed-off-by: BALATON Zoltan
---
Reviewed-by: Daniel Henrique Barboza
And queued. Thanks,
Daniel
hw/ppc/p
On Sat, 22 Jul 2023 at 12:35, Richard Henderson
wrote:
>
> Signed-off-by: Richard Henderson
> ---
> include/exec/exec-all.h | 10 ++
> bsd-user/mmap.c | 1 +
> linux-user/mmap.c | 1 +
> 3 files changed, 12 insertions(+)
>
> diff --git a/include/exec/exec-all.h b/include/
On Sat, 22 Jul 2023 at 12:35, Richard Henderson
wrote:
>
> In the initial commit, cdfac37be0d, the sense of the test is incorrect,
> as the -1/0 return was confusing. In bef6f008b981, we mechanically
> invert all callers while changing to false/true return, preserving the
> incorrectness of the t
On Sat, 22 Jul 2023 at 12:35, Richard Henderson
wrote:
>
> For user-only, the probe for page writability may race with another
> thread's mprotect. Take the mmap_lock around the operation. This
> is still faster than the start/end_exclusive fallback.
>
> Signed-off-by: Richard Henderson
> ---
>
On 7/23/23 15:18, Peter Maydell wrote:
On Sat, 22 Jul 2023 at 12:35, Richard Henderson
wrote:
Signed-off-by: Richard Henderson
---
include/exec/exec-all.h | 10 ++
bsd-user/mmap.c | 1 +
linux-user/mmap.c | 1 +
3 files changed, 12 insertions(+)
diff --git a/incl
On 7/14/23 16:46, Peter Maydell wrote:
arm_hcr_el2_eff_secstate() takes a bool secure, which it uses to
determine whether EL2 is enabled in the current security state.
With the advent of FEAT_RME this is no longer sufficient, because
EL2 can be enabled for Secure state but not for Root, and both
On 7/14/23 16:46, Peter Maydell wrote:
When we do a translation in Secure state, the NSTable bits in table
descriptors may downgrade us to NonSecure; we update ptw->in_secure
and ptw->in_space accordingly. We guard that check correctly with a
conditional that means it's only applied for Secure s
On 7/14/23 16:46, Peter Maydell wrote:
Replace the last uses of ptw->in_secure with appropriate
checks on ptw->in_space.
Signed-off-by: Peter Maydell
---
target/arm/ptw.c | 11 +++
1 file changed, 7 insertions(+), 4 deletions(-)
Reviewed-by: Richard Henderson
r~
On 7/14/23 16:46, Peter Maydell wrote:
We no longer look at the in_secure field of the S1Translate struct
anyway, so we can remove it and all the code which sets it.
Signed-off-by: Peter Maydell
---
target/arm/ptw.c | 13 -
1 file changed, 13 deletions(-)
Reviewed-by: Richard He
On 7/14/23 16:46, Peter Maydell wrote:
We only use S1Translate::out_secure in two places, where we are
setting up MemTxAttrs for a page table load. We can use
arm_space_is_secure(ptw->out_space) instead, which guarantees
that we're setting the MemTxAttrs secure and space fields
consistently, and
On 7/14/23 16:46, Peter Maydell wrote:
When the MMU is disabled, data accesses should be Device nGnRnE,
Outer Shareable, Untagged. We handle the other cases from
AArch64.S1DisabledOutput() correctly but missed this one.
Device nGnRnE is memattr == 0, so the only part we were missing
was that sha
On 7/14/23 16:46, Peter Maydell wrote:
The architecture doesn't permit block descriptors at any arbitrary
level of the page table walk; it depends on the granule size which
levels are permitted. We implemented only a partial version of this
check which assumes that block descriptors are valid at
On 7/14/23 16:46, Peter Maydell wrote:
When we report faults due to stage 2 faults during a stage 1
page table walk, the 'level' parameter should be the level
of the walk in stage 2 that faulted, not the level of the
walk in stage 1. Correct the reporting of these faults.
Signed-off-by: Peter Ma
On 7/14/23 16:46, Peter Maydell wrote:
The PAR_EL1.SH field documents that for the cases of:
* Device memory
* Normal memory with both Inner and Outer Non-Cacheable
the field should be 0b10 rather than whatever was in the
translation table descriptor field. (In the pseudocode this
is handled
On 7/19/23 23:11, Ilya Leoshkevich wrote:
R2 designates an even-odd register pair; the instruction should raise
a specification exception when R2 is not even.
Cc: qemu-sta...@nongnu.org
Fixes: e023e832d0ac ("s390x: translate engine for s390x CPU")
Reviewed-by: David Hildenbrand
Signed-off-by: I
On 7/19/23 23:11, Ilya Leoshkevich wrote:
When the mask is zero, access exceptions should still be recognized for
1 byte at the second-operand address. CC should be set to 0.
Reviewed-by: David Hildenbrand
Cc: qemu-sta...@nongnu.org
Fixes: defb0e3157af ("s390x: Implement opcode helpers")
Signed
On 7/19/23 23:11, Ilya Leoshkevich wrote:
CONVERT TO LOGICAL/FIXED deviate from IEEE 754 in that they raise an
inexact exception on out-of-range inputs. float_flag_invalid_cvti
aligns nicely with that behavior, so convert it to
S390_IEEE_MASK_INEXACT.
Cc:qemu-sta...@nongnu.org
Fixes: defb0e3157a
On 7/19/23 23:11, Ilya Leoshkevich wrote:
When the mask is zero, access exceptions should still be recognized for
1 byte at the second-operand address. CC should be set to 0.
Cc:qemu-sta...@nongnu.org
Fixes: e023e832d0ac ("s390x: translate engine for s390x CPU")
Reviewed-by: David Hildenbrand
Si
On 7/19/23 23:11, Ilya Leoshkevich wrote:
MC requires bit positions 8-11 (upper 4 bits of class) to be zeros,
otherwise it must raise a specification exception.
Cc:qemu-sta...@nongnu.org
Fixes: 20d143e2cab8 ("s390x/tcg: Implement MONITOR CALL")
Reviewed-by: David Hildenbrand
Signed-off-by: Ilya
On 7/19/23 23:11, Ilya Leoshkevich wrote:
i386 and s390x implementations of op_add2 require an earlyclobber,
which is currently missing. This breaks VCKSM in s390x guests. E.g., on
x86_64 the following op:
add2_i32 tmp2,tmp3,tmp2,tmp3,tmp3,tmp2 dead: 0 2 3 4 5 pref=none,0x
is transl
On 7/19/23 23:11, Ilya Leoshkevich wrote:
Type 13 is reserved, so using it should result in specification
exception. Due to an off-by-1 error the code triggers an assertion at a
later point in time instead.
Cc:qemu-sta...@nongnu.org
Fixes: da4807527f3b ("s390x/tcg: Implement VECTOR FP (MAXIMUM|M
On 7/19/23 02:03, Jordan Niethe wrote:
On 5/4/23 1:04 am, Richard Henderson wrote:
Something is wrong with this code, and also wrong with gdb on the
sparc systems to which I have access, so I cannot debug it either.
Disable for now, so the release is not broken.
I'm not sure if it is the ent
On 7/13/23 13:07, Anton Johansson wrote:
In replacing target_ulong with vaddr and TARGET_FMT_lx with VADDR_PRIx,
the zero-padding of TARGET_FMT_lx got lost. Readd 16-wide zero-padding
for logging consistency.
Suggested-by: Peter Maydell
Signed-off-by: Anton Johansson
---
accel/tcg/cputlb.c |
On 7/18/23 15:50, Luca Bonissi wrote:
On 32bit qemu-user targets, memory allocation failed after about 2GB due to incorrect
signed (instead of the correct unsigned) "last" parameter in pageflags_find and
pageflags_next functions (file accel/tcg/user-exec.c).
The parameter, on 32bit targets, wi
When QEMU is started with `-smp D,sockets=1,dies=D,cores=1,threads=1` (that
is, 1 socket with D dies but each die contains just a single thread), both
Linux and Windows guests incorrectly interprets the system as having D
sockets with 1 die each
Ultimately this is caused by various CPUID leaves no
Signed-off-by: Sergii Zasenko
---
ui/vnc.c | 5 -
1 file changed, 5 deletions(-)
diff --git a/ui/vnc.c b/ui/vnc.c
index 92964dc..dea1414 100644
--- a/ui/vnc.c
+++ b/ui/vnc.c
@@ -3715,11 +3715,6 @@ static int vnc_display_get_address(const char *addrstr,
addr->type = SOCKET_ADDRESS_TY
On Fri, Jul 21, 2023 at 7:48 PM Thomas Huth wrote:
>
> Values that have been read via cpu_physical_memory_read() from the
> guest's memory have to be swapped in case the host endianess differs
> from the guest.
>
> Fixes: a6e13e31d5 ("riscv_htif: Support console output via proxy syscall")
> Signed
On Fri, Jul 21, 2023 at 7:48 PM Thomas Huth wrote:
>
> The character that should be printed is stored in the 64 bit "payload"
> variable. The code currently tries to print it by taking the address
> of the variable and passing this pointer to qemu_chr_fe_write(). However,
> this only works on litt
On Fri, Jul 21, 2023 at 11:35 PM Daniel Henrique Barboza
wrote:
>
> The 'host' CPU is available in a CONFIG_KVM build and it's currently
> available for all accels, but is a KVM only CPU. This means that in a
> RISC-V KVM capable host we can do things like this:
>
> $ ./build/qemu-system-riscv64 -
On Thu, Jul 20, 2023 at 11:25 PM Daniel Henrique Barboza
wrote:
>
> zmmul was promoted from experimental to ratified in commit 6d00ffad4e95.
> Add a riscv,isa string for it.
>
> Fixes: 6d00ffad4e95 ("target/riscv: move zmmul out of the experimental
> properties")
> Signed-off-by: Daniel Henrique
On Thu, Jul 20, 2023 at 11:26 PM Daniel Henrique Barboza
wrote:
>
> The cpu->cfg.epmp extension is still experimental, but it already has a
> 'smepmp' riscv,isa string. Add it.
>
> Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Alistair Francis
Alistair
> ---
> target/riscv/cpu.c | 1 +
On Fri, Jul 21, 2023 at 11:35 PM Daniel Henrique Barboza
wrote:
>
> The 'host' CPU is available in a CONFIG_KVM build and it's currently
> available for all accels, but is a KVM only CPU. This means that in a
> RISC-V KVM capable host we can do things like this:
>
> $ ./build/qemu-system-riscv64 -
On Fri, Jul 21, 2023 at 7:48 PM Thomas Huth wrote:
>
> The tests/avocado/riscv_opensbi.py avocado test is currently failing
> on big endian hosts since the console of the Spike machine is not
> working there. With two small patches, this can be fixed: First patch
> fixes riscv64, and the second on
On Thu, Jul 13, 2023 at 2:41 AM Sunil V L wrote:
>
> The functions which add fw_cfg and virtio to DSDT are same for ARM
> and RISC-V. So, instead of duplicating in RISC-V, move them from
> hw/arm/virt-acpi-build.c to common aml-build.c.
>
> Signed-off-by: Sunil V L
Reviewed-by: Alistair Francis
On Thu, Jul 13, 2023 at 2:42 AM Sunil V L wrote:
>
> The PCI bus information is needed in RISCVVirtState so that other
> files like virt-acpi-build.c can make use of it. Add new field in
> RISCVVirtState so that ACPI code can use it.
>
> Signed-off-by: Sunil V L
Reviewed-by: Alistair Francis
A
On Thu, Jul 13, 2023 at 2:42 AM Sunil V L wrote:
>
> Some macros and static function related to IMSIC are defined
> in virt.c. They are required in virt-acpi-build.c. So, make them
> public.
>
> Signed-off-by: Sunil V L
Reviewed-by: Alistair Francis
Alistair
> ---
> hw/riscv/virt.c |
On Tue, Jul 18, 2023 at 7:55 AM Daniel Henrique Barboza
wrote:
>
> zicntr is the Base Counters and Timers extension described in chapter 12
> of the unprivileged spec. It describes support for RDCYCLE, RDTIME and
> RDINSTRET.
>
> QEMU already implements it way before it was a discrete extension.
>
On Tue, Jul 18, 2023 at 7:55 AM Daniel Henrique Barboza
wrote:
>
> zihpm is the Hardware Performance Counters extension described in
> chapter 12 of the unprivileged spec. It describes support for 29
> unprivileged performance counters, hpmcounter3-hpmcounter21.
>
> As with zicntr, QEMU already im
Hi Connie,
On 7/18/23 21:14, Cornelia Huck wrote:
We can neaten the code by switching to the kvm_set_one_reg function.
Signed-off-by: Cornelia Huck
---
target/arm/kvm.c | 13 +++--
target/arm/kvm64.c | 66 +-
2 files changed, 21 insertions(
On 2023/07/20 11:20, Jason Wang wrote:
On Wed, Jul 19, 2023 at 9:59 AM Yui Washizu wrote:
This patch series is the first step towards enabling
hardware offloading of the L2 packet switching feature on virtio-net device to
host machine.
We are considering that this hardware offloading enables
Hi Connie,
On 7/18/23 21:14, Cornelia Huck wrote:
We can neaten the code by switching the callers that work on a
CPUstate to the kvm_get_one_reg function.
Signed-off-by: Cornelia Huck
---
target/arm/kvm.c | 15 +++-
target/arm/kvm64.c | 57 -
On Thu, Jul 20, 2023 at 12:35 PM Tomasz Jeznach wrote:
>
> Adding virt machine property 'iommu' to enable/disable IOMMU
> support, with platform RISC-V IOMMU device implementation.
>
> Generate device tree entry for riscv-iommu device, along with
> mapping all PCI device identifiers to the single
On Thu, Jul 20, 2023 at 11:26 PM Daniel Henrique Barboza
wrote:
>
> The cpu->cfg.epmp extension is still experimental, but it already has a
> 'smepmp' riscv,isa string. Add it.
>
> Signed-off-by: Daniel Henrique Barboza
Thanks!
Applied to riscv-to-apply.next
Alistair
> ---
> target/riscv/cpu
On Thu, Jul 20, 2023 at 11:25 PM Daniel Henrique Barboza
wrote:
>
> Hi,
>
> Found these 2 instances while working in more 8.2 material.
>
> I believe both are safe for freeze but I won't lose my sleep if we
> decide to postpone it.
I wasn't going to squeeze them into the freeze
>
> Daniel Henriq
On Fri, Jun 30, 2023 at 7:45 AM Palmer Dabbelt wrote:
>
> On Fri, 30 Jun 2023 04:14:09 PDT (-0700), rory.opensou...@gmail.com wrote:
> > RISCV architecture supports an optional big endian mode of operation.
> > In this mode, data accesses are treated as big endian, while code is
> > always in litt
On Fri, Jul 21, 2023 at 3:20 AM Daniel Henrique Barboza
wrote:
>
> We'll add a new CPU type that will enable a considerable amount of
> extensions. To make it easier for us we'll do a few cleanups in our
> existing riscv_cpu_extensions[] array.
>
> Start by splitting all CPU non-boolean options fr
On Tue, Jul 18, 2023 at 10:22 PM liguang.zhang <18622748...@163.com> wrote:
>
> From: "liguang.zhang"
>
> Fix the guest reboot error when using KVM
> There are two issues when rebooting a guest using KVM
> 1. When the guest initiates a reboot the host is unable to stop the vcpu
> 2. When running a
Hi there,
I guess removing this line would have been causing the problem. Can you
add this line back and test it?
diff --git a/ui/gtk-egl.c b/ui/gtk-egl.c
index eee821d73a..98b3a116bf 100644
--- a/ui/gtk-egl.c
+++ b/ui/gtk-egl.c
@@ -242,7 +242,6 @@ void gd_egl_scanout_texture(DisplayChangeList
Peter Maydell writes:
> On Fri, 21 Jul 2023 at 10:03, Philippe Mathieu-Daudé
> wrote:
>>
>> +Markus
>>
>> On 20/7/23 17:58, Peter Maydell wrote:
>> > This patchset was prompted by a couple of Coverity warnings
>> > (CID 1507157, 1517772) which note that in the m48t59 RTC device model
>> > we ke
> On Tue, Jul 18, 2023 at 10:22???PM liguang.zhang <18622748...@163.com> wrote:
> >
> > From: "liguang.zhang"
> >
> > Fix the guest reboot error when using KVM
> > There are two issues when rebooting a guest using KVM
> > 1. When the guest initiates a reboot the host is unable to stop the vcpu
> >
From: "liguang.zhang"
There are two issues when rebooting a guest using KVM
1. When the guest initiates a reboot the host is unable to stop the vcpu
2. When running a SMP guest the qemu monitor system_reset causes a vcpu crash
This can be fixed by clearing the CSR values at reset and syncing the
From: "liguang.zhang"
Fix the guest reboot error when using KVM
There are two issues when rebooting a guest using KVM
1. When the guest initiates a reboot the host is unable to stop the vcpu
2. When running a SMP guest the qemu monitor system_reset causes a vcpu crash
This can be fixed by cleari
On Mon, Jul 24, 2023 at 10:32 AM Yui Washizu wrote:
>
>
> On 2023/07/20 11:20, Jason Wang wrote:
> > On Wed, Jul 19, 2023 at 9:59 AM Yui Washizu wrote:
> >> This patch series is the first step towards enabling
> >> hardware offloading of the L2 packet switching feature on virtio-net
> >> device
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