[PATCH v3 3/3] Implement audio capture in virtio-snd device

Signed-off-by: Emmanouil Pitsidianakis --- hw/virtio/trace-events | 3 +- hw/virtio/virtio-snd.c | 238 +++-- 2 files changed, 205 insertions(+), 36 deletions(-) diff --git a/hw/virtio/trace-events b/hw/virtio/trace-events index 8f3953dc28..3e7b259aef 1006

[PATCH v3 1/3] Add virtio-sound device

This patch adds an audio device implementing the recent virtio sound spec (1.2). PCM functionality is implemented, and jack[0], chmaps[1] messages are at the moment left unimplemented. PS2: This patch was based on a draft patch posted by OpenSynergy in 2019. [2] [0]: https://www.kernel.org/doc

Re: [PATCH 4/6] linux-user: Fix signed math overflow in brk() syscall

On 7/18/23 00:02, Philippe Mathieu-Daudé wrote: On 17/7/23 23:35, Helge Deller wrote: Fix the math overflow when calculating the new_malloc_size. new_host_brk_page and brk_page are unsigned integers. If userspace reduces the heap, new_host_brk_page is lower than brk_page which results in a huge

[PATCH for-8.1] virtio-iommu: Standardize granule extraction and formatting

At several locations we compute the granule from the config page_size_mask using ctz() and then format it in traces using BIT(). As the page_size_mask is 64b we should use ctz64 and BIT_ULL() for formatting. We failed to be consistent. Note the page_size_mask is garanteed to be non null. The spec

Re: [PATCH v2 2/4] vhost-user: Interface for migration state transfer

On Wed, Jul 12, 2023 at 01:17:00PM +0200, Hanna Czenczek wrote: > Add the interface for transferring the back-end's state during migration > as defined previously in vhost-user.rst. > > Signed-off-by: Hanna Czenczek > --- > include/hw/virtio/vhost-backend.h | 24 + > include/hw/virtio/vhost

Re: [PATCH v2 3/4] vhost: Add high-level state save/load functions

On Wed, Jul 12, 2023 at 01:17:01PM +0200, Hanna Czenczek wrote: > vhost_save_backend_state() and vhost_load_backend_state() can be used by > vhost front-ends to easily save and load the back-end's state to/from > the migration stream. > > Because we do not know the full state size ahead of time, >

Re: [PATCH v2 4/4] vhost-user-fs: Implement internal migration

On Wed, Jul 12, 2023 at 01:17:02PM +0200, Hanna Czenczek wrote: > A virtio-fs device's VM state consists of: > - the virtio device (vring) state (VMSTATE_VIRTIO_DEVICE) > - the back-end's (virtiofsd's) internal state > > We get/set the latter via the new vhost operations to transfer migratory > st

Re: [PATCH for-8.2 v3 0/8] target/riscv: add 'max' CPU, deprecate

Alistair, I'm doing some overly complicated stuff here w.r.t to KVM specific code that are biting me back in further cleanups I'm working on. I'll do some changes in this series and re-send. Thanks, Daniel On 7/14/23 14:43, Daniel Henrique Barboza wrote: Hi, This version has changes suggest

[PATCH v2 5/5] linux-user: Fix qemu-arm to run static armhf binaries

qemu-user crashes immediately when running static binaries on the armhf architecture. The problem is the memory layout where the executable is loaded before the interpreter library, in which case the reserved brk region clashes with the interpreter code and is released before qemu tries to start th

[PATCH v2 1/5] linux-user: Fix qemu brk() to not zero bytes on current page

The qemu brk() implementation is too aggressive and cleans remaining bytes on the current page above the last brk address. But some existing applications are buggy and read/write bytes above their current heap address. On a phyiscal machine this does not trigger a runtime error as long as the acce

[PATCH v2 0/5] linux-user: brk() syscall fixes and armhf static binary fix

Commit 86f04735ac ("linux-user: Fix brk() to release pages") introduced the possibility for userspace applications to reduce memory footprint by calling brk() with a lower address and as such free up memory, the same way as the Linux kernel allows on physical machines. This change introduced some

[PATCH v2 2/5] linux-user: Prohibit brk() to to shrink below initial heap address

Since commit 86f04735ac ("linux-user: Fix brk() to release pages") it's possible for userspace applications to reduce their memory footprint by calling brk() with a lower address and free up memory. Before that commit guest heap memory was never unmapped. But the Linux kernel prohibits to reduce b

[PATCH v2 3/5] linux-user: Fix signed math overflow in brk() syscall

Fix the math overflow when calculating the new_malloc_size. new_host_brk_page and brk_page are unsigned integers. If userspace reduces the heap, new_host_brk_page is lower than brk_page which results in a huge positive number (but should actually be negative). Fix it by adding a proper check and

[PATCH v2 4/5] linux-user: Fix strace output for old_mmap

The old_mmap syscall (e.g. on i386) hands over the parameters in a struct. Adjust the strace output to print the correct values. Signed-off-by: Helge Deller Reported-by: John Reiser Closes: https://gitlab.com/qemu-project/qemu/-/issues/1760 --- linux-user/strace.c | 49 +

Re: PING: [PATCH v4 0/3] hw/ufs: Add Universal Flash Storage (UFS) support

On Tue, Jul 11, 2023 at 07:31:02PM +0900, Jeuk Kim wrote: > Hi, > Any more reviews...? > > Dear Stefan > If you don't mind, Could you give it "reviewed-by"? > And is there anything else I should do...? Sorry for the late reply. I was on vacation and am working my way through pending code review a

Re: [PATCH 04/10] hw/riscv: virt: Add PCIe HIGHMEM in memmap

On 7/12/23 13:39, Sunil V L wrote: PCIe High MMIO base is actually dynamic and fixed at run time based on the RAM configured. Currently, this is not part of the memmap and kept in separate static variable in virt.c. However, ACPI code also needs this information to populate DSDT. So, once the

Re: [PATCH 05/10] hw/riscv/virt-acpi-build.c: Add AIA support in RINTC

On 7/12/23 13:39, Sunil V L wrote: Update the RINTC structure in MADT with AIA related fields. Signed-off-by: Sunil V L --- Reviewed-by: Daniel Henrique Barboza hw/riscv/virt-acpi-build.c | 66 +++--- 1 file changed, 62 insertions(+), 4 deletions(-) d

Re: [PATCH 06/10] hw/riscv/virt-acpi-build.c: Add IMSIC in the MADT

On 7/12/23 13:39, Sunil V L wrote: Add IMSIC structure in MADT when IMSIC is configured. Signed-off-by: Sunil V L --- Reviewed-by: Daniel Henrique Barboza hw/riscv/virt-acpi-build.c | 34 ++ 1 file changed, 34 insertions(+) diff --git a/hw/riscv/virt-

Re: [PATCH 07/10] hw/riscv/virt-acpi-build.c: Add APLIC in the MADT

On 7/12/23 13:39, Sunil V L wrote: Add APLIC structures for each socket in the MADT when system is configured with APLIC as the external wired interrupt controller. Signed-off-by: Sunil V L --- Reviewed-by: Daniel Henrique Barboza hw/riscv/virt-acpi-build.c | 36 ++

Re: [PATCH 08/10] hw/riscv/virt-acpi-build.c: Add CMO information in RHCT

On 7/12/23 13:39, Sunil V L wrote: When CMO related extensions like Zicboz, Zicbom and Zicbop are enabled, the block size for those extensions need to be communicated via CMO node in RHCT. Add CMO node in RHCT if any of those CMO extensions are detected. Signed-off-by: Sunil V L --- Review

Re: [PATCH 09/10] hw/riscv/virt-acpi-build.c: Add MMU node in RHCT

On 7/12/23 13:39, Sunil V L wrote: MMU type information is available via MMU node in RHCT. Add this node in RHCT. Signed-off-by: Sunil V L --- Reviewed-by: Daniel Henrique Barboza hw/riscv/virt-acpi-build.c | 36 1 file changed, 36 insertions(+)

Re: [PATCH 10/10] hw/riscv/virt-acpi-build.c: Add IO controllers and devices

On 7/12/23 13:39, Sunil V L wrote: Add basic IO controllers and devices like PCI, VirtIO and UART in the ACPI namespace. Signed-off-by: Sunil V L --- Reviewed-by: Daniel Henrique Barboza hw/riscv/Kconfig | 1 + hw/riscv/virt-acpi-build.c | 87 ++

Re: [PATCH v4 1/3] hw/ufs: Initial commit for emulated Universal-Flash-Storage

On Tue, Jul 04, 2023 at 05:33:57PM +0900, Jeuk Kim wrote: > From: Jeuk Kim > > Universal Flash Storage (UFS) is a high-performance mass storage device > with a serial interface. It is primarily used as a high-performance > data storage device for embedded applications. > > This commit contains c

Re: [PATCH v4 2/3] hw/ufs: Support for Query Transfer Requests

On Tue, Jul 04, 2023 at 05:33:58PM +0900, Jeuk Kim wrote: > +static MemTxResult ufs_dma_read_prdt(UfsRequest *req) > +{ > +UfsHc *u = req->hc; > +uint16_t prdt_len = le16_to_cpu(req->utrd.prd_table_length); > +uint16_t prdt_byte_off = > +le16_to_cpu(req->utrd.prd_table_offset) *

Re: [PATCH v4 3/3] hw/ufs: Support for UFS logical unit

On Tue, Jul 04, 2023 at 05:33:59PM +0900, Jeuk Kim wrote: > +static Property ufs_lu_props[] = { > +DEFINE_PROP_DRIVE_IOTHREAD("drive", UfsLu, qdev.conf.blk), This device is not aware of IOThreads, so I think DEFINE_PROP_DRIVE() should be used instead. signature.asc Description: PGP signature

[PATCH for-8.2 v4 00/11] riscv: add 'max' CPU, deprecate 'any'

Hi, This new version has some adjustments w.r.t the KVM code that got a bit neglected in the last 3 versions. The most notable change is in patch 3, a new patch where we're moving the KVM property handling into an exclusive helper. This helped to unclog riscv_cpu_add_user_properties() a lot, makin

[PATCH for-8.2 v4 01/11] target/riscv/cpu.c: split CPU options from riscv_cpu_extensions[]

We'll add a new CPU type that will enable a considerable amount of extensions. To make it easier for us we'll do a few cleanups in our existing riscv_cpu_extensions[] array. Start by splitting all CPU non-boolean options from it. Create a new riscv_cpu_options[] array for them. Add all these prope

[PATCH for-8.2 v4 10/11] avocado, risc-v: add opensbi tests for 'max' CPU

Add smoke tests to ensure that we'll not break the 'max' CPU type when adding new ratified extensions to be enabled. Signed-off-by: Daniel Henrique Barboza --- tests/avocado/riscv_opensbi.py | 16 1 file changed, 16 insertions(+) diff --git a/tests/avocado/riscv_opensbi.py b/te

[PATCH for-8.2 v4 05/11] target/riscv/cpu.c: split vendor exts from riscv_cpu_extensions[]

Our goal is to make riscv_cpu_extensions[] hold only ratified, non-vendor extensions. Create a new riscv_cpu_vendor_exts[] array for them, changing riscv_cpu_add_user_properties() and riscv_cpu_add_kvm_properties() accordingly. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis

[PATCH for-8.2 v4 09/11] target/riscv: add 'max' CPU type

The 'max' CPU type is used by tooling to determine what's the most capable CPU a current QEMU version implements. Other archs such as ARM implements this type. Let's add it to RISC-V. What we consider "most capable CPU" in this context are related to ratified, non-vendor extensions. This means tha

[PATCH for-8.2 v4 04/11] target/riscv/cpu.c: del DEFINE_PROP_END_OF_LIST() from riscv_cpu_extensions

This last blank element is used by the 'for' loop to check if a property has a valid name. Remove it and use ARRAY_SIZE() instead like riscv_cpu_options is already using. All future arrays will also do the same and we'll able to encapsulate more repetitions in macros later on. Signed-off-by: Dani

[PATCH for-8.2 v4 07/11] target/riscv/cpu.c: add ADD_CPU_QDEV_PROPERTIES_ARRAY() macro

The code inside riscv_cpu_add_user_properties() became quite repetitive after recent changes. Add a macro to hide the repetition away. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Weiwei Li --- target/riscv/cpu.c | 26 +++--- 1 file changed, 11 insertions(+), 15 delet

[PATCH for-8.2 v4 02/11] target/riscv/cpu.c: skip 'bool' check when filtering KVM props

After the introduction of riscv_cpu_options[] all properties in riscv_cpu_extensions[] are booleans. This check is now obsolete. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 14 -- 1 file changed, 4 insertions(+), 10 deletions(-) dif

[PATCH for-8.2 v4 11/11] target/riscv: deprecate the 'any' CPU type

The 'any' CPU type was introduced in commit dc5bd18fa5725 ("RISC-V CPU Core Definition"), being around since the beginning. It's not an easy CPU to use: it's undocumented and its name doesn't tell users much about what the CPU is supposed to bring. 'git log' doesn't help us either in knowing what w

[PATCH for-8.2 v4 06/11] target/riscv/cpu.c: split non-ratified exts from riscv_cpu_extensions[]

Create a new riscv_cpu_experimental_exts[] to store the non-ratified extensions properties. Once they are ratified we'll move them back to riscv_cpu_extensions[]. riscv_cpu_add_user_properties() and riscv_cpu_add_kvm_properties() are changed to keep adding non-ratified properties to users. Signed

[PATCH for-8.2 v4 03/11] target/riscv/cpu.c: split kvm prop handling to its own helper

Future patches will split the existing Property arrays even further, and the existing code in riscv_cpu_add_user_properties() will start to scale bad with it because it's dealing with KVM constraints mixed in with TCG constraints. We're going to pay a high price to share a couple of common lines of

[PATCH for-8.2 v4 08/11] target/riscv/cpu.c: add ADD_UNAVAIL_KVM_PROP_ARRAY() macro

Use a macro in riscv_cpu_add_kvm_properties() to eliminate some of its code repetition, similar to what we're already doing with ADD_CPU_QDEV_PROPERTIES_ARRAY(). Signed-off-by: Daniel Henrique Barboza --- target/riscv/cpu.c | 22 ++ 1 file changed, 10 insertions(+), 12 deleti

[PATCH 07/14] target/s390x: Fix assertion failure in VFMIN/VFMAX with reserved type

Passing reserved type to VFMIN/VFMAX causes an assertion failure in vfmin_res() and vfmax_res(). These instructions should raise a specification exception in this case. Cc: qemu-sta...@nongnu.org Fixes: da4807527f3b ("s390x/tcg: Implement VECTOR FP (MAXIMUM|MINIMUM)") Signed-off-by: Ilya Leoshkevi

[PATCH 09/14] tests/tcg/s390x: Test CLGEBR and CGEBRA

Add a small test to prevent regressions. Signed-off-by: Ilya Leoshkevich --- tests/tcg/s390x/Makefile.target | 5 + tests/tcg/s390x/cgebra.c| 32 tests/tcg/s390x/clgebr.c| 32 3 files changed, 69 insertions(+)

[PATCH 00/14] target/s390x: Miscellaneous TCG fixes, part 2

Hi, Here is another set of fixes for issues found by randomized testing. Most of them have to do with simple insufficient error handling or corner cases, but 3/14 and 6/14 took a while to figure out, and hopefully I got the fixes right. 13/14 is a test for an issue that Richard has already fixed,

[PATCH 08/14] tests/tcg/s390x: Test CKSM

Add a small test to prevent regressions. Signed-off-by: Ilya Leoshkevich --- tests/tcg/s390x/Makefile.softmmu-target | 1 + tests/tcg/s390x/cksm.S | 29 + 2 files changed, 30 insertions(+) create mode 100644 tests/tcg/s390x/cksm.S diff --git a/tests/tc

[PATCH 12/14] tests/tcg/s390x: Test MC

Add a small test to prevent regressions. Signed-off-by: Ilya Leoshkevich --- tests/tcg/s390x/Makefile.softmmu-target | 1 + tests/tcg/s390x/mc.S| 56 + 2 files changed, 57 insertions(+) create mode 100644 tests/tcg/s390x/mc.S diff --git a/tests/tcg/

[PATCH 06/14] tcg/{i386, s390x}: Add earlyclobber to the op_add2's first output

i386 and s390x implementations of op_add2 require an earlyclobber, which is currently missing. This breaks VCKSM in s390x guests. E.g., on x86_64 the following op: add2_i32 tmp2,tmp3,tmp2,tmp3,tmp3,tmp2 dead: 0 2 3 4 5 pref=none,0x is translated to: addl %ebx, %r12d adcl

[PATCH 11/14] tests/tcg/s390x: Test ICM

Add a small test to prevent regressions. Signed-off-by: Ilya Leoshkevich --- tests/tcg/s390x/Makefile.softmmu-target | 1 + tests/tcg/s390x/icm.S | 32 + 2 files changed, 33 insertions(+) create mode 100644 tests/tcg/s390x/icm.S diff --git a/tests/tcg

[PATCH 05/14] target/s390x: Make MC raise specification exception when class >= 16

MC requires bit positions 8-11 (upper 4 bits of class) to be zeros, otherwise it must raise a specification exception. Cc: qemu-sta...@nongnu.org Fixes: 20d143e2cab8 ("s390x/tcg: Implement MONITOR CALL") Signed-off-by: Ilya Leoshkevich --- target/s390x/tcg/excp_helper.c | 2 +- target/s390x/tcg/

[PATCH 03/14] target/s390x: Fix CONVERT TO LOGICAL/FIXED with out-of-range inputs

CONVERT TO LOGICAL/FIXED deviate from IEEE 754 in that they raise an inexact exception on out-of-range inputs. float_flag_invalid_cvti aligns nicely with that behavior, so convert it to S390_IEEE_MASK_INEXACT. Cc: qemu-sta...@nongnu.org Fixes: defb0e3157af ("s390x: Implement opcode helpers") Signe

[PATCH 04/14] target/s390x: Fix ICM with M3=0

When the mask is zero, access exceptions should still be recognized for 1 byte at the second-operand address. CC should be set to 0. Cc: qemu-sta...@nongnu.org Fixes: e023e832d0ac ("s390x: translate engine for s390x CPU") Signed-off-by: Ilya Leoshkevich --- target/s390x/tcg/translate.c | 6 +

[PATCH 14/14] tests/tcg/s390x: Test VCKSM

Add a small test to prevent regressions. Signed-off-by: Ilya Leoshkevich --- tests/tcg/s390x/Makefile.target | 1 + tests/tcg/s390x/vcksm.c | 31 +++ tests/tcg/s390x/vx.h| 2 ++ 3 files changed, 34 insertions(+) create mode 100644 tests/tcg/s390

[PATCH 10/14] tests/tcg/s390x: Test CLM

Add a small test to prevent regressions. Signed-off-by: Ilya Leoshkevich --- tests/tcg/s390x/Makefile.softmmu-target | 1 + tests/tcg/s390x/clm.S | 29 + 2 files changed, 30 insertions(+) create mode 100644 tests/tcg/s390x/clm.S diff --git a/tests/tcg

[PATCH 02/14] target/s390x: Fix CLM with M3=0

When the mask is zero, access exceptions should still be recognized for 1 byte at the second-operand address. CC should be set to 0. Cc: qemu-sta...@nongnu.org Fixes: defb0e3157af ("s390x: Implement opcode helpers") Signed-off-by: Ilya Leoshkevich --- target/s390x/tcg/mem_helper.c | 5 + 1 f

[PATCH 01/14] target/s390x: Make CKSM raise an exception if R2 is odd

R2 designates an even-odd register pair; the instruction should raise a specification exception when R2 is not even. Cc: qemu-sta...@nongnu.org Fixes: e023e832d0ac ("s390x: translate engine for s390x CPU") Signed-off-by: Ilya Leoshkevich --- target/s390x/tcg/translate.c | 11 +-- 1 file

Re: [RFC PATCH 10/17] misc/i2c_mctp_cxl: Initial device emulation

On Mon, Jul 17, 2023 at 06:16:39PM +0100, Jonathan Cameron wrote: > @@ -397,8 +401,9 @@ struct CXLType3Dev { > AddressSpace hostpmem_as; > CXLComponentState cxl_cstate; > CXLDeviceState cxl_dstate; > -CXLCCI cci; > - > +CXLCCI cci; /* Primary PCI mailbox CCI */ > +CXL

[PATCH 13/14] tests/tcg/s390x: Test STPQ

Add a small test to prevent regressions. Signed-off-by: Ilya Leoshkevich --- tests/tcg/s390x/Makefile.softmmu-target | 1 + tests/tcg/s390x/stpq.S | 20 2 files changed, 21 insertions(+) create mode 100644 tests/tcg/s390x/stpq.S diff --git a/tests/tcg/s39

Re: [PATCH v2] plugins: Set final instruction count in plugin_gen_tb_end

Matt Borgerson writes: > Thanks Alex! > > > On Mon, Jul 17, 2023 at 8:34 AM Alex Bennée wrote: >> >> >> Alex Bennée writes: >> >> > Matt Borgerson writes: >> > >> >> Translation logic may partially decode an instruction, then abort and >> >> remove the instruction from the TB. This can happe

Re: PING: [PATCH v4 0/3] hw/ufs: Add Universal Flash Storage (UFS) support

On 2023-07-19 오전 3:56, Stefan Hajnoczi wrote: On Tue, Jul 11, 2023 at 07:31:02PM +0900, Jeuk Kim wrote: Hi, Any more reviews...? Dear Stefan If you don't mind, Could you give it "reviewed-by"? And is there anything else I should do...? Sorry for the late reply. I was on vacation and am workin

Re: [PATCH qemu 2/2] dump: Only use the makedumpfile flattened format when necessary

Marc-André Lureau writes: > Hi > > On Mon, Jul 17, 2023 at 8:45 PM Stephen Brennan < > stephen.s.bren...@oracle.com> wrote: > >> The flattened format is used by makedumpfile only when it is outputting >> a vmcore to a file which is not seekable. The flattened format functions >> essentially as a s

[PATCH 2/3] ppc/pegasos2: Fix reg property of ROM BARs

The register offset of the ROM BAR is 0x30 not 0x28. This fixes the reg property entry of the ROM region in the device tree. Signed-off-by: BALATON Zoltan --- hw/ppc/pegasos2.c | 6 +- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/hw/ppc/pegasos2.c b/hw/ppc/pegasos2.c index 4a

[PATCH 3/3] ppc/pegasos2: Fix naming of device tree nodes

The board firmware names devices by their class so match that for common devices. Also make sure the /rtas node has a name. This is needed because VOF otherwise does not include it in results got by nextprop which is how AmigaOS queries it and fails if no name property is found. Signed-off-by: BAL

[PATCH 0/3] pegasos2 fixes for 8.1

These are some small fixes when using pegasos2 with the QEMU built in VOF instead of the non-free board firmware that fix bugs in the generated device tree and matches the board firmware in the reset state of on-board USB devices. This fixes booting AmigaOS with VOF and only touches parts that are

[PATCH 1/3] ppc/pegasos2: Fix reset state of USB functions

The original non-free board firmware sets the command register of the USB functions to 7 and some guests rely on this for working USB. Match what the board firmware does when using VOF instead. Signed-off-by: BALATON Zoltan --- hw/ppc/pegasos2.c | 4 1 file changed, 4 insertions(+) diff --

Re: [PATCH v8 01/15] target/riscv: Refactor some of the generic vector functionality

On Wed, Jul 12, 2023 at 2:59 AM Max Chou wrote: > > From: Kiran Ostrolenk > > Take some functions/macros out of `vector_helper` and put them in a new > module called `vector_internals`. This ensures they can be used by both > vector and vector-crypto helpers (latter implemented in proceeding > co

Re: [PATCH v2 08/16] target/riscv: Move TCG-specific cpu_get_tb_cpu_state() to tcg/cpu.c

On Tue, Jul 4, 2023 at 4:34 AM Philippe Mathieu-Daudé wrote: > > Signed-off-by: Philippe Mathieu-Daudé Acked-by: Alistair Francis Alistair > --- > target/riscv/cpu_helper.c| 84 --- > target/riscv/tcg/cpu.c | 98 > ta

Re: [PATCH v3 07/16] target/riscv: Move TCG-specific files to target/riscv/tcg/

On Tue, Jul 11, 2023 at 10:21 PM Philippe Mathieu-Daudé wrote: > > Move TCG-specific files to the a new 'tcg' sub-directory. Add > stubs for riscv_cpu_[get/set]_fflags and riscv_raise_exception(). > Adapt meson rules. > > Signed-off-by: Philippe Mathieu-Daudé Acked-by: Alistair Francis Alistai

Re: [PATCH v3 08/16] target/riscv: Move TCG-specific cpu_get_tb_cpu_state() to tcg/cpu.c

On Tue, Jul 11, 2023 at 10:18 PM Philippe Mathieu-Daudé wrote: > > Signed-off-by: Philippe Mathieu-Daudé Acked-by: Alistair Francis Alistair > --- > target/riscv/cpu_helper.c| 84 --- > target/riscv/tcg/cpu.c | 98 >

Re: [PATCH v3 09/16] target/riscv: Expose some 'trigger' prototypes from debug.c

On Tue, Jul 11, 2023 at 10:16 PM Philippe Mathieu-Daudé wrote: > > We want to extract TCG-specific code from debug.c, but some > functions call get_trigger_type() / do_trigger_action(). > Expose these prototypes in "debug.h". > > Signed-off-by: Philippe Mathieu-Daudé Acked-by: Alistair Francis

Re: [PATCH for-8.0] tcg/sparc64: Disable direct linking for goto_tb

On 5/4/23 1:04 am, Richard Henderson wrote: Something is wrong with this code, and also wrong with gdb on the sparc systems to which I have access, so I cannot debug it either. Disable for now, so the release is not broken. I'm not sure if it is the entire problem but it looks like the broke

Re: [PATCH v3 10/16] target/riscv: Extract TCG-specific code from debug.c

On Tue, Jul 11, 2023 at 10:21 PM Philippe Mathieu-Daudé wrote: > > Extract TCG-specific code from debug.c to tcg/sysemu/debug.c, > restrict the prototypes to TCG, adapt meson rules. > > Signed-off-by: Philippe Mathieu-Daudé Acked-by: Alistair Francis Alistair > --- > target/riscv/debug.h

Re: [PATCH v3 11/16] target/riscv: Move sysemu-specific debug files to target/riscv/sysemu/

On Tue, Jul 11, 2023 at 10:22 PM Philippe Mathieu-Daudé wrote: > > Signed-off-by: Philippe Mathieu-Daudé Acked-by: Alistair Francis Alistair > --- > target/riscv/cpu.h| 2 +- > target/riscv/{ => sysemu}/debug.h | 0 > target/riscv/cpu_helper.c | 2 +- > target/riscv/{

Re: [PATCH v3 12/16] target/riscv: Expose riscv_cpu_pending_to_irq() from cpu_helper.c

On Tue, Jul 11, 2023 at 10:22 PM Philippe Mathieu-Daudé wrote: > > We want to extract TCG/sysemu-specific code from cpu_helper.c, > but some functions call riscv_cpu_pending_to_irq(). Expose the > prototype in "internals.h". > > Signed-off-by: Philippe Mathieu-Daudé Acked-by: Alistair Francis

Re: [PATCH] target/riscv/cpu.c: check priv_ver before auto-enable zca/zcd/zcf

On Tue, Jul 18, 2023 at 1:42 AM Daniel Henrique Barboza wrote: > > Commit bd30559568 made changes in how we're checking and disabling > extensions based on env->priv_ver. One of the changes was to move the > extension disablement code to the end of realize(), being able to > disable extensions aft

Re: Tips for local testing guestfwd

Hi all, I am continuing debugging the ipv6 guestfwd feature, and I would like to understand the behavior of slirp better. Progress I've made: Let QEMU take parameter like following: guestfwd=tcp:[fec0::105]:54322-tcp:[::1]:6655 For slirp side, I basically searched for the appearance of gfwd_list

Re: [PATCH] target/riscv/cpu.c: check priv_ver before auto-enable zca/zcd/zcf

On Tue, Jul 18, 2023 at 7:50 PM Daniel Henrique Barboza wrote: > > > > On 7/17/23 22:36, LIU Zhiwei wrote: > > > > On 2023/7/17 23:41, Daniel Henrique Barboza wrote: > >> Commit bd30559568 made changes in how we're checking and disabling > >> extensions based on env->priv_ver. One of the changes w

Re: [PATCH] target/riscv/cpu.c: check priv_ver before auto-enable zca/zcd/zcf

On Tue, Jul 18, 2023 at 1:42 AM Daniel Henrique Barboza wrote: > > Commit bd30559568 made changes in how we're checking and disabling > extensions based on env->priv_ver. One of the changes was to move the > extension disablement code to the end of realize(), being able to > disable extensions aft

Re: [PATCH] hw/riscv: Fix topo field in error_report

On Tue, Jul 18, 2023 at 5:57 PM Zhao Liu wrote: > > From: Zhao Liu > > "smp.cpus" means the number of online CPUs and "smp.max_cpus" means the > total number of CPUs. > > riscv_numa_get_default_cpu_node_id() checks "smp.cpus" and the > "available CPUs" description in the next error message also i

Re: [PATCH v2] target/riscv: Fix LMUL check to use VLEN

On 2023/7/18 21:11, Rob Bradford wrote: The previous check was failing with: VLEN=128 ELEN = 64 SEW = 16 and LMUL = 1/8 which is a valid combination. Fix the check to allow valid combinations when VLEN is a multiple of ELEN. From the specification: "In general, the requirement is to suppor

Re: [PATCH 1/3] target/riscv: Add cycle & instret privilege mode filtering properties

On 2023/7/19 06:47, Kaiwen Xue wrote: This adds the properties for ISA extension smcntrpmf. Patches implementing it will follow. Signed-off-by: Kaiwen Xue Signed-off-by: Kaiwen Xue --- target/riscv/cpu.c | 2 ++ target/riscv/cpu_cfg.h | 1 + 2 files changed, 3 insertions(+) diff --g

Re: [PATCH] hw/riscv: Fix topo field in error_report

On Tue, Jul 18, 2023 at 5:57 PM Zhao Liu wrote: > > From: Zhao Liu > > "smp.cpus" means the number of online CPUs and "smp.max_cpus" means the > total number of CPUs. > > riscv_numa_get_default_cpu_node_id() checks "smp.cpus" and the > "available CPUs" description in the next error message also i

[PATCH 2/3] target/riscv: Add cycle & instret privilege mode filtering definitions

This adds the definitions for ISA extension smcntrpmf. Signed-off-by: Kaiwen Xue Signed-off-by: Kaiwen Xue --- target/riscv/cpu.h | 6 ++ target/riscv/cpu_bits.h | 29 + 2 files changed, 35 insertions(+) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h

[PATCH 3/3] target/riscv: Add cycle & instret privilege mode filtering support

QEMU only calculates dummy cycles and instructions, so there is no actual means to stop the icount in QEMU. Hence this patch merely adds the functionality of accessing the cfg registers, and cause no actual effects on the counting of cycle and instret counters. Signed-off-by: Kaiwen Xue Signed-of

[PATCH 1/3] target/riscv: Add cycle & instret privilege mode filtering properties

This adds the properties for ISA extension smcntrpmf. Patches implementing it will follow. Signed-off-by: Kaiwen Xue Signed-off-by: Kaiwen Xue --- target/riscv/cpu.c | 2 ++ target/riscv/cpu_cfg.h | 1 + 2 files changed, 3 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c

[PATCH 0/3] risc-v: Add ISA extension smcntrpmf support

This patch series adds the support for RISC-V ISA extension smcntrpmf (cycle and privilege mode filtering) [1]. QEMU only calculates dummy cycles and instructions, so there is no actual means to stop the icount in QEMU. Therefore, this series only add the read/write behavior of the relevant CSRs su

Re: [PATCH 3/3] target/riscv: Add cycle & instret privilege mode filtering support

On 2023/7/19 06:47, Kaiwen Xue wrote: QEMU only calculates dummy cycles and instructions, so there is no actual means to stop the icount in QEMU. Hence this patch merely adds the functionality of accessing the cfg registers, and cause no actual effects on the counting of cycle and instret count

Re: Boot failure after QEMU's upgrade to OpenSBI v1.3 (was Re: [PATCH for-8.2 6/7] target/riscv: add 'max' CPU type)

On Sat, Jul 15, 2023 at 7:14 PM Atish Patra wrote: > > On Fri, Jul 14, 2023 at 5:29 AM Conor Dooley wrote: > > > > On Fri, Jul 14, 2023 at 11:19:34AM +0100, Conor Dooley wrote: > > > On Fri, Jul 14, 2023 at 10:00:19AM +0530, Anup Patel wrote: > > > > > > > > > OpenSBI v1.3 > > > > > >

Re: [PATCH v2] target/riscv: Fix LMUL check to use VLEN

On Tue, Jul 18, 2023 at 11:14 PM Rob Bradford wrote: > > The previous check was failing with: > > VLEN=128 ELEN = 64 SEW = 16 and LMUL = 1/8 which is a > valid combination. > > Fix the check to allow valid combinations when VLEN is a multiple of > ELEN. > > From the specification: > > "In general,

Re: [PATCH] vhost: disable VHOST_OPS_DEBUG by default

On 7/17/2023 6:14 PM, Philippe Mathieu-Daudé wrote: Hi, On 17/7/23 19:44, Zhu Lingshan wrote: This commit disables VHOST_OPS_DEBUG by default These information are ususally only required in development environment Signed-off-by: Zhu Lingshan ---   hw/virtio/vhost.c | 7 ++-   1 file cha

[PATCH v5 0/3] hw/ufs: Add Universal Flash Storage (UFS) support

Since v4: Addressed review comment from Stefan Hajnoczi. The fixes are as follows. - Keep u->reg fields in host endian (Removed little-endian helper functions from MemoryRegionOps) - Remove unnecessary NULL checks for g_new and g_malloc0 - Replace DEFINE_PROP_DRIVE_IOTHREAD -> DEFINE_PROP_DRIVE

[PATCH v5 2/3] hw/ufs: Support for Query Transfer Requests

From: Jeuk Kim This commit makes the UFS device support query and nop out transfer requests. The next patch would be support for UFS logical unit and scsi command transfer request. Signed-off-by: Jeuk Kim --- hw/ufs/trace-events | 1 + hw/ufs/ufs.c| 980 +

[PATCH v5 1/3] hw/ufs: Initial commit for emulated Universal-Flash-Storage

From: Jeuk Kim Universal Flash Storage (UFS) is a high-performance mass storage device with a serial interface. It is primarily used as a high-performance data storage device for embedded applications. This commit contains code for UFS device to be recognized as a UFS PCI device. Patches to hand

[PATCH v5 3/3] hw/ufs: Support for UFS logical unit

From: Jeuk Kim This commit adds support for ufs logical unit. The LU handles processing for the SCSI command, unit descriptor query request. This commit enables the UFS device to process IO requests. Signed-off-by: Jeuk Kim --- hw/ufs/lu.c | 1439 +

Re: [PATCH 04/10] hw/riscv: virt: Add PCIe HIGHMEM in memmap

On Tue, Jul 18, 2023 at 05:05:12PM -0300, Daniel Henrique Barboza wrote: > > > On 7/12/23 13:39, Sunil V L wrote: > > PCIe High MMIO base is actually dynamic and fixed at > > run time based on the RAM configured. Currently, this is > > not part of the memmap and kept in separate static variable >

Re: [PATCH QEMU v8 4/9] migration: Introduce dirty-limit capability

On Tue, Jul 18, 2023 at 7:04 PM Markus Armbruster wrote: > Yong Huang writes: > > > On Thu, Jul 13, 2023 at 8:44 PM Markus Armbruster > wrote: > > > >> ~hyman writes: > >> > >> > From: Hyman Huang(黄勇) > >> > > >> > Introduce migration dirty-limit capability, which can > >> > be turned on befo

[PULL 2/5] riscv/disas: Fix disas output of upper immediates

From: Christoph Müllner The GNU assembler produces the following output for instructions with upper immediates: 2597auipc a1,0x2 24b7lui s1,0x2 6409lui s0,0x2 # c.lui The immediate operands of upper immediates are

[PULL 0/5] riscv-to-apply queue

The following changes since commit 361d5397355276e3007825cc17217c1e4d4320f7: Merge tag 'block-pull-request' of https://gitlab.com/stefanha/qemu into staging (2023-07-17 15:49:27 +0100) are available in the Git repository at: https://github.com/alistair23/qemu.git tags/pull-riscv-to-apply-20

[PULL 4/5] hw/riscv: Fix typo field in error_report

From: Zhao Liu "smp.cpus" means the number of online CPUs and "smp.max_cpus" means the total number of CPUs. riscv_numa_get_default_cpu_node_id() checks "smp.cpus" and the "available CPUs" description in the next error message also indicates online CPUs. So report "smp.cpus" in error_report() i

[PULL 5/5] target/riscv: Fix LMUL check to use VLEN

From: Rob Bradford The previous check was failing with: VLEN=128 ELEN = 64 SEW = 16 and LMUL = 1/8 which is a valid combination. Fix the check to allow valid combinations when VLEN is a multiple of ELEN. >From the specification: "In general, the requirement is to support LMUL ≥ SEWMIN/ELEN, w

[PULL 1/5] docs/system/target-riscv.rst: tidy CPU firmware section

From: Daniel Henrique Barboza This is how the content of the "RISC-V CPU firmware" section is displayed after the html is generated: "When using the sifive_u or virt machine there are three different firmware boot options: 1. -bios default - This is the default behaviour if no -bios option is in

[PULL 3/5] target/riscv/cpu.c: check priv_ver before auto-enable zca/zcd/zcf

From: Daniel Henrique Barboza Commit bd30559568 made changes in how we're checking and disabling extensions based on env->priv_ver. One of the changes was to move the extension disablement code to the end of realize(), being able to disable extensions after we've auto-enabled some of them. An un

Re: [PATCH QEMU v8 4/9] migration: Introduce dirty-limit capability

Yong Huang writes: > On Tue, Jul 18, 2023 at 7:04 PM Markus Armbruster wrote: > >> Yong Huang writes: >> >> > On Thu, Jul 13, 2023 at 8:44 PM Markus Armbruster >> wrote: >> > >> >> ~hyman writes: >> >> >> >> > From: Hyman Huang(黄勇) >> >> > >> >> > Introduce migration dirty-limit capability,

[PATCH] ppc: Add stub implementation of TRIG SPRs

Linux sets these to control cache flush behaviour on Power9. Supervisor and hypervisor are allowed to write, and reads are noops. Add implementations to avoid noisy messages when booting Linux under the pseries machine with guest_errors enabled. Reviewed-by: Nicholas Piggin Signed-off-by: Joel S

Re: Boot failure after QEMU's upgrade to OpenSBI v1.3 (was Re: [PATCH for-8.2 6/7] target/riscv: add 'max' CPU type)

On Wed, Jul 19, 2023 at 7:03 AM Alistair Francis wrote: > > On Sat, Jul 15, 2023 at 7:14 PM Atish Patra wrote: > > > > On Fri, Jul 14, 2023 at 5:29 AM Conor Dooley wrote: > > > > > > On Fri, Jul 14, 2023 at 11:19:34AM +0100, Conor Dooley wrote: > > > > On Fri, Jul 14, 2023 at 10:00:19AM +0530, A

  1   2   3   >