On 7/10/23 18:50, Philippe Mathieu-Daudé wrote:
+if (s->read_count == s->read_trigger - 1)
+s->int_level &= ~ INT_RX;
Fix the braces. Otherwise,
Reviewed-by: Richard Henderson
r~
On 7/10/23 18:50, Philippe Mathieu-Daudé wrote:
We shouldn't transmit characters when the full UART or its
transmitter is disabled. However we don't want to break the
possibly incomplete "my first bare metal assembly program"s,
so we choose to simply display a warning when this occurs.
Signed-of
On 7/10/23 18:51, Philippe Mathieu-Daudé wrote:
Do not receive characters when UART or receiver are disabled.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/char/pl011.c | 7 +--
1 file changed, 5 insertions(+), 2 deletions(-)
I guess this doesn't fall under "my first assembly program" be
On 7/10/23 18:51, Philippe Mathieu-Daudé wrote:
In preparation of having a TX FIFO, rename the RX FIFO methods.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Alex Bennée
---
hw/char/pl011.c | 10 +-
hw/char/trace-events | 4 ++--
2 files changed, 7 insertions(+), 7 deletio
The impetus for this patch set is to get TPM 2.0 working on Windows 11 ARM64.
Windows' tpm.sys does not seem to work on a TPM TIS device (as verified with
VMWare's implementation). However, the current TPM CRB device uses a fixed
system bus address that is reserved for RAM in ARM64 Virt machines.
In preparation for the SysBus variant, we move common code styled
after the TPM TIS devices.
To maintain compatibility, we do not rename the existing tpm-crb
device.
Signed-off-by: Joelle van Dyne
Reviewed-by: Stefan Berger
---
docs/specs/tpm.rst | 1 +
hw/tpm/tpm_crb.h| 76 +++
This logic is similar to TPM TIS ISA device. Since TPM CRB can only
support TPM 2.0 backends, we check for this in realize.
Signed-off-by: Joelle van Dyne
---
hw/i386/acpi-build.c | 23 ---
hw/tpm/tpm_crb.c | 29 +
2 files changed, 29 insertion
The register is actually 64-bits but in order to make this more clear
than the specification, we define two 32-bit registers:
CTRL_RSP_LADDR and CTRL_RSP_HADDR to match the CTRL_CMD_* naming. This
deviates from the specs but is way more clear.
Previously, the only CRB device uses a fixed system ad
This SysBus variant of the CRB interface supports dynamically locating
the MMIO interface so that Virt machines can use it. This interface
is currently the only one supported by QEMU that works on Windows 11
ARM64. We largely follow the TPM TIS SysBus device as a template.
To try out this device w
On Apple Silicon, when Windows performs a LDP on the CRB MMIO space,
the exception is not decoded by hardware and we cannot trap the MMIO
read. This led to the idea from @agraf to use the same mapping type as
ROM devices: namely that reads should be seen as memory type and
writes should trap as MMI
Since this device is gated to only build for targets with the PC
configuration, we should use the ISA bus like with TPM TIS.
Signed-off-by: Joelle van Dyne
---
hw/tpm/tpm_crb.c | 52
hw/tpm/Kconfig | 2 +-
2 files changed, 27 insertions(+), 27
Instead of calling `memory_region_add_subregion` directly, we defer to
the caller to do it. This allows us to re-use the code for a SysBus
device.
Signed-off-by: Joelle van Dyne
Reviewed-by: Stefan Berger
---
hw/tpm/tpm_ppi.h| 10 +++---
hw/tpm/tpm_crb.c| 4 ++--
hw/tpm/tpm
When we moved to a single mapping and modified TPM CRB's VMState, it
broke restoring of VMs that were saved on an older version. This
change allows those VMs to gracefully migrate to the new memory
mapping.
Signed-off-by: Joelle van Dyne
---
hw/tpm/tpm_crb.h| 1 +
hw/tpm/tpm_crb.c
TPM needs to know its own base address in order to generate its DSDT
device entry.
Signed-off-by: Joelle van Dyne
---
hw/arm/virt.c | 37 +
1 file changed, 37 insertions(+)
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index 7d9dbc2663..432148ef47 100644
--- a/h
TPM needs to know its own base address in order to generate its DSDT
device entry.
Signed-off-by: Joelle van Dyne
---
hw/loongarch/virt.c | 37 +
1 file changed, 37 insertions(+)
diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c
index e19b042ce8..9c536c5
This reduces redundent code in different machine types with ACPI table
generation. Additionally, this will allow us to support multiple TPM
interfaces. Finally, this matches up with the TPM TIS ISA
implementation.
Ideally, we would be able to call `qbus_build_aml` and avoid any TPM
specific code i
Andrew Melnychenko writes:
> Now, the binary objects may be retrieved by id.
> It would require for future qmp commands that may require specific
> eBPF blob.
>
> Signed-off-by: Andrew Melnychenko
> ---
> ebpf/ebpf.c | 70
> ebpf/ebpf.h
Andrew Melnychenko writes:
> Now, the binary objects may be retrieved by id.
> It would require for future qmp commands that may require specific
> eBPF blob.
>
> Signed-off-by: Andrew Melnychenko
> ---
[...]
> diff --git a/ebpf/meson.build b/ebpf/meson.build
> index 2f627d6c7d..c9bbaa7c90 100
On 7/10/23 18:51, Philippe Mathieu-Daudé wrote:
+static gboolean pl011_xmit(void *do_not_use, GIOCondition cond, void *opaque)
+{
+PL011State *s = opaque;
+int ret;
+const uint8_t *buf;
+uint32_t buflen;
+uint32_t count;
+bool tx_enabled;
+
+if (!qemu_chr_fe_backend_co
Andrew Melnychenko writes:
> Added command "request-ebpf". This command returns
> eBPF program encoded base64. The program taken from the
> skeleton and essentially is an ELF object that can be
> loaded in the future with libbpf.
>
> The reason to use the command to provide the eBPF object
> inst
Ping
Am 30.06.23 um 16:18 schrieb Fiona Ebner:
> This is intended to be a semantic revert of commit 9b09503752
> ("migration: run setup callbacks out of big lock"). There have been so
> many changes since that commit (e.g. a new setup callback
> dirty_bitmap_save_setup() that also needs to be adap
This series adds support for KVM AIA in RISC-V architecture.
In order to test these patches, we require Linux with KVM AIA support which can
be found in the riscv_kvm_aia_hwaccel_v1 branch at
https://github.com/avpatel/linux.git
---
v6:
- fix alignment
- add hart index to the error message of ISM
We create a vAIA chip by using the KVM_DEV_TYPE_RISCV_AIA and then set up
the chip with the KVM_DEV_RISCV_AIA_GRP_* APIs.
Signed-off-by: Yong-Xuan Wang
Reviewed-by: Jim Shu
Reviewed-by: Daniel Henrique Barboza
Reviewed-by: Andrew Jones
---
target/riscv/kvm.c | 160 ++
We check the in-kernel irqchip support when using KVM acceleration.
Signed-off-by: Yong-Xuan Wang
Reviewed-by: Jim Shu
Reviewed-by: Daniel Henrique Barboza
Reviewed-by: Andrew Jones
---
target/riscv/kvm.c | 10 +-
1 file changed, 9 insertions(+), 1 deletion(-)
diff --git a/target/ris
Select KVM AIA when the host kernel has in-kernel AIA chip support.
Since KVM AIA only has one APLIC instance, we map the QEMU APLIC
devices to KVM APLIC.
We also extend virt machine to specify the KVM AIA mode. The "kvm-aia"
parameter is passed along with machine name in QEMU command-line.
1) "kvm
In this patch, we create the APLIC and IMSIC FDT helper functions and
remove M mode AIA devices when using KVM acceleration.
Signed-off-by: Yong-Xuan Wang
Reviewed-by: Jim Shu
Reviewed-by: Daniel Henrique Barboza
Reviewed-by: Andrew Jones
---
hw/riscv/virt.c | 290 +++-
KVM AIA can't emulate APLIC only. When "aia=aplic" parameter is passed,
APLIC devices is emulated by QEMU. For "aia=aplic-imsic", remove the
mmio operations of APLIC when using KVM AIA and send wired interrupt
signal via KVM_IRQ_LINE API.
After KVM AIA enabled, MSI messages are delivered by KVM_SIG
Signed-off-by: Song Gao
Reviewed-by: Richard Henderson
---
target/loongarch/insn_trans/trans_lasx.c.inc | 6 ++
target/loongarch/translate.c | 1 +
2 files changed, 7 insertions(+)
create mode 100644 target/loongarch/insn_trans/trans_lasx.c.inc
diff --git a/target/loongarch
This patch includes:
- XVNEG.{B/H/W/D}.
Signed-off-by: Song Gao
Reviewed-by: Richard Henderson
---
target/loongarch/disas.c | 10 ++
target/loongarch/insn_trans/trans_lasx.c.inc | 5 +
target/loongarch/insn_trans/trans_lsx.c.inc | 12 ++--
target/loonga
This patch includes:
- XVREPLGR2VR.{B/H/W/D}.
Signed-off-by: Song Gao
Reviewed-by: Richard Henderson
---
target/loongarch/disas.c | 10 ++
target/loongarch/insn_trans/trans_lasx.c.inc | 5 +
target/loongarch/insn_trans/trans_lsx.c.inc | 13 +++--
target
This patch includes:
- XVLDI.
Signed-off-by: Song Gao
Reviewed-by: Richard Henderson
---
target/loongarch/disas.c | 7 +++
target/loongarch/insn_trans/trans_lasx.c.inc | 2 ++
target/loongarch/insn_trans/trans_lsx.c.inc | 6 --
target/loongarch/insns.decode
This patch includes:
- XVAVG.{B/H/W/D/}[U];
- XVAVGR.{B/H/W/D}[U].
Signed-off-by: Song Gao
---
target/loongarch/disas.c | 17 +
target/loongarch/insn_trans/trans_lasx.c.inc | 17 +
target/loongarch/insns.decode| 17 +
target
Signed-off-by: Song Gao
Reviewed-by: Richard Henderson
---
linux-user/loongarch64/signal.c | 1 +
target/loongarch/cpu.c | 1 +
target/loongarch/cpu.h | 24 --
target/loongarch/gdbstub.c | 1 +
target/loongarch/internals.h| 22 ---
This patch includes:
- XVMUL.{B/H/W/D};
- XVMUH.{B/H/W/D}[U];
- XVMULW{EV/OD}.{H.B/W.H/D.W/Q.D}[U];
- XVMULW{EV/OD}.{H.BU.B/W.HU.H/D.WU.W/Q.DU.D}.
Signed-off-by: Song Gao
---
target/loongarch/disas.c | 38 +
target/loongarch/insn_trans/trans_lasx.c.inc | 42 ++
This patch includes:
- XVMSKLTZ.{B/H/W/D};
- XVMSKGEZ.B;
- XVMSKNZ.B.
Signed-off-by: Song Gao
---
target/loongarch/disas.c | 7 ++
target/loongarch/insn_trans/trans_lasx.c.inc | 7 ++
target/loongarch/insns.decode| 7 ++
target/loongarch/vec_helper.c
This patch includes:
- XVFRSTP[I].{B/H}.
Signed-off-by: Song Gao
---
target/loongarch/disas.c | 5 ++
target/loongarch/insn_trans/trans_lasx.c.inc | 5 ++
target/loongarch/insns.decode| 5 ++
target/loongarch/vec_helper.c| 48 ---
This patch includes:
- XVADD.{B/H/W/D/Q};
- XVSUB.{B/H/W/D/Q}.
Signed-off-by: Song Gao
Reviewed-by: Richard Henderson
---
target/loongarch/disas.c | 23 +
target/loongarch/insn_trans/trans_lasx.c.inc | 52 +-
target/loongarch/insn_trans/trans_lsx.c.inc | 511 +
This patch includes:
- XVADDI.{B/H/W/D}U;
- XVSUBI.{B/H/W/D}U.
Signed-off-by: Song Gao
Reviewed-by: Richard Henderson
---
target/loongarch/disas.c | 14 ++
target/loongarch/insn_trans/trans_lasx.c.inc | 9 ++
target/loongarch/insn_trans/trans_lsx.c.inc | 136 +---
Reviewed-by: Richard Henderson
Signed-off-by: Song Gao
---
target/loongarch/cpu.c | 2 ++
target/loongarch/cpu.h | 2 ++
target/loongarch/insn_trans/trans_lasx.c.inc | 10 ++
3 files changed, 14 insertions(+)
diff --git a/target/loongarch/cp
This patch includes:
- XVDIV.{B/H/W/D}[U];
- XVMOD.{B/H/W/D}[U].
Signed-off-by: Song Gao
---
target/loongarch/disas.c | 17 +
target/loongarch/insn_trans/trans_lasx.c.inc | 17 +
target/loongarch/insns.decode| 17 +++
This patch includes:
- XVEXTH.{H.B/W.H/D.W/Q.D};
- XVEXTH.{HU.BU/WU.HU/DU.WU/QU.DU}.
Signed-off-by: Song Gao
---
target/loongarch/disas.c | 9 +
target/loongarch/insn_trans/trans_lasx.c.inc | 9 +
target/loongarch/insns.decode| 9 +
target/loong
This patch includes:
- XVADDW{EV/OD}.{H.B/W.H/D.W/Q.D}[U];
- XVSUBW{EV/OD}.{H.B/W.H/D.W/Q.D}[U];
- XVADDW{EV/OD}.{H.BU.B/W.HU.H/D.WU.W/Q.DU.D}.
Signed-off-by: Song Gao
---
target/loongarch/disas.c | 43 +++
target/loongarch/insn_trans/trans_lasx.c.inc | 45 +++
targ
This patch includes:
- XVSEQ[I].{B/H/W/D};
- XVSLE[I].{B/H/W/D}[U];
- XVSLT[I].{B/H/W/D/}[U].
Signed-off-by: Song Gao
---
target/loongarch/disas.c | 43 +++
target/loongarch/insn_trans/trans_lasx.c.inc | 43 +++
target/loongarch/insn_trans/trans_lsx.c.inc | 263 ++-
This patch includes:
- XVMAX[I].{B/H/W/D}[U];
- XVMIN[I].{B/H/W/D}[U].
Signed-off-by: Song Gao
---
target/loongarch/disas.c | 34 ++
target/loongarch/insn_trans/trans_lasx.c.inc | 36
target/loongarch/insns.decode| 36 +
This patch includes:
- XVSIGNCOV.{B/H/W/D}.
Signed-off-by: Song Gao
Reviewed-by: Richard Henderson
---
target/loongarch/disas.c | 5 +
target/loongarch/insn_trans/trans_lasx.c.inc | 5 +
target/loongarch/insns.decode| 5 +
target/loongarch/vec.h
This patch includes:
- XV{AND/OR/XOR/NOR/ANDN/ORN}.V;
- XV{AND/OR/XOR/NOR}I.B.
Signed-off-by: Song Gao
---
target/loongarch/disas.c | 12
target/loongarch/insn_trans/trans_lasx.c.inc | 11 +++
target/loongarch/insn_trans/trans_lsx.c.inc | 5 +++--
targe
This patch includes:
- XVLD[X], XVST[X];
- XVLDREPL.{B/H/W/D};
- XVSTELM.{B/H/W/D}.
Signed-off-by: Song Gao
---
target/loongarch/disas.c | 24 ++
target/loongarch/insn_trans/trans_lasx.c.inc | 80
target/loongarch/insn_trans/trans_lsx.c.inc | 54
This patch includes:
- XVBITCLR[I].{B/H/W/D};
- XVBITSET[I].{B/H/W/D};
- XVBITREV[I].{B/H/W/D}.
Signed-off-by: Song Gao
---
target/loongarch/disas.c | 25 ++
target/loongarch/insn_trans/trans_lasx.c.inc | 27 +++
target/loongarch/insns.decode|
This patch includes:
- XVF{ADD/SUB/MUL/DIV}.{S/D};
- XVF{MADD/MSUB/NMADD/NMSUB}.{S/D};
- XVF{MAX/MIN}.{S/D};
- XVF{MAXA/MINA}.{S/D};
- XVFLOGB.{S/D};
- XVFCLASS.{S/D};
- XVF{SQRT/RECIP/RSQRT}.{S/D}.
Signed-off-by: Song Gao
---
target/loongarch/disas.c | 46 +++
target
Signed-off-by: Song Gao
---
target/loongarch/cpu.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c
index c9f9cbb19d..aeccbb42e6 100644
--- a/target/loongarch/cpu.c
+++ b/target/loongarch/cpu.c
@@ -392,6 +392,7 @@ static void loongarch_la464_init
This patch includes:
- VEXT2XV.{H/W/D}.B, VEXT2XV.{HU/WU/DU}.BU;
- VEXT2XV.{W/D}.B, VEXT2XV.{WU/DU}.HU;
- VEXT2XV.D.W, VEXT2XV.DU.WU.
Signed-off-by: Song Gao
---
target/loongarch/disas.c | 13 +
target/loongarch/helper.h| 13 +
target/loong
Hi,
This series adds LoongArch LASX instructions.
About test:
We use RISU test the LoongArch LASX instructions.
QEMU:
https://github.com/loongson/qemu/tree/tcg-old-abi-support-lasx
RISU:
https://github.com/loongson/risu/tree/loongarch-suport-lasx
Please review, Thanks.
Changes for v3:
This patch includes:
- XVBITSEL.V;
- XVBITSELI.B;
- XVSET{EQZ/NEZ}.V;
- XVSETANYEQZ.{B/H/W/D};
- XVSETALLNEZ.{B/H/W/D}.
Signed-off-by: Song Gao
---
target/loongarch/disas.c | 19 +
target/loongarch/helper.h| 16
target/loongarch/insn_trans
This patch includes:
- XVFCMP.cond.{S/D}.
Signed-off-by: Song Gao
---
target/loongarch/disas.c | 94
target/loongarch/helper.h| 8 +-
target/loongarch/insn_trans/trans_lasx.c.inc | 3 +
target/loongarch/insn_trans/trans_lsx.c.inc |
This patch includes:
- XVSHUF.{B/H/W/D};
- XVPERM.W;
- XVSHUF4i.{B/H/W/D};
- XVPERMI.{W/D/Q};
- XVEXTRINS.{B/H/W/D}.
Signed-off-by: Song Gao
---
target/loongarch/disas.c | 21
target/loongarch/helper.h| 3 +
target/loongarch/insn_trans/trans_lasx.c
This patch includes:
- XVABSD.{B/H/W/D}[U].
Signed-off-by: Song Gao
Reviewed-by: Richard Henderson
---
target/loongarch/disas.c | 9 +
target/loongarch/insn_trans/trans_lasx.c.inc | 9 +
target/loongarch/insns.decode| 9 +
target/loong
This patch includes:
- XVINSGR2VR.{W/D};
- XVPICKVE2GR.{W/D}[U].
Signed-off-by: Song Gao
---
target/loongarch/disas.c | 18
target/loongarch/insn_trans/trans_lasx.c.inc | 30
target/loongarch/insns.decode| 7 +
3 files ch
This patch includes:
- XVSLLWIL.{H.B/W.H/D.W};
- XVSLLWIL.{HU.BU/WU.HU/DU.WU};
- XVEXTL.Q.D, VEXTL.QU.DU.
Signed-off-by: Song Gao
---
target/loongarch/disas.c | 9
target/loongarch/insn_trans/trans_lasx.c.inc | 9
target/loongarch/insns.decode| 9
This patch includes:
- XVMADD.{B/H/W/D};
- XVMSUB.{B/H/W/D};
- XVMADDW{EV/OD}.{H.B/W.H/D.W/Q.D}[U];
- XVMADDW{EV/OD}.{H.BU.B/W.HU.H/D.WU.W/Q.DU.D}.
Signed-off-by: Song Gao
---
target/loongarch/disas.c | 34 ++
target/loongarch/insn_trans/trans_lasx.c.inc | 38 +++
t
This patch includes:
- XVSRLRN.{B.H/H.W/W.D};
- XVSRARN.{B.H/H.W/W.D};
- XVSRLRNI.{B.H/H.W/W.D/D.Q};
- XVSRARNI.{B.H/H.W/W.D/D.Q}.
Signed-off-by: Song Gao
---
target/loongarch/disas.c | 16 ++
target/loongarch/insn_trans/trans_lasx.c.inc | 16 ++
target/loongarch/insns.deco
This patch includes:
- XVPACK{EV/OD}.{B/H/W/D};
- XVPICK{EV/OD}.{B/H/W/D};
- XVILV{L/H}.{B/H/W/D}.
Signed-off-by: Song Gao
---
target/loongarch/disas.c | 27
target/loongarch/insn_trans/trans_lasx.c.inc | 27
target/loongarch/insns.decode| 27
This patch includes:
- XVSRLR[I].{B/H/W/D};
- XVSRAR[I].{B/H/W/D}.
Signed-off-by: Song Gao
---
target/loongarch/disas.c | 18 ++
target/loongarch/insn_trans/trans_lasx.c.inc | 18 ++
target/loongarch/insns.decode| 17 +++
This patch includes:
- XVSLL[I].{B/H/W/D};
- XVSRL[I].{B/H/W/D};
- XVSRA[I].{B/H/W/D};
- XVROTR[I].{B/H/W/D}.
Signed-off-by: Song Gao
Reviewed-by: Richard Henderson
---
target/loongarch/disas.c | 36
target/loongarch/insn_trans/trans_lasx.c.inc | 36
This patch includes:
- XVSSRLN.{B.H/H.W/W.D};
- XVSSRAN.{B.H/H.W/W.D};
- XVSSRLN.{BU.H/HU.W/WU.D};
- XVSSRAN.{BU.H/HU.W/WU.D};
- XVSSRLNI.{B.H/H.W/W.D/D.Q};
- XVSSRANI.{B.H/H.W/W.D/D.Q};
- XVSSRLNI.{BU.H/HU.W/WU.D/DU.Q};
- XVSSRANI.{BU.H/HU.W/WU.D/DU.Q}.
Signed-off-by: Song Gao
---
target/loonga
This patch includes:
- XVSAT.{B/H/W/D}[U].
Signed-off-by: Song Gao
---
target/loongarch/disas.c | 9
target/loongarch/insn_trans/trans_lasx.c.inc | 9
target/loongarch/insns.decode| 9
target/loongarch/vec_helper.c| 48 +++
This patch includes:
- XVREPLVE.{B/H/W/D};
- XVREPL128VEI.{B/H/W/D};
- XVREPLVE0.{B/H/W/D/Q};
- XVINSVE0.{W/D};
- XVPICKVE.{W/D};
- XVBSLL.V, XVBSRL.V.
Signed-off-by: Song Gao
---
target/loongarch/disas.c | 28 +
target/loongarch/helper.h| 5 +
targ
This patch includes:
- XVHADDW.{H.B/W.H/D.W/Q.D/HU.BU/WU.HU/DU.WU/QU.DU};
- XVHSUBW.{H.B/W.H/D.W/Q.D/HU.BU/WU.HU/DU.WU/QU.DU}.
Signed-off-by: Song Gao
---
target/loongarch/disas.c | 17 +
target/loongarch/insn_trans/trans_lasx.c.inc | 17 +
target/loongarch/in
This patch includes:
- XVSRLN.{B.H/H.W/W.D};
- XVSRAN.{B.H/H.W/W.D};
- XVSRLNI.{B.H/H.W/W.D/D.Q};
- XVSRANI.{B.H/H.W/W.D/D.Q}.
Signed-off-by: Song Gao
---
target/loongarch/disas.c | 16 ++
target/loongarch/insn_trans/trans_lasx.c.inc | 16 ++
target/loongarch/insns.decode
This patch includes:
- XVCLO.{B/H/W/D};
- XVCLZ.{B/H/W/D}.
Signed-off-by: Song Gao
---
target/loongarch/disas.c | 9 +
target/loongarch/insn_trans/trans_lasx.c.inc | 9 +
target/loongarch/insns.decode| 9 +
target/loongarch/vec.h
This patch includes:
- XVSADD.{B/H/W/D}[U];
- XVSSUB.{B/H/W/D}[U].
Signed-off-by: Song Gao
Reviewed-by: Richard Henderson
---
target/loongarch/disas.c | 17 +
target/loongarch/insn_trans/trans_lasx.c.inc | 17 +
target/loongarch/insns.decode
This patch includes:
- XVSSRLRN.{B.H/H.W/W.D};
- XVSSRARN.{B.H/H.W/W.D};
- XVSSRLRN.{BU.H/HU.W/WU.D};
- XVSSRARN.{BU.H/HU.W/WU.D};
- XVSSRLRNI.{B.H/H.W/W.D/D.Q};
- XVSSRARNI.{B.H/H.W/W.D/D.Q};
- XVSSRLRNI.{BU.H/HU.W/WU.D/DU.Q};
- XVSSRARNI.{BU.H/HU.W/WU.D/DU.Q}.
Signed-off-by: Song Gao
---
targe
This patch includes:
- XVFCVT{L/H}.{S.H/D.S};
- XVFCVT.{H.S/S.D};
- XVFRINT[{RNE/RZ/RP/RM}].{S/D};
- XVFTINT[{RNE/RZ/RP/RM}].{W.S/L.D};
- XVFTINT[RZ].{WU.S/LU.D};
- XVFTINT[{RNE/RZ/RP/RM}].W.D;
- XVFTINT[{RNE/RZ/RP/RM}]{L/H}.L.S;
- XVFFINT.{S.W/D.L}[U];
- X[CVFFINT.S.L, VFFINT{L/H}.D.W.
Signed-off
This patch includes:
- XVADDA.{B/H/W/D}.
Signed-off-by: Song Gao
---
target/loongarch/disas.c | 5
target/loongarch/insn_trans/trans_lasx.c.inc | 5
target/loongarch/insns.decode| 5
target/loongarch/vec.h | 2 ++
targe
This patch includes:
- VPCNT.{B/H/W/D}.
Signed-off-by: Song Gao
---
target/loongarch/disas.c | 5 +
target/loongarch/insn_trans/trans_lasx.c.inc | 5 +
target/loongarch/insns.decode| 5 +
target/loongarch/vec_helper.c| 4 ++--
4 fil
bdrv_pad_request() relies on requests' lengths not to exceed SIZE_MAX,
which bdrv_check_qiov_request() does not guarantee.
bdrv_check_request32() however will guarantee this, and both of
bdrv_pad_request()'s callers (bdrv_co_preadv_part() and
bdrv_co_pwritev_part()) already run it before calling
b
On 13/07/2023 22.23, Richard Henderson wrote:
We adjust CONFIG_ATOMIC128 and CONFIG_CMPXCHG128 with
CONFIG_ATOMIC128_OPT in atomic128.h. It is difficult
to tell when those changes have been applied with the
ifdef we must use with CONFIG_CMPXCHG128. So instead
use HAVE_CMPXCHG128, which triggers
On 7/14/23 10:51, Gavin Shan wrote:
On 7/14/23 02:29, Philippe Mathieu-Daudé wrote:
On 13/7/23 14:34, Gavin Shan wrote:
On 7/13/23 21:52, Marcin Juszkiewicz wrote:
W dniu 13.07.2023 o 13:44, Peter Maydell pisze:
I see this isn't a change in this patch, but given that
what the user specifies
On Wed, Jul 12, 2023 at 03:25:24PM +0800, Zhenzhong Duan wrote:
> From: Yi Liu
>
> Add the iommufd backend. The IOMMUFD container class is implemented
> based on the new /dev/iommu user API. This backend obviously depends
> on CONFIG_IOMMUFD.
>
> So far, the iommufd backend doesn't support live
On 7/14/23 00:12, Alistair Francis wrote:
On Fri, Jul 14, 2023 at 11:14 AM Daniel Henrique Barboza
wrote:
On 7/13/23 19:47, Conor Dooley wrote:
On Thu, Jul 13, 2023 at 07:35:01PM -0300, Daniel Henrique Barboza wrote:
On 7/13/23 19:12, Conor Dooley wrote:
And a question for you below
>-Original Message-
>From: Joel Granados
>Sent: Friday, July 14, 2023 5:23 PM
>Subject: Re: [RFC PATCH v4 20/24] vfio/iommufd: Implement the iommufd
>backend
>
>On Wed, Jul 12, 2023 at 03:25:24PM +0800, Zhenzhong Duan wrote:
>> From: Yi Liu
...
>> +static int vfio_get_devicefd(const char
On Wed, 5 Jul 2023 10:12:40 +0200
Claudio Fontana wrote:
> Hi all, partially resurrecting an old thread.
>
> I've seen how for Epyc something special was done in the past in terms of
> apicid assignments based on topology, which was then reverted apparently,
> but I wonder if something more gen
On 13.07.23 21:58, Maciej S. Szmigiero wrote:
On 16.06.2023 11:26, David Hildenbrand wrote:
Having large virtio-mem devices that only expose little memory to a VM
is currently a problem: we map the whole sparse memory region into the
guest using a single memslot, resulting in one gigantic memslo
On Thu, 13 Jul 2023 at 19:43, Stefan Berger wrote:
>
>
>
> On 7/13/23 13:18, Peter Maydell wrote:
> > On Thu, 13 Jul 2023 at 18:16, Stefan Berger wrote:
> >> I guess the first point would be to decide whether to support an i2c bus
> >> on the virt board and then whether we can use the aspeed bus
On Fri, Jul 14, 2023 at 10:00:19AM +0530, Anup Patel wrote:
> > > OpenSBI v1.3
> > >_ _
> > > / __ \ / | _ \_ _|
> > > | | | |_ __ ___ _ __ | (___ | |_) || |
> > > | | | | '_ \ / _ \ '_ \ \___ \| _ < | |
> > > | |__| | |_)
On 7/6/23 21:15, Denis V. Lunev wrote:
Commit e6df58a5578fee7a50bbf36f4a50a2781cff855d
Author: Hanna Reitz
Date: Wed May 8 23:18:18 2019 +0200
qemu-nbd: Do not close stderr
has introduced an interesting regression. Original behavior of
ssh somehost qemu-nbd /home/den/tmp/fi
It's possible to compile QEMU without the USB devices (e.g. when using
"--without-default-devices" as option for the "configure" script).
To be still able to run the loongson3-virt machine in default mode with
such a QEMU binary, we have to check here for the availability of the
OHCI controller fir
The following changes since commit 3dd9e54703e6ae4f9ab3767f5cecc99edf08:
Merge tag 'block-pull-request' of https://gitlab.com/stefanha/qemu into
staging (2023-07-12 20:46:10 +0100)
are available in the Git repository at:
https://gitlab.com/bonzini/qemu.git tags/for-upstream
for you to
From: Olaf Hering
According to the 82371FB documentation (82371FB.pdf, 2.3.9. BMIBA-BUS
MASTER INTERFACE BASE ADDRESS REGISTER, April 1997), the register is
32bit wide. To properly reset it to default values, all 32bit need to be
cleared. Bit #0 "Resource Type Indicator (RTE)" needs to be enabled
From: Cédric Le Goater
It is useful to extend the number of available PCIe devices to KVM guests
for passthrough scenarios and also to expose these models to a different
(big endian) architecture. Introduce a new config PCIE_DEVICES to select
models, Intel Ethernet adapters and one USB controller
From: Stefano Garzarella
Commit 1880ad4f4e ("virtio-scsi: Batched prepare for cmd reqs") split
calls to scsi_req_new() and scsi_req_enqueue() in the virtio-scsi device.
No ill effects were observed until commit 8cc5583abe ("virtio-scsi: Send
"REPORTED LUNS CHANGED" sense data upon disk hotplug ev
From: Stefano Garzarella
The previous commit moved the unit attention clearing when we create
the request. So now we can clean scsi_clear_unit_attention() to handle
only the case of the REPORT LUNS command: this is the only case in
which a UNIT ATTENTION is cleared without having been reported.
From: Stefano Garzarella
scsi_clear_unit_attention() now only handles REPORTED LUNS DATA HAS
CHANGED.
This only happens when we handle REPORT LUNS commands, so let's rename
the function in scsi_clear_reported_luns_changed() and call it only in
scsi_target_emulate_report_luns().
Suggested-by: Pa
Signed-off-by: Michael Tokarev
---
block.c | 2 +-
block/block-copy.c | 4 ++--
block/export/vduse-blk.c | 2 +-
block/export/vhost-user-blk-server.c | 2 +-
block/export/vhost-user-blk-server.h | 2 +-
block/file-posix.c
Signed-off-by: Michael Tokarev
---
host/include/ppc/host/cpuinfo.h | 2 +-
hw/ppc/ppc.c| 2 +-
hw/ppc/prep_systemio.c | 2 +-
hw/ppc/spapr.c | 8
hw/ppc/spapr_hcall.c| 2 +-
hw/ppc/spapr_nvdimm.c
Signed-off-by: Michael Tokarev
---
bsd-user/errno_defs.h| 2 +-
bsd-user/freebsd/target_os_siginfo.h | 2 +-
bsd-user/freebsd/target_os_stack.h | 4 ++--
bsd-user/freebsd/target_os_user.h| 2 +-
bsd-user/qemu.h | 2 +-
bsd-user/signal-common.h
Signed-off-by: Michael Tokarev
---
util/cpuinfo-aarch64.c | 4 ++--
util/cpuinfo-i386.c| 4 ++--
util/cpuinfo-ppc.c | 2 +-
util/main-loop.c | 2 +-
util/oslib-posix.c | 2 +-
util/qdist.c | 2 +-
util/qemu-progress.c | 2 +-
util/qemu-sockets.c| 2 +-
util/rcu.c
Signed-off-by: Michael Tokarev
---
host/include/i386/host/cpuinfo.h | 2 +-
hw/i386/acpi-build.c | 4 ++--
hw/i386/amd_iommu.c | 4 ++--
hw/i386/intel_iommu.c| 4 ++--
hw/i386/kvm/xen_xenstore.c | 2 +-
hw/i386/kvm/xenstore_impl.c | 2 +-
hw/i386/pc
Signed-off-by: Michael Tokarev
---
target/hexagon/README | 2 +-
target/hexagon/fma_emu.c| 2 +-
target/hexagon/idef-parser/README.rst | 2 +-
target/hexagon/idef-parser/idef-parser.h| 2 +-
target/hexagon/idef-parser/parser-helpers.c | 6 +
Signed-off-by: Michael Tokarev
---
ui/cocoa.m| 2 +-
ui/keymaps.h | 2 +-
ui/sdl2-2d.c | 2 +-
ui/sdl2.c | 2 +-
ui/vnc-enc-tight.c| 2 +-
ui/vnc-enc-zrle.c.inc | 2 +-
ui/vnc-enc-zywrle.h | 4 ++--
7 files changed, 8 insertions(+), 8 deletions(-)
Signed-off-by: Michael Tokarev
---
hw/acpi/aml-build.c | 6 +++---
hw/acpi/hmat.c | 2 +-
hw/acpi/nvdimm.c | 2 +-
hw/block/hd-geometry.c | 4 ++--
hw/block/pflash_cfi01.c | 2 +-
hw/char/cadence_uart.c | 2 +-
hw/c
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