Re: [PATCH] virtio-gpu-udmabuf: replacing scanout_width/height with backing_width/height

On 7/10/2023 4:57 AM, Marc-André Lureau wrote: Hi On Thu, Jul 6, 2023 at 3:10 AM Dongwon Kim wrote: 'backing_width' and 'backing_height' are commonly used to indicate the size of the whole backing region so it makes sense to use those terms for VGAUDMABuf as well in place of

[PATCH 00/11] tpm: introduce TPM CRB SysBus device

The impetus for this patch set is to get TPM 2.0 working on Windows 11 ARM64. Windows' tpm.sys does not seem to work on a TPM TIS device (as verified with VMWare's implementation). However, the current TPM CRB device uses a fixed system bus address that is reserved for RAM in ARM64 Virt machines.

[PATCH 09/11] tpm_tis_sysbus: fix crash when PPI is enabled

If 'ppi' property is set, then `tpm_ppi_reset` is called on reset which SEGFAULTs because `tpmppi->buf` is not allocated. Signed-off-by: Joelle van Dyne --- hw/tpm/tpm_tis_sysbus.c | 4 1 file changed, 4 insertions(+) diff --git a/hw/tpm/tpm_tis_sysbus.c b/hw/tpm/tpm_tis_sysbus.c index 45e

[PATCH 05/11] tpm_crb: use the ISA bus

Since this device is gated to only build for targets with the PC configuration, we should use the ISA bus like with TPM TIS. Signed-off-by: Joelle van Dyne --- hw/tpm/tpm_crb.c | 52 hw/tpm/Kconfig | 2 +- 2 files changed, 27 insertions(+), 27

[PATCH 02/11] tpm_crb: CTRL_RSP_ADDR is 64-bits wide

The register is actually 64-bits but in order to make this more clear than the specification, we define two 32-bit registers: CTRL_RSP_LADDR and CTRL_RSP_HADDR to match the CTRL_CMD_* naming. This deviates from the specs but is way more clear. Previously, the only CRB device uses a fixed system ad

[PATCH 06/11] tpm_crb: move ACPI table building to device interface

This logic is similar to TPM TIS ISA device. Signed-off-by: Joelle van Dyne --- hw/i386/acpi-build.c | 23 --- hw/tpm/tpm_crb.c | 28 2 files changed, 28 insertions(+), 23 deletions(-) diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c

[PATCH 08/11] hw/loongarch/virt: add plug handler for TPM on SysBus

TPM needs to know its own base address in order to generate its DSDT device entry. Signed-off-by: Joelle van Dyne --- hw/loongarch/virt.c | 37 + 1 file changed, 37 insertions(+) diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c index e19b042ce8..9c536c5

[PATCH 03/11] tpm_ppi: refactor memory space initialization

Instead of calling `memory_region_add_subregion` directly, we defer to the caller to do it. This allows us to re-use the code for a SysBus device. Signed-off-by: Joelle van Dyne --- hw/tpm/tpm_ppi.h| 10 +++--- hw/tpm/tpm_crb.c| 4 ++-- hw/tpm/tpm_crb_common.c | 3 +++ hw/t

[PATCH 04/11] tpm_crb: use a single read-as-mem/write-as-mmio mapping

On Apple Silicon, when Windows performs a LDP on the CRB MMIO space, the exception is not decoded by hardware and we cannot trap the MMIO read. This led to the idea from @agraf to use the same mapping type as ROM devices: namely that reads should be seen as memory type and writes should trap as MMI

[PATCH 10/11] tpm_tis_sysbus: move DSDT AML generation to device

This reduces redundent code in different machine types with ACPI table generation. Additionally, this will allow us to support multiple TPM interfaces. Finally, this matches up with the TPM TIS ISA implementation. Ideally, we would be able to call `qbus_build_aml` and avoid any TPM specific code i

[PATCH 11/11] tpm_crb_sysbus: introduce TPM CRB SysBus device

This SysBus variant of the CRB interface supports dynamically locating the MMIO interface so that Virt machines can use it. This interface is currently the only one supported by QEMU that works on Windows 11 ARM64. We largely follow the TPM TIS SysBus device as a template. Signed-off-by: Joelle va

[PATCH 07/11] hw/arm/virt: add plug handler for TPM on SysBus

TPM needs to know its own base address in order to generate its DSDT device entry. Signed-off-by: Joelle van Dyne --- hw/arm/virt.c | 37 + 1 file changed, 37 insertions(+) diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 7d9dbc2663..432148ef47 100644 --- a/h

[PATCH 01/11] tpm_crb: refactor common code

In preparation for the SysBus variant, we move common code styled after the TPM TIS devices. To maintain compatibility, we do not rename the existing tpm-crb device. Signed-off-by: Joelle van Dyne --- docs/specs/tpm.rst | 1 + hw/tpm/tpm_crb.h| 76 +++ hw/tpm/tpm_crb.c

[PATCH] virtio-gpu-udmabuf: correct naming of QemuDmaBuf size properties

Replace 'width' and 'height' in QemuDmaBuf with 'backing_widht' and 'backing_height' as these commonly indicate the size of the whole surface (e.g. guest's Xorg extended display). Then use 'width' and 'height' for sub region in there (e.g. guest's scanouts). Cc: Gerd Hoffmann Cc: Marc-André Lurea

Re: [RFC PATCH 6/9] ui/gtk: Add a new parameter to assign connectors/monitors to GFX VCs

On 7/11/2023 10:52 PM, Markus Armbruster wrote: "Kim, Dongwon" writes: On 7/10/2023 11:36 PM, Markus Armbruster wrote: "Kim, Dongwon" writes: On 7/9/2023 11:05 PM, Markus Armbruster wrote: "Kim, Dongwon" writes: On 7/7/2023 7:07 AM, Markus Armbruster wrote: [...] Old question not

[PATCH 3/3] hw/arm/virt: Support host CPU type only when KVM or HVF is configured

The CPU type 'host-arm-cpu' class won't be registered until KVM or HVF is configured in target/arm/cpu64.c. Support the corresponding CPU type only when KVM or HVF is configured. Signed-off-by: Gavin Shan --- hw/arm/virt.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/hw/arm/virt.c b/hw/

[PATCH 2/3] hw/arm/virt: Use generic CPU type invalidation

There is a generic CPU type invalidation in machine_run_board_init() and we needn't a same and private invalidation. Set mc->valid_cpu_types to use the generic CPU type invalidation. No functional change intended. Signed-off-by: Gavin Shan --- hw/arm/virt.c | 21 +++-- 1 file ch

[PATCH 1/3] machine: Factor CPU type invalidation out into helper

The CPU type invalidation logic in machine_run_board_init() is independent enough. Lets factor it out into helper validate_cpu_type(). Since we're here, the relevant comments are improved a bit. No functional change intended. Signed-off-by: Gavin Shan --- hw/core/machine.c | 81

[PATCH 0/3] hw/arm/virt: Use generic CPU invalidation

There is a generic CPU type invalidation in machine_run_board_init() and we needn't a same and private invalidation for hw/arm/virt machines. This series intends to use the generic CPU type invalidation on the hw/arm/virt machines. PATCH[1] factors the CPU type invalidation logic in machine_run_bo

[PATCH 1/1] dump: kdump-zlib data pages not dumped with pvtime/aarch64

The kdump-zlib data pages are not dumped from aarch64 host when the 'pvtime' is involved, that is, when the block->target_end is not aligned to page_size. In the below example, it is expected to dump two blocks. (qemu) info mtree -f ... ... 090a-090a0fff (prio 0, ram): pvtime

[PATCH v3 0/6] Misc fixes for throttle

v2 -> v3: - patch 1 -> patch 5 are already reviewed by Alberto - append patch 6: throttle: use enum ThrottleType instead of bool is_write v1 -> v2: - rename 'ThrottleTimerType' to 'ThrottleType' - add assertion to throttle_schedule_timer v1: - introduce enum ThrottleTimerType instead of timers[0]

[PATCH v3 6/6] throttle: use enum ThrottleType instead of bool is_write

enum ThrottleType is already there, use ThrottleType instead of 'bool is_write' for throttle API, also modify related codes from block, fsdev, cryptodev and tests. Signed-off-by: zhenwei pi --- backends/cryptodev.c| 9 + block/throttle-groups.c | 6 -- fsdev/qemu-fsdev-

[PATCH v3 5/6] cryptodev: use NULL throttle timer cb for read direction

Operations on a crytpodev are considered as *write* only, the callback of read direction is never invoked. Use NULL instead of an unreachable path(cryptodev_backend_throttle_timer_cb on read direction). Reviewed-by: Alberto Garcia Signed-off-by: zhenwei pi --- backends/cryptodev.c | 3 +-- 1 fi

[PATCH v3 2/6] test-throttle: use enum ThrottleType

Use enum ThrottleType instead in the throttle test codes. Reviewed-by: Alberto Garcia Signed-off-by: zhenwei pi --- tests/unit/test-throttle.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/tests/unit/test-throttle.c b/tests/unit/test-throttle.c index 7adb5e6652..a60b

[PATCH v3 1/6] throttle: introduce enum ThrottleType

Use enum ThrottleType instead of number index. Reviewed-by: Alberto Garcia Signed-off-by: zhenwei pi --- include/qemu/throttle.h | 11 --- util/throttle.c | 16 +--- 2 files changed, 17 insertions(+), 10 deletions(-) diff --git a/include/qemu/throttle.h b/include/qe

[PATCH v3 4/6] test-throttle: test read only and write only

Reviewed-by: Alberto Garcia Signed-off-by: zhenwei pi --- tests/unit/test-throttle.c | 66 ++ 1 file changed, 66 insertions(+) diff --git a/tests/unit/test-throttle.c b/tests/unit/test-throttle.c index a60b5fe22e..5547837a58 100644 --- a/tests/unit/test-throt

[PATCH v3 3/6] throttle: support read-only and write-only

Only one direction is necessary in several scenarios: - a read-only disk - operations on a device are considered as *write* only. For example, encrypt/decrypt/sign/verify operations on a cryptodev use a single *write* timer(read timer callback is defined, but never invoked). Allow a single dir

Re: [PATCH] docs/system/target-riscv.rst: tidy CPU firmware section

12.07.2023 17:37, Daniel Henrique Barboza wrote: This is how the content of the "RISC-V CPU firmware" section is displayed after the html is generated: "When using the sifive_u or virt machine there are three different firmware boot options: 1. -bios default - This is the default behaviour if no

[PATCH] memory: Remove unecessary variable in memory_region_escape_name()

The variable 'c' isn't needed because it can be replaced by '*p' completely. Remove the unecessary variable 'c' to simplify the function a bit. No functional change intended. Signed-off-by: Gavin Shan --- softmmu/memory.c | 11 +-- 1 file changed, 5 insertions(+), 6 deletions(-) diff -

<    1   2   3