Re: [PATCH 0/3] block: align CoR requests to subclusters

On 6/26/23 19:08, Andrey Drobyshev wrote: > This series makes IO requests performed with copy-on-read to be aligned > to subclusters rather than clusters. It also affects mirror job requests > alignment. > > The initial reason for that change is the following crash discovered: > > qemu-img creat

[PULL 37/60] ppc440: Add a macro to shorten PCIe controller DCR registration

From: BALATON Zoltan It is shorter and more readable to wrap the complex call to ppc_dcr_register() in a macro than to repeat it several times. Signed-off-by: BALATON Zoltan Reviewed-by: Philippe Mathieu-Daudé Message-ID: <4dec5ef8115791dc67253afdff9a703eb816a2a8.1688586835.git.bala...@eik.bm

[PULL 20/60] pnv/xive: Add property on xive sources to define PQ state on reset

From: Frederic Barrat The PQ state of a xive interrupt is always initialized to Q=1, which means the interrupt is disabled. Since a xive source can be embedded in many objects, this patch adds a property to allow that behavior to be refined if needed. Signed-off-by: Frederic Barrat Reviewed-by:

[PULL 21/60] pnv/psi: Initialize the PSIHB interrupts to match hardware

From: Frederic Barrat On the powernv9 and powernv10 machines, the PSIHB interrupts are currently initialized with a PQ state of 0b01, i.e. interrupts are disabled. However real hardware initializes them to 0b00 for the PSIHB. This patch updates it, in case an hypervisor is in the mood of checking

[PULL 51/60] tests/qtest: Add xscom tests for powernv10 machine

From: Nicholas Piggin Add basic chip and core xscom tests for powernv10 machine, equivalent to tests for powernv8 and 9. Signed-off-by: Nicholas Piggin Reviewed-by: Cédric Le Goater Tested-by: Cédric Le Goater Message-ID: <20230706053923.115003-3-npig...@gmail.com> Signed-off-by: Daniel Henri

[PULL 41/60] ppc440: Add busnum property to PCIe controller model

From: BALATON Zoltan Instead of guessing controller number from dcrn_base add a property so the device does not need knowledge about where it is used. Signed-off-by: BALATON Zoltan Reviewed-by: Philippe Mathieu-Daudé Message-ID: Signed-off-by: Daniel Henrique Barboza --- hw/ppc/ppc440_uc.c

[PULL 02/60] target/ppc: Make HDECR underflow edge triggered

From: Nicholas Piggin HDEC interrupts are edge-triggered on HDECR underflow (notably different from DEC which is level-triggered). HDEC interrupts already clear the irq on delivery so that does not need to be changed. Signed-off-by: Nicholas Piggin Reviewed-by: Cédric Le Goater Message-ID: <2

[PULL 07/60] target/ppc: Add TFMR SPR implementation with read and write helpers

From: Nicholas Piggin TFMR is the Time Facility Management Register which is specific to POWER CPUs, and used for the purpose of timebase management (generally by firmware, not the OS). Add helpers for the TFMR register, which will form part of the core timebase facility model in future but for

[PULL 18/60] target: ppc: Use MSR_HVB bit to get the target endianness for memory dump

From: Narayana Murty N Currently on PPC64 qemu always dumps the guest memory in Big Endian (BE) format even though the guest running in Little Endian (LE) mode. So crash tool fails to load the dump as illustrated below: Log : $ virsh dump DOMAIN --memory-only dump.file Domain 'DOMAIN' dumped to

Re: [PATCH v2 2/2] accel/tcg: Always lock pages before translation

On Fri, Jul 07, 2023 at 11:36:11AM +0100, Richard Henderson wrote: > We had done this for user-mode by invoking page_protect > within the translator loop. Extend this to handle system > mode as well. Move page locking out of tb_link_page. > > Reported-by: Liren Wei > Reported-by: Richard W.M. J

[PULL 38/60] ppc440: Rename parent field of PPC460EXPCIEState to match code style

From: BALATON Zoltan QOM prefers to call the parent field parent_obj, change PPC460EXPCIEState ro match that convention. Signed-off-by: BALATON Zoltan Reviewed-by: Philippe Mathieu-Daudé Message-ID: <6995f28215d2a489a661b7d91a1783048829d467.1688586835.git.bala...@eik.bme.hu> Signed-off-by: Da

[PULL 23/60] ppc/pnv: Subclass quad xscom callbacks

From: Joel Stanley Make the existing pnv_quad_xscom_read/write be P9 specific, in preparation for a different P10 callback. Reviewed-by: Cédric Le Goater Signed-off-by: Joel Stanley Reviewed-by: Frederic Barrat Message-ID: <20230704054204.168547-3-j...@jms.id.au> Signed-off-by: Daniel Henriqu

[PULL 49/60] ppc/pnv: Log all unimp warnings with similar message

From: Joel Stanley Add the function name so there's an indication as to where the message is coming from. Change all prints to use the offset instead of the address. Signed-off-by: Joel Stanley Reviewed-by: Cédric Le Goater Reviewed-by: Philippe Mathieu-Daudé Message-ID: <20230706024528.40065

[PULL 13/60] target/ppc: Remove unneeded parameter from powerpc_reset_wakeup()

From: BALATON Zoltan CPUState is rarely needed by this function (only for logging a fatal error) and it's easy to get from the env parameter so passing it separately is not necessary. Signed-off-by: BALATON Zoltan Acked-by: Nicholas Piggin Message-ID: Signed-off-by: Daniel Henrique Barboza

[PULL 09/60] target/ppc: Fix icount access for some hypervisor instructions

From: Nicholas Piggin Several instructions and register access require icount reads and are missing translator_io_start(). Signed-off-by: Nicholas Piggin Acked-by: Richard Henderson Message-ID: <20230625103700.8992-1-npig...@gmail.com> Signed-off-by: Daniel Henrique Barboza --- target/ppc/tr

[PULL 36/60] ppc440: Add cpu link property to PCIe controller model

From: BALATON Zoltan The PCIe controller model uses PPC DCRs but cannot be modeled with TYPE_PPC4xx_DCR_DEVICE as it derives from TYPE_PCIE_HOST_BRIDGE. Add a cpu link property to it similar to other DCR devices to allow registering DCRs from the device model. Signed-off-by: BALATON Zoltan Revi

[PULL 03/60] hw/ppc: Fix clock update drift

From: Nicholas Piggin The clock update logic reads the clock twice to compute the new clock value, with a value derived from the later time subtracted from a value derived from the earlier time. The delta causes time to be lost. This can ultimately result in time becoming unsynchronized between

[PULL 45/60] ppc440_pcix: Stop using system io region for PCI bus

From: BALATON Zoltan Reduce the iomem region to 64K and use it for the PCI io space and map it directly from the board without an intermediate alias that is not really needed. Signed-off-by: BALATON Zoltan Reviewed-by: Philippe Mathieu-Daudé Message-ID: Signed-off-by: Daniel Henrique Barboza

[PULL 14/60] target/ppc: Move common check in exception handlers to a function

From: BALATON Zoltan All powerpc exception handlers share some code when handling machine check exceptions. Move this to a common function. Signed-off-by: BALATON Zoltan Reviewed-by: Nicholas Piggin Message-ID: <9cfffaa35aa894086dd092af6b0b26f2d62ff3de.1686868895.git.bala...@eik.bme.hu> Signe

[PULL 55/60] target/ppc: Move CPU QOM definitions to cpu-qom.h

From: Philippe Mathieu-Daudé Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Cédric Le Goater Message-ID: <20230627115124.19632-4-phi...@linaro.org> [dhb: keep cpu_list define in target/ppc/cpu.h] Signed-off-by: Daniel Henrique Barboza --- target/ppc/cpu-qom.h | 4 target/ppc/cpu.h

[PULL 26/60] ppc/pnv: Return zero for core thread state xscom

From: Joel Stanley Firmware now warns if booting in LPAR per core mode (PPC bit 62). So this warning doesn't trigger, report the core thread state is 0. Reviewed-by: Cédric Le Goater Signed-off-by: Joel Stanley Reviewed-by: Frederic Barrat Message-ID: <20230704054204.168547-6-j...@jms.id.au>

[PULL 08/60] sungem: Add WOL MMIO

From: Nicholas Piggin Apple sungem devices are expected to have WOL MMIO registers. Add a region to prevent transaction failures, and implement the WOL-disable CSR write because the Linux driver reset writes this. Signed-off-by: Nicholas Piggin Reviewed-by: Cédric Le Goater Reviewed-by: Joel S

[PULL 27/60] pnv/xive: Allow mmio operations of any size on the ESB CI pages

From: Frederic Barrat We currently only allow 64-bit operations on the ESB CI pages. There's no real reason for that limitation, skiboot/linux didn't need more. However the hardware supports any size, so this patch relaxes that restriction. It impacts both the ESB pages for "normal" interrupts as

[PULL 58/60] target/ppc: Remove pointless checks of CONFIG_USER_ONLY in 'kvm_ppc.h'

From: Philippe Mathieu-Daudé Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Cédric Le Goater Reviewed-by: Greg Kurz Message-ID: <20230627115124.19632-7-phi...@linaro.org> Signed-off-by: Daniel Henrique Barboza --- target/ppc/kvm_ppc.h | 5 - 1 file changed, 5 deletions(-) diff --git

[PULL 19/60] pnv/xive2: Fix TIMA offset for indirect access

From: Frederic Barrat Direct TIMA operations can be done through 4 pages, each with a different privilege level dictating what fields can be accessed. On the other hand, indirect TIMA accesses on P10 are done through a single page, which is the equivalent of the most privileged page of direct TIM

[PULL 59/60] ppc/pnv: Add QME region for P10

From: Joel Stanley The Quad Management Engine (QME) manages power related settings for its quad. The xscom region is separate from the quad xscoms, therefore a new region is added. The xscoms in a QME select a given core by selecting the forth nibble. Implement dummy reads for the stop state his

[PULL 43/60] ppc/sam460ex: Remove address_space_mem local variable

From: BALATON Zoltan Some places already use get_system_memory() directly so replace the remaining uses and drop the local variable. Signed-off-by: BALATON Zoltan Reviewed-by: Daniel Henrique Barboza Message-ID: Signed-off-by: Daniel Henrique Barboza --- hw/ppc/sam460ex.c | 8 1

[PULL 30/60] pnv/xive2: Always pass a presenter object when accessing the TIMA

From: Frederic Barrat The low-level functions to access the TIMA take a presenter object as a first argument. When accessing the TIMA from the IC BAR, i.e. indirect calls, we currently pass a NULL pointer for the presenter argument. While it appears ok with the current usage, it's dangerous. And

[PULL 31/60] target/ppc: Add LPAR-per-core vs per-thread mode flag

From: Nicholas Piggin The Power ISA has the concept of sub-processors: Hardware is allowed to sub-divide a multi-threaded processor into "sub-processors" that appear to privileged programs as multi-threaded processors with fewer threads. POWER9 and POWER10 have two modes, either every thr

[PULL 40/60] ppc440: Stop using system io region for PCIe buses

From: BALATON Zoltan Add separate memory regions for the mem and io spaces of the PCIe bus to avoid different buses using the same system io region. Signed-off-by: BALATON Zoltan Reviewed-by: Philippe Mathieu-Daudé Message-ID: Signed-off-by: Daniel Henrique Barboza --- hw/ppc/ppc440_uc.c |

[PULL 25/60] ppc/pnv: Add P10 core xscom model

From: Joel Stanley Like the quad xscoms, add a core model for P10 to allow future differentiation from P9. Signed-off-by: Joel Stanley Reviewed-by: Cédric Le Goater Reviewed-by: Frederic Barrat Message-ID: <20230704054204.168547-5-j...@jms.id.au> Signed-off-by: Daniel Henrique Barboza --- h

[PULL 52/60] target/ppc: Machine check on invalid real address access on POWER9/10

From: Nicholas Piggin ppc currently silently accepts invalid real address access. Catch these and turn them into machine checks on POWER9/10 machines. Signed-off-by: Nicholas Piggin Reviewed-by: Cédric Le Goater Message-ID: <20230703120301.45313-1-npig...@gmail.com> Signed-off-by: Daniel Henri

[PULL 56/60] target/ppc: Define TYPE_HOST_POWERPC_CPU in cpu-qom.h

From: Philippe Mathieu-Daudé TYPE_HOST_POWERPC_CPU is used in various places of cpu_init.c, in order to restrict "kvm_ppc.h" to sysemu, move this QOM-related definition to cpu-qom.h. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Cédric Le Goater Reviewed-by: Greg Kurz Message-ID: <202306

[PULL 46/60] ppc4xx_pci: Rename QOM type name define

From: BALATON Zoltan Rename the TYPE_PPC4xx_PCI_HOST_BRIDGE define and its string value to match each other and other similar types and to avoid confusion with "ppc4xx-host-bridge" type defined in same file. Signed-off-by: BALATON Zoltan Reviewed-by: Daniel Henrique Barboza Message-ID: Signe

[PULL 01/60] pnv/psi: Allow access to PSI registers through xscom

From: Frederic Barrat skiboot only uses mmio to access the PSI registers (once the BAR is set) but we don't have any reason to block the accesses through xscom. This patch enables xscom access to the PSI registers. It converts the xscom addresses to mmio addresses, which requires a bit of care fo

[PULL 50/60] ppc/pnv: Set P10 core xscom region size to match hardware

From: Nicholas Piggin The P10 core xscom memory regions overlap because the size is wrong. The P10 core+L2 xscom region size is allocated as 0x1000 (with some unused ranges). "EC" is used as a closer match, as "EX" includes L3 which has a disjoint xscom range that would require a different region

Re: [PATCH v3 5/6] qmp: Added new command to retrieve eBPF blob.

Andrew Melnychenko writes: > Added command "request-ebpf". This command returns > eBPF program encoded base64. The program taken from the > skeleton and essentially is an ELF object that can be > loaded in the future with libbpf. > > Signed-off-by: Andrew Melnychenko In review of v2, I asked wh

[PULL 22/60] ppc/pnv: quad xscom callbacks are P9 specific

From: Joel Stanley Rename the functions to include P9 in the name in preparation for adding P10 versions. Correct the unimp read message while we're changing the function. Reviewed-by: Cédric Le Goater Signed-off-by: Joel Stanley Reviewed-by: Frederic Barrat Message-ID: <20230704054204.16854

[PULL 39/60] ppc440: Rename local variable in dcr_read_pcie()

From: BALATON Zoltan Rename local variable storing state struct in dcr_read_pcie() for brevity and consistency with other functions. Signed-off-by: BALATON Zoltan Reviewed-by: Philippe Mathieu-Daudé Message-ID: <7b6f0033ada74075fc094b1397deb406e1a05741.1688586835.git.bala...@eik.bme.hu> Signe

[PULL 24/60] ppc/pnv: Add P10 quad xscom model

From: Joel Stanley Add a PnvQuad class for the P10 powernv machine. No xscoms are implemented yet, but this allows them to be added. The size is reduced to avoid the quad region from overlapping with the core region. address-space: xscom-0 -0003 (prio 0, i/o):

[PULL 11/60] pnv/xive2: Allow indirect TIMA accesses of all sizes

From: Frederic Barrat Booting linux on the powernv10 machine logs a few errors like: Invalid read at addr 0x38, size 1, region 'xive-ic-tm-indirect', reason: invalid size (min:8 max:8) Invalid write at addr 0x38, size 1, region 'xive-ic-tm-indirect', reason: invalid size (min:8 max:8) Invalid

[PULL 00/60] ppc queue

The following changes since commit 97c81ef4b8e203d9620fd46e7eb77004563e3675: Merge tag 'pull-9p-20230706' of https://github.com/cschoenebeck/qemu into staging (2023-07-06 18:19:42 +0100) are available in the Git repository at: https://gitlab.com/danielhb/qemu.git tags/pull-pp

[PULL 47/60] ppc4xx_pci: Add define for ppc4xx-host-bridge type name

From: BALATON Zoltan Add a QOM type name define for ppc4xx-host-bridge in the common header and replace direct use of the string name with the constant. Signed-off-by: BALATON Zoltan Reviewed-by: Daniel Henrique Barboza Message-ID: Signed-off-by: Daniel Henrique Barboza --- hw/ppc/ppc440_p

[PULL 12/60] target/ppc: Remove some superfluous parentheses

From: BALATON Zoltan Signed-off-by: BALATON Zoltan Acked-by: Nicholas Piggin Message-ID: <8384ed0f7335093012bbd3d28fb2a543a2e7346c.1686868895.git.bala...@eik.bme.hu> Signed-off-by: Daniel Henrique Barboza --- target/ppc/excp_helper.c | 8 1 file changed, 4 insertions(+), 4 deletions

Re: [PATCH v6] ppc: Enable 2nd DAWR support on p10

Hi Daniel and Shiva ! On Fri, 7 Jul 2023 08:09:47 -0300 Daniel Henrique Barboza wrote: > This one was a buzzer shot. > Indeed ! :-) I would have appreciated some more time to re-assess my R-b tag on this 2 year old bug though ;-) My concerns were that the DAWR1 spapr cap was still not enabled

Re: [PATCH v2 0/2] accel/tcg: Fix race condition in tb create/invalidate

On Fri, 7 Jul 2023 at 16:06, Richard Henderson wrote: > > Changes for v2: > > Adjust the change to cpu_exec_longjmp_cleanup, which should now survive > user-only testing. I'm not really happy with it. I suggested two > alternatives in the block comment, but neither of them are trivial. > > Pleas

Re: [PATCH v2 0/4] virtio-mem: Support "x-ignore-shared" migration

On 06.07.23 16:03, Michael S. Tsirkin wrote: On Thu, Jul 06, 2023 at 09:56:05AM +0200, David Hildenbrand wrote: If there is no further feedback, I'll queue this myself shortly. Stumbling over "x-ignore-shared" migration support for virtio-mem on my todo list, I remember talking to Dave G. a whi

Re: [PATCH v6] ppc: Enable 2nd DAWR support on p10

On 7/7/23 08:59, Greg Kurz wrote: Hi Daniel and Shiva ! On Fri, 7 Jul 2023 08:09:47 -0300 Daniel Henrique Barboza wrote: This one was a buzzer shot. Indeed ! :-) I would have appreciated some more time to re-assess my R-b tag on this 2 year old bug though ;-) My bad! I never thought i

[PATCH] target/riscv KVM_RISCV_SET_TIMER macro is not configured correctly

From: "yang.zhang" Should set/get riscv all reg timer,i.e, time/compare/frequency/state. Signed-off-by:Yang Zhang Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1688 --- target/riscv/kvm.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/riscv/kvm.c b/target/

Re: [PATCH v2 0/6] Add new CPU model GraniteRapids

On Fri, Jul 07, 2023 at 12:52:37PM +0200, Paolo Bonzini wrote: > Queued, thanks. Paolo, thanks! > > Paolo >

Re: [RFC PATCH] docs/interop: define STANDALONE protocol feature for vhost-user

"Michael S. Tsirkin" writes: > On Fri, Jul 07, 2023 at 08:58:00AM +0100, Alex Bennée wrote: >> >> "Michael S. Tsirkin" writes: >> >> > On Tue, Jul 04, 2023 at 01:36:00PM +0100, Alex Bennée wrote: >> >> Currently QEMU has to know some details about the back-end to be able >> >> to setup the g

[PATCH 2/4] linux-user: Fix accept4(SOCK_NONBLOCK) syscall

The accept4() syscall takes two flags only: SOCK_NONBLOCK and SOCK_CLOEXEC. Even the real Linux kernel returns -EINVAL if any other bits have been set. Change the implementation of accept4() to recognize those two values only, instead of using the fcntl_flags_tbl[] bitmask translation. Beside thi

[PATCH 4/4] linux-user: Improve strace output of pread64() and pwrite64()

Make the strace look nicer for those two syscalls. Signed-off-by: Helge Deller --- linux-user/strace.c| 19 +++ linux-user/strace.list | 4 ++-- 2 files changed, 21 insertions(+), 2 deletions(-) diff --git a/linux-user/strace.c b/linux-user/strace.c index aad2b62ca4..669200

[PATCH 1/4] linux-user: Fix fcntl64() to return O_LARGEFILE for 32-bit targets

On a 64-bit host, O_LARGEFILE has the value 0. When running a 32-bit guest on a 64-bit host, fcntl64(F_GETFL) should return with the O_LARGEFILE flag set, because the 64-bit host supports large files unconditionally. The flag translation should have happened in do_fcntl(), but since O_LARGEFILE is

[PATCH 3/4] linux-user: Fix mmap2() syscall on 32-bit targets to allow file mapping beyond 4GB

The mmap2() syscall allows 32-bit guests to specify the offset into a file in page units (instead of bytes, as done by mmap(2)). On physical machines this allows 32-bit applications to map such parts of large files which are stored beyond the 4GB limit. Allow the same behaviour when emulating 32-b

[PATCH 0/4] linux-user: Fix fcntl64() and accept4() for 32-bit targets

A set of 4 patches: The first two patches fix fcntl64() and accept4() for 32-bit targets. Patch 3 and 4 are resent here with ask to get review. They improve mmap2() for 32-bit targets and strace of pread64/pwrite64(). Helge Helge Deller (4): linux-user: Fix fcntl64() to return O_LARGEFILE for

Re: [PATCH v2 1/2] accel/tcg: Split out cpu_exec_longjmp_cleanup

On 7/7/23 12:36, Richard Henderson wrote: Share the setjmp cleanup between cpu_exec_step_atomic and cpu_exec_setjmp. Reviewed-by: Richard W.M. Jones Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé

Re: [PATCH] tcg: Fix info_in_idx increment in layout_arg_by_ref

On 7/7/23 12:29, Richard Henderson wrote: Off by one error, failing to take into account that layout_arg_1 already incremeneted info_in_idx for the first piece. We only need care for the n-1 TCG_CALL_ARG_BY_REF_N pieces here. Cc: qemu-sta...@nongnu.org Fixes: 313bdea84d2 ("tcg: Add TCG_CALL_{RE

Re: [PATCH] tcg: Fix info_in_idx increment in layout_arg_by_ref

On 7/7/23 12:29, Richard Henderson wrote: Off by one error, failing to take into account that layout_arg_1 already incremeneted info_in_idx for the first piece. We only "incremented" need care for the n-1 TCG_CALL_ARG_BY_REF_N pieces here. Cc: qemu-sta...@nongnu.org Fixes: 313bdea84d2 ("tcg

[PULL 3/9] qemu_cleanup: begin drained section after vm_shutdown()

From: Fiona Ebner in order to avoid requests being stuck in a BlockBackend's request queue during cleanup. Having such requests can lead to a deadlock [0] with a virtio-scsi-pci device using iothread that's busy with IO when initiating a shutdown with QMP 'quit'. There is a race where such a que

[PULL 1/9] python: bump minimum requirements so they are compatible with 3.12

There are many Python 3.12 issues right now, but a particularly problematic one when debugging them is that one cannot even use minreqs.txt in a Python 3.12 virtual environment to test with locked package versions. Bump the mypy and wrapt versions to fix this, while remaining within the realm of v

[PULL 6/9] target/i386: Allow MCDT_NO if host supports

From: Tao Su MCDT_NO bit indicates HW contains the security fix and doesn't need to be mitigated to avoid data-dependent behaviour for certain instructions. It needs no hypervisor support. Treat it as supported regardless of what KVM reports. Signed-off-by: Tao Su Reviewed-by: Xiaoyao Li Messa

[PULL 8/9] target/i386: Add few security fix bits in ARCH_CAPABILITIES into SapphireRapids CPU model

From: Lei Wang SapphireRapids has bit 13, 14 and 15 of MSR_IA32_ARCH_CAPABILITIES enabled, which are related to some security fixes. Add version 2 of SapphireRapids CPU model with those bits enabled also. Signed-off-by: Lei Wang Signed-off-by: Tao Su Message-ID: <20230706054949.66556-6-tao1..

[PULL 0/9] Final batch of patches for QEMU 8.1 soft freeze

The following changes since commit 97c81ef4b8e203d9620fd46e7eb77004563e3675: Merge tag 'pull-9p-20230706' of https://github.com/cschoenebeck/qemu into staging (2023-07-06 18:19:42 +0100) are available in the Git repository at: https://gitlab.com/bonzini/qemu.git tags/for-upstream for you t

[PULL 2/9] meson.build: Remove the logic to link C code with the C++ linker

From: Thomas Huth We are not mixing C++ with C code anymore, the only remaining C++ code in qga/vss-win32/ is used for a plain C++ executable. Thus we can remove the hacks for linking C code with the C++ linker now to simplify meson.build a little bit, and also to avoid that some C++ code sneaks

[PULL 9/9] target/i386: Add new CPU model GraniteRapids

From: Tao Su The GraniteRapids CPU model mainly adds the following new features based on SapphireRapids: - PREFETCHITI CPUID.(EAX=7,ECX=1):EDX[bit 14] - AMX-FP16 CPUID.(EAX=7,ECX=1):EAX[bit 21] And adds the following security fix for corresponding vulnerabilities: - MCDT_NO CPUID.(EAX=7,ECX=2):E

[PULL 5/9] target/i386: Add support for MCDT_NO in CPUID enumeration

From: Tao Su CPUID.(EAX=7,ECX=2):EDX[bit 5] enumerates MCDT_NO. Processors enumerate this bit as 1 do not exhibit MXCSR Configuration Dependent Timing (MCDT) behavior and do not need to be mitigated to avoid data-dependent behavior for certain instructions. Since MCDT_NO is in a new sub-leaf, ad

Re: [PATCH v3 2/4] QGA VSS: Replace 'fprintf(stderr' with PRINT_DEBUG

On Fri, Jul 7, 2023 at 1:34 PM Philippe Mathieu-Daudé wrote: > On 7/7/23 11:22, Konstantin Kostiuk wrote: > > Signed-off-by: Konstantin Kostiuk > > --- > > qga/vss-win32/install.cpp | 12 ++-- > > qga/vss-win32/requester.cpp | 9 + > > 2 files changed, 11 insertions(+), 10

[PULL 7/9] target/i386: Add new bit definitions of MSR_IA32_ARCH_CAPABILITIES

From: Tao Su Currently, bit 13, 14, 15 and 24 of MSR_IA32_ARCH_CAPABILITIES are disclosed for fixing security issues, so add those bit definitions. Signed-off-by: Tao Su Reviewed-by: Igor Mammedov Message-ID: <20230706054949.66556-5-tao1...@linux.intel.com> Signed-off-by: Paolo Bonzini --- t

[PULL 4/9] target/i386: Adjust feature level according to FEAT_7_1_EDX

From: Tao Su If FEAT_7_1_EAX is 0 and FEAT_7_1_EDX is non-zero, as is the case with a Granite Rapids host and '-cpu host,-avx-vnni,-avx512-bf16,-fzrm,-fsrs,-fsrc,-amx-fp16', we can't get CPUID_7_1 leaf even though CPUID_7_1_EDX has non-zero value. Update cpuid_level_func7 according to CPUID_7_1_

Re: [RFC PATCH 6/9] ui/gtk: Add a new parameter to assign connectors/monitors to GFX VCs

"Kim, Dongwon" writes: > Hi Markus, > > So I've worked on the description of this param. Can you check if this new > version looks ok? > > # @connectors:  List of physical monitor/connector names where the GTK > #           windows containing the respective graphics virtual consoles (VCs) > #   

Re: [PATCH v3 1/4] QGA VSS: Add wrapper to send log to debugger and stderr

On Fri, Jul 7, 2023 at 1:33 PM Philippe Mathieu-Daudé wrote: > On 7/7/23 11:22, Konstantin Kostiuk wrote: > > Signed-off-by: Konstantin Kostiuk > > --- > > qga/vss-win32/meson.build | 2 +- > > qga/vss-win32/vss-debug.cpp | 31 +++ > > qga/vss-win32/vss-debug.h

Re: [PATCH v6] ppc: Enable 2nd DAWR support on p10

On 7/7/23 13:59, Greg Kurz wrote: Hi Daniel and Shiva ! On Fri, 7 Jul 2023 08:09:47 -0300 Daniel Henrique Barboza wrote: This one was a buzzer shot. Indeed ! :-) I would have appreciated some more time to re-assess my R-b tag on this 2 year old bug though ;-) We should drop that patch IM

Re: [PATCH 1/2] i386: Add support for SUCCOR feature

On 7/6/23 21:40, John Allen wrote: case 0x8007: *eax = 0; -*ebx = 0; +*ebx = env->features[FEAT_8000_0007_EBX] | CPUID_8000_0007_EBX_SUCCOR; *ecx = 0; *edx = env->features[FEAT_8000_0007_EDX]; break; I agree that it needs no hype

Re: [PULL 00/60] ppc queue

ps://github.com/cschoenebeck/qemu into staging (2023-07-06 18:19:42 +0100) are available in the Git repository at: https://gitlab.com/danielhb/qemu.git tags/pull-ppc-20230707 for you to fetch changes up to 2f8ebb98ef8c7e85b23678812d8a7a95c9479673: ppc: Enable 2nd DAWR support on p10 (2023-07-07

[PULL v2 00/59] ppc queue

2 +0100) are available in the Git repository at: https://gitlab.com/danielhb/qemu.git tags/pull-ppc-20230707-1 for you to fetch changes up to bdb97596f663e9af9741353417c651f0d581de29: ppc/pnv: Add QME region for P10 (2023-07-07 06:32:53 -0300) -

Re: [PATCH v4 4/6] util/osdep: Introduce qemu_close_range()

Bin Meng writes: > This introduces a new QEMU API qemu_close_range() that closes all > open file descriptors from first to last (included). > > This API will try a more efficient call to close_range(), or walk > through of /proc/self/fd whenever these are possible, otherwise it > falls back to a

Re: [PATCH v4 5/6] util/async-teardown: Use qemu_close_range() to close fds

Bin Meng writes: > From: Zhangjin Wu > > Based on the old close_all_open_fd() of util/async-teardown.c, a new > generic qemu_close_range() has been added in osdep.c. > > Now, let's switch over to use the generic qemu_close_range(). > > Signed-off-by: Zhangjin Wu > Signed-off-by: Bin Meng > > -

Re: [PATCH v6] ppc: Enable 2nd DAWR support on p10

On 7/7/23 11:24, Cédric Le Goater wrote: On 7/7/23 13:59, Greg Kurz wrote: Hi Daniel and Shiva ! On Fri, 7 Jul 2023 08:09:47 -0300 Daniel Henrique Barboza wrote: This one was a buzzer shot. Indeed ! :-) I would have appreciated some more time to re-assess my R-b tag on this 2 year old

[PATCH v2 0/6] hw/virtio: Build vhost-vdpa.o once for all targets

v1: https://lore.kernel.org/qemu-devel/20230523163600.83391-12-phi...@linaro.org/ Since v1: - Addressed Richard's review comments - Split in multiple patches to KISS - Rename system_virtio_ss[] Philippe Mathieu-Daudé (6): hw/virtio: Propagate page_mask to vhost_vdpa_listener_skipped_sectio

[PATCH v2 2/6] hw/virtio: Propagate page_mask to vhost_vdpa_section_end()

Propagate TARGET_PAGE_MASK (see the previous commit for rationale). Signed-off-by: Philippe Mathieu-Daudé --- hw/virtio/vhost-vdpa.c | 11 ++- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/hw/virtio/vhost-vdpa.c b/hw/virtio/vhost-vdpa.c index 87653bf841..3040bd8ee8 100644

[PATCH v2 4/6] hw/virtio/vhost-vdpa: Use target-agnostic qemu_target_page_mask()

Similarly to commit e414ed2c47 ("virtio-iommu: Use target-agnostic qemu_target_page_mask"), Replace the target-specific TARGET_PAGE_SIZE and TARGET_PAGE_MASK definitions by a call to the runtime qemu_target_page_size() helper which is target agnostic. Signed-off-by: Philippe Mathieu-Daudé --- hw

[PATCH v2 5/6] hw/virtio: Build vhost-vdpa.o once

The previous commit removed the dependencies on the target-specific TARGET_PAGE_FOO macros. We can now move vhost-vdpa.c to the 'softmmu_virtio_ss' source set to build it once for all our targets. Signed-off-by: Philippe Mathieu-Daudé --- hw/virtio/meson.build | 3 ++- 1 file changed, 2 insertio

[PATCH v2 1/6] hw/virtio: Propagate page_mask to vhost_vdpa_listener_skipped_section()

In order to make vhost-vdpa.c a target-agnostic source unit, we need to remove the TARGET_PAGE_SIZE / TARGET_PAGE_MASK / TARGET_PAGE_ALIGN uses. TARGET_PAGE_SIZE will be replaced by the runtime qemu_target_page_size(). The other ones will be deduced from TARGET_PAGE_SIZE. Since the 3 macros are us

[PATCH v2 6/6] hw/virtio/meson: Rename softmmu_virtio_ss[] -> system_virtio_ss[]

Similarly to commit de6cd7599b ("meson: Replace softmmu_ss -> system_ss"), rename the virtio source set common to all system emulation as 'system_virtio_ss[]'. This is clearer because softmmu can be used for user emulation. Signed-off-by: Philippe Mathieu-Daudé --- hw/virtio/meson.build | 24 +++

[PATCH v2 3/6] hw/virtio/vhost-vdpa: Inline TARGET_PAGE_ALIGN() macro

Use TARGET_PAGE_SIZE to calculate TARGET_PAGE_ALIGN (see the rationale in previous commits). Signed-off-by: Philippe Mathieu-Daudé --- hw/virtio/vhost-vdpa.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/hw/virtio/vhost-vdpa.c b/hw/virtio/vhost-vdpa.c index 3040bd8ee8..

Re: [PATCH v2 0/2] VIRTIO-IOMMU/VFIO page size related fixes

On Wed, Jul 05, 2023 at 06:51:16PM +0200, Eric Auger wrote: > When assigning a host device and protecting it with the virtio-iommu we may > end up with qemu crashing with > > qemu-kvm: virtio-iommu page mask 0xf000 is incompatible > with mask 0x2001 > qemu: hardware err

[PATCH v3 6/7] vdpa: Avoid forwarding large CVQ command failures

Due to the size limitation of the out buffer sent to the vdpa device, which is determined by vhost_vdpa_net_cvq_cmd_len(), excessive CVQ command is truncated in QEMU. As a result, the vdpa device rejects this flawd CVQ command. However, the problem is that, the VIRTIO_NET_CTRL_MAC_TABLE_SET CVQ co

[PATCH v3 2/7] vdpa: Restore MAC address filtering state

This patch refactors vhost_vdpa_net_load_mac() to restore the MAC address filtering state at device's startup. Signed-off-by: Hawkins Jiawei --- v3: - return early if mismatch the condition suggested by Eugenio v2: https://lore.kernel.org/all/2f2560f749186c0eb1055f9926f464587e419eeb.168805125

[PATCH v3 3/7] vdpa: Restore packet receive filtering state relative with _F_CTRL_RX feature

This patch introduces vhost_vdpa_net_load_rx_mode() and vhost_vdpa_net_load_rx() to restore the packet receive filtering state in relation to VIRTIO_NET_F_CTRL_RX feature at device's startup. Signed-off-by: Hawkins Jiawei --- v3: - return early if mismatch the condition suggested by Eugenio -

[PATCH v3 5/7] vdpa: Accessing CVQ header through its structure

We can access the CVQ header through `struct virtio_net_ctrl_hdr`, instead of accessing it through a `uint8_t` pointer, which improves the code's readability and maintainability. Signed-off-by: Hawkins Jiawei --- net/vhost-vdpa.c | 5 - 1 file changed, 4 insertions(+), 1 deletion(-) diff --

[PATCH v3 4/7] vhost: Fix false positive out-of-bounds

QEMU uses vhost_svq_translate_addr() to translate addresses between the QEMU's virtual address and the SVQ IOVA. In order to validate this translation, QEMU checks whether the translated range falls within the mapped range. Yet the problem is that, the value of `needle_last`, which is calculated b

[PATCH v3 7/7] vdpa: Allow VIRTIO_NET_F_CTRL_RX in SVQ

Enable SVQ with VIRTIO_NET_F_CTRL_RX feature. Signed-off-by: Hawkins Jiawei Acked-by: Eugenio Pérez --- net/vhost-vdpa.c | 1 + 1 file changed, 1 insertion(+) diff --git a/net/vhost-vdpa.c b/net/vhost-vdpa.c index a4ff6c52b7..0994836f8c 100644 --- a/net/vhost-vdpa.c +++ b/net/vhost-vdpa.c @@ -

[PATCH v3 1/7] vdpa: Use iovec for vhost_vdpa_net_load_cmd()

According to VirtIO standard, "The driver MUST follow the VIRTIO_NET_CTRL_MAC_TABLE_SET command by a le32 number, followed by that number of non-multicast MAC addresses, followed by another le32 number, followed by that number of multicast addresses." Considering that these data is not stored in c

[PATCH v3 0/7] Vhost-vdpa Shadow Virtqueue _F_CTRL_RX commands support

This series enables shadowed CVQ to intercept rx commands related to VIRTIO_NET_F_CTRL_RX feature through shadowed CVQ, update the virtio NIC device model so qemu send it in a migration, and the restore of that rx state in the destination. Note that this patch should be based on [1] patch "vdpa: R

Re: [PATCH v3 1/4] QGA VSS: Add wrapper to send log to debugger and stderr

On 7/7/23 16:24, Konstantin Kostiuk wrote: On Fri, Jul 7, 2023 at 1:33 PM Philippe Mathieu-Daudé > wrote: On 7/7/23 11:22, Konstantin Kostiuk wrote: > Signed-off-by: Konstantin Kostiuk mailto:kkost...@redhat.com>> > --- >   qga/vss-win32/meson.buil

[PATCH] tests/tcg/s390x: Fix test-svc with clang

clang does not support expressions involving symbols in instructions like lghi yet, so building hello-s390x-asm.S with it fails. Move the expression to the literal pool and load it from there. Reported-by: Thomas Huth Fixes: be4a4cb42961 ("tests/tcg/s390x: Test single-stepping SVC") Signed-off-b

Re: [PATCH] Revert "virtio-scsi: Send "REPORTED LUNS CHANGED" sense data upon disk hotplug events"

Hi Stefano, On 7/5/2023 7:36 AM, Stefano Garzarella wrote: Hi Mark, On Wed, Jul 05, 2023 at 07:28:05AM -0500, Mark Kanda wrote: On 7/5/2023 2:15 AM, Stefano Garzarella wrote: This reverts commit 8cc5583abe6419e7faaebc9fbd109f34f4c850f2. That commit causes several problems in Linux as describ

Re: [PATCH v6] ppc: Enable 2nd DAWR support on p10

On 7/7/23 17:52, Daniel Henrique Barboza wrote: On 7/7/23 08:59, Greg Kurz wrote: Hi Daniel and Shiva ! On Fri, 7 Jul 2023 08:09:47 -0300 Daniel Henrique Barboza wrote: This one was a buzzer shot. Indeed ! :-) I would have appreciated some more time to re-assess my R-b tag on this 2 yea

Re: [PATCH v6] ppc: Enable 2nd DAWR support on p10

On 7/7/23 19:54, Cédric Le Goater wrote: On 7/7/23 13:59, Greg Kurz wrote: Hi Daniel and Shiva ! On Fri, 7 Jul 2023 08:09:47 -0300 Daniel Henrique Barboza wrote: This one was a buzzer shot. Indeed ! :-) I would have appreciated some more time to re-assess my R-b tag on this 2 year old b

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