On 7/4/23 16:49, Philippe Mathieu-Daudé wrote:
Following docs/devel/style.rst guidelines, rename arm_timer_state
as ArmTimer.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Peter Maydell
---
hw/timer/arm_timer.c | 30 +++---
1 file changed, 15 insertions(+), 15 del
On 7/4/23 16:50, Philippe Mathieu-Daudé wrote:
Having a QOM object using its device type as suffix is
often helpful.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/timer/arm_timer.c | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
Reviewed-by: Richard Henderson
r~
On 7/4/23 16:49, Philippe Mathieu-Daudé wrote:
Following docs/devel/style.rst guidelines, rename SP804State
as SP804Timer.
Suggested-by: Peter Maydell
Signed-off-by: Philippe Mathieu-Daudé
---
hw/timer/arm_timer.c | 22 +++---
1 file changed, 11 insertions(+), 11 deletions(-)
On 7/4/23 16:50, Philippe Mathieu-Daudé wrote:
Extract arm_timer_reset_hold() before converting this model to
QOM/QDev in few commits. This will become our ResettableHoldPhase
handler.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/timer/arm_timer.c | 9 -
1 file changed, 8 insertions(+
On 7/4/23 16:50, Philippe Mathieu-Daudé wrote:
In order to simplify the QOM convertion of ARM_TIMER in a few
commits, start converting the read/write() handlers to follow
the MemoryRegionOps::read/write() prototypes.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/timer/arm_timer.c | 16 -
On 7/4/23 16:50, Philippe Mathieu-Daudé wrote:
QDev models often use foo_new() as the combination of
foo_init() + foo_realize(). Here arm_timer_init() is
a such combination, so rename it as arm_timer_new() to
emphasis the returned device is already realized.
Signed-off-by: Philippe Mathieu-Daudé
On 7/4/23 16:50, Philippe Mathieu-Daudé wrote:
In preparation of accessing ArmTimer::freq as a QOM property,
convert it to uint32_t (so we'll be able to use DEFINE_PROP_UINT32).
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Peter Maydell
---
hw/timer/arm_timer.c | 2 +-
1 file changed, 1
On 7/4/23 16:50, Philippe Mathieu-Daudé wrote:
SP804Timer use arrays for timers and IRQ levels. Be consistent
and use another one for the frequencies. This will allow to
simplify using for() loop statement in the next commit.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Peter Maydell
---
On 7/4/23 16:50, Philippe Mathieu-Daudé wrote:
The same pattern is used for each timer, 2 or 3 times. To avoid
too much code churn in the next commits, iterate on the number
of timers using a for() loop statement.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Peter Maydell
---
hw/timer/ar
On 7/4/23 16:50, Philippe Mathieu-Daudé wrote:
Both SP804Timer/IntegratorPIT peek at ArmTimer internal state.
This is fine so far but we want to convert ArmTimer to QOM
where peeking at QOM state internal should be avoided.
ArmTimer's IRQ is just a pointer, so we can pass/set it via
argument, avo
On 7/4/23 16:50, Philippe Mathieu-Daudé wrote:
SysBus IRQ are*output* IRQs. As some sort of simplification
to avoid to forward it, IntegratorPIT misuses it as ARM timer
input IRQ. Fix that by using a simple IRQ forwarder handler.
Note: sysbus_pass_irq() forwards GPIOs and IRQs from a container
On 7/4/23 16:50, Philippe Mathieu-Daudé wrote:
To make the next commit easier to digest, extract icp_pit_realize()
from icp_pit_init() as a preliminary step.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/timer/arm_timer.c | 21 +++--
1 file changed, 19 insertions(+), 2 deletion
This patch breaks make check-qtest:
$ make -j -C build && make -C build check-qtest
(...)
16/44 qemu:qtest+qtest-ppc64 / qtest-ppc64/pnv-xscom-test ERROR
0.89s killed by signal 6 SIGABRT
G_TEST_DBUS_DAEMON=/home/danielhb/powerpc/qemu/tests/dbus-vmstate-daemon.sh
QT
On 7/4/23 16:50, Philippe Mathieu-Daudé wrote:
Instead of manually forwarding MMIO accesses to each ARM_TIMER,
let have the generic memory code dispatch that for us.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/timer/arm_timer.c | 43 ---
1 file changed
On 7/4/23 16:50, Philippe Mathieu-Daudé wrote:
Instead of manually forwarding MMIO accesses to each ARM_TIMER,
let have the generic memory code dispatch that for us.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/timer/arm_timer.c | 23 ++-
1 file changed, 2 insertions(+), 2
On 7/5/23 14:10, Pierrick Bouvier wrote:
Support for execveat syscall was implemented in 55bbe4 and is available
since QEMU 8.0.0. It relies on host execveat, which is widely available
on most of Linux kernels today.
However, this change breaks qemu-user self emulation, if "host" qemu
version is
This v4 patchset is based on master. Since I'm not sure how long this
series will take for review, we could probably apply Dan's previous patch
10 first, then when I repost I can provide a revert patch when needed.
v4:
- Remove one unused var (accident after the rebase..)
v3:
- Rebase only (v2 is
This solution is heavily based on Daniel's original approach here, but
hopefully a cleaner way to impl:
https://lore.kernel.org/r/20230601161347.1803440-11-berra...@redhat.com
The difference is we use the switchover-hold flag rather than tuning
bw+downtime to guide test convergence, comparing to
Add a new migration parameter switchover-hold which can block src qemu
migration from switching over to dest from running.
One can set this flag to true so src qemu will keep iterating the VM data,
not switching over to dest even if it can.
It means now live migration works somehow like COLO; we
v2:
- Patch "migration: Provide explicit error message for file shutdowns"
- Touched up qapi doc [Fabiano]
- Added Bugzilla link to commit which I didn't even notice that I was
fixing a bug.. but rightfully pointed out by Laszlo.
- Moved it to the 1st patch because it fixes a bug, please
rp_state.error was a boolean used to show error happened in return path
thread. That's not only duplicating error reporting (migrate_set_error),
but also not good enough in that we only do error_report() and set it to
true, we never can keep a history of the exact error and show it in
query-migrat
Introduce a helper to detect whether MigrationState.error is set for
whatever reason. It is intended to not taking the error_mutex here because
neither do we reference the pointer, nor do we modify the pointer. State
why it's safe to do so.
This is preparation work for any thread (e.g. source re
migrate_set_error() used one error_copy() so it always copy an error.
However that's not the major use case - the major use case is one would
like to pass the error to migrate_set_error() without further touching the
error.
It can be proved if we see most of the callers are freeing the error
expli
We've already did this for most of the return path thread errors, but not
yet for the IO errors happened on the return path qemufile. Do that too.
Remember to reset "err" always, because the ownership is not us anymore,
otherwise we're prone to use-after-free later after recovered.
Reviewed-by:
There're a lot of cases where we only have an errno set in last_error but
without a detailed error description. When this happens, try to generate
an error contains the errno as a descriptive error.
This will be helpful in cases where one relies on the Error*. E.g.,
migration state only caches E
Display it as long as being set, irrelevant of FAILED status. E.g., it may
also be applicable to PAUSED stage of postcopy, to provide hint on what has
gone wrong.
The error_mutex seems to be overlooked when referencing the error, add it
to be very safe.
Bugzilla: https://bugzilla.redhat.com/show
On 7/5/2023 6:42 AM, Alex Bennée wrote:
zhanghao1 writes:
Each vcpu creates a corresponding timer task. The watchdog
is driven by a timer according to a certain period. Each time
the timer expires, the counter is decremented. When the counter
is "0", the watchdog considers the vcpu to be stal
Provide an explicit reason for qemu_file_shutdown()s, which can be
displayed in query-migrate when used.
This will make e.g. migrate-pause to display explicit error descriptions,
from:
"error-desc": "Channel error: Input/output error"
To:
"error-desc": "Channel is explicitly shutdown by the use
I believe it might have been master unstable branch. Last commit before my
patches was:
commit 19a720b74fde7e859d19f12c66a72e545947a657
Merge: c6a5fc2ac7 367189efae
Author: Richard Henderson
Date: Thu Jun 1 08:30:29 2023 -0700
-Joel
On Thu, Jun 22, 2023 at 1:11 PM Bernhard Beschow wrote:
>
When assigning a host device and protecting it with the virtio-iommu we may
end up with qemu crashing with
qemu-kvm: virtio-iommu page mask 0xf000 is incompatible
with mask 0x2001
qemu: hardware error: vfio: DMA mapping failed, unable to continue
This happens if the ho
When running on a 64kB page size host and protecting a VFIO device
with the virtio-iommu, qemu crashes with this kind of message:
qemu-kvm: virtio-iommu page mask 0xf000 is incompatible
with mask 0x2001
qemu: hardware error: vfio: DMA mapping failed, unable to continue
This is due
The current error messages in virtio_iommu_set_page_size_mask()
sound quite similar for different situations and miss the IOMMU
memory region that causes the issue.
Clarify them and rework the comment.
Also remove the trace when the new page_size_mask is not applied as
the current frozen granule
Queued in gitlab.com/danielhb/qemu/tree/ppc-next. Thanks,
Daniel
On 7/5/23 08:00, Frederic Barrat wrote:
Add the CPU target in the trace when reading/writing the TIMA
space. It was already done for other TIMA ops (notify, accept, ...),
only missing for those 2. Useful for debug and even more n
Queued in gitlab.com/danielhb/qemu/tree/ppc-next. Thanks,
Daniel
On 7/5/23 09:06, Nicholas Piggin wrote:
These patches implement enough to install a distro, boot, run SMP KVM
guests with libvirt with good performance using MTTCG (as reported by
Cedric).
There are a few more SPRs that need to
Queued in gitlab.com/danielhb/qemu/tree/ppc-next. Thanks,
Daniel
On 7/5/23 05:14, Frederic Barrat wrote:
The low-level functions to access the TIMA take a presenter object as
a first argument. When accessing the TIMA from the IC BAR,
i.e. indirect calls, we currently pass a NULL pointer for th
On Tue, Jun 27, 2023 at 8:36 AM Si-Wei Liu wrote:
>
>
>
> On 6/9/2023 7:32 AM, Eugenio Perez Martin wrote:
> > On Fri, Jun 9, 2023 at 12:39 AM Si-Wei Liu wrote:
> >>
> >> On 6/7/23 01:08, Eugenio Perez Martin wrote:
> >>> On Wed, Jun 7, 2023 at 12:43 AM Si-Wei Liu wrote:
> Sorry for revivin
The TLS handshake make take some time to complete, during which time an
I/O watch might be registered with the main loop. If the owner of the
I/O channel invokes qio_channel_close() while the handshake is waiting
to continue the I/O watch must be removed. Failing to remove it will
later trigger the
HI Leo,
On 7/2/23 11:14 PM, Leo Yan wrote:
Hi Vikram,
On Thu, Jun 29, 2023 at 10:43:10AM -0700, Oleksandr Tyshchenko wrote:
[...]
void arch_handle_ioreq(XenIOState *state, ioreq_t *req)
{
hw_error("Invalid ioreq type 0x%x\n", req->type);
@@ -135,6 +170,14 @@ static void xen_arm_ini
As docs/devel/loads-stores.rst states:
``GETPC()`` should be used with great care: calling
it in other functions that are *not* the top level
``HELPER(foo)`` will cause unexpected behavior. Instead, the
value of ``GETPC()`` should be read from the helper and passed
if needed to the funct
On 7/5/23 11:23 AM, Cédric Le Goater wrote:
> It is useful to extend the number of available PCI devices to KVM guests
> for passthrough scenarios and also to expose these models to a different
> (big endian) architecture. Include models for Intel Ethernet adapters
> and one USB controller, which a
On 03/07/2023 09:26, Philippe Mathieu-Daudé wrote:
On 2/7/23 17:48, Mark Cave-Ayland wrote:
Signed-off-by: Mark Cave-Ayland
---
hw/block/swim.c | 14 ++
hw/block/trace-events | 7 +++
2 files changed, 21 insertions(+)
@@ -267,6 +275,7 @@ static void iwmctrl_write(
On 7/5/23 10:41, Andrew Jones wrote:
On Fri, Jun 30, 2023 at 07:08:05AM -0300, Daniel Henrique Barboza wrote:
Let's add KVM user properties for the multi-letter extensions that KVM
currently supports: zicbom, zicboz, zihintpause, zbb, ssaia, sstc,
svinval and svpbmt.
As with MISA extensions,
On 03/07/2023 09:30, Philippe Mathieu-Daudé wrote:
On 2/7/23 17:48, Mark Cave-Ayland wrote:
The MacOS toolbox ROM calculates the number of branches that can be executed
per millisecond as part of its timer calibration. Since modern hosts are
considerably quicker than original hardware, the nega
Hi Sittisak,
Minipack3 is not open-sourced yet, and we are unlikely to be able to upstream
detailed data.
1. What is these FRUID datas for, is it for testing?
2. What other option do we have, since we are not able to upstream FRUID
data. (It is still OK to upstream system configuration,
Change parameter of ppc460ex_pcie_init() from env to cpu to allow
further refactoring.
Signed-off-by: BALATON Zoltan
Reviewed-by: Philippe Mathieu-Daudé
---
hw/ppc/ppc440.h| 2 +-
hw/ppc/ppc440_uc.c | 7 ---
hw/ppc/sam460ex.c | 2 +-
3 files changed, 6 insertions(+), 5 deletions(-)
di
These are some small misc clean ups to PPC440 related device models
which is all I have ready for now.
v2:
- Added R-b tags from Philippe
- Addressed review comments
- Added new patch to rename parent field of PPC460EXPCIEState to parent_obj
Patches needing review: 6 7 10-13
BALATON Zoltan (14):
Rename TYPE_PPC440_PCIX_HOST_BRIDGE to better match its string value,
move it to common header and use it also in sam460ex to replace hard
coded type name.
Signed-off-by: BALATON Zoltan
---
hw/ppc/ppc440_pcix.c| 9 -
hw/ppc/sam460ex.c | 2 +-
include/hw/ppc/ppc4xx.h | 1 +
3 fi
Reduce the iomem region to 64K and use it for the PCI io space and map
it directly from the board without an intermediate alias that is not
really needed.
Signed-off-by: BALATON Zoltan
Reviewed-by: Philippe Mathieu-Daudé
---
hw/ppc/ppc440_pcix.c | 9 ++---
hw/ppc/sam460ex.c| 6 +-
2
Instead of guessing controller number from dcrn_base add a property so
the device does not need knowledge about where it is used.
Signed-off-by: BALATON Zoltan
Reviewed-by: Philippe Mathieu-Daudé
---
hw/ppc/ppc440_uc.c | 25 +++--
1 file changed, 11 insertions(+), 14 deletio
Add separate memory regions for the mem and io spaces of the PCIe bus
to avoid different buses using the same system io region.
Signed-off-by: BALATON Zoltan
---
hw/ppc/ppc440_uc.c | 9 ++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/hw/ppc/ppc440_uc.c b/hw/ppc/ppc440_uc.
Rename local variable storing state struct in dcr_read_pcie() for
brevity and consistency with other functions.
Signed-off-by: BALATON Zoltan
Reviewed-by: Philippe Mathieu-Daudé
---
hw/ppc/ppc440_uc.c | 50 +++---
1 file changed, 25 insertions(+), 25 dele
The iomem memory region is better used for the PCI IO space but
currently used for registers. Stop using it for that to allow this to
be cleaned up in the next patch.
Signed-off-by: BALATON Zoltan
---
hw/ppc/ppc440_pcix.c | 7 ---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a
Rename the TYPE_PPC4xx_PCI_HOST_BRIDGE define and its string value to
match each other and other similar types and to avoid confusion with
"ppc4xx-host-bridge" type defined in same file.
Signed-off-by: BALATON Zoltan
---
hw/ppc/ppc440_bamboo.c | 3 +--
hw/ppc/ppc4xx_pci.c | 6 +++---
includ
Some places already use get_system_memory() directly so replace the
remaining uses and drop the local variable.
Signed-off-by: BALATON Zoltan
---
hw/ppc/sam460ex.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/hw/ppc/sam460ex.c b/hw/ppc/sam460ex.c
index aaa8d2f4a5.
The PCIe controller model uses PPC DCRs but cannot be modeled with
TYPE_PPC4xx_DCR_DEVICE as it derives from TYPE_PCIE_HOST_BRIDGE. Add a
cpu link property to it similar to other DCR devices to allow
registering DCRs from the device model.
Signed-off-by: BALATON Zoltan
Reviewed-by: Philippe Mathi
It is shorter and more readable to wrap the complex call to
ppc_dcr_register() in a macro than to repeat it several times.
Signed-off-by: BALATON Zoltan
Reviewed-by: Philippe Mathieu-Daudé
---
hw/ppc/ppc440_uc.c | 76 +-
1 file changed, 28 insertions(
Add a QOM type name define for ppc4xx-host-bridge in the common header
and replace direct use of the string name with the constant.
Signed-off-by: BALATON Zoltan
---
hw/ppc/ppc440_pcix.c| 3 ++-
hw/ppc/ppc4xx_pci.c | 4 ++--
include/hw/ppc/ppc4xx.h | 1 +
3 files changed, 5 insertions(+)
After previous changes we can now remove the legacy init function and
move the device creation to board code.
Signed-off-by: BALATON Zoltan
Reviewed-by: Philippe Mathieu-Daudé
---
hw/ppc/ppc440.h | 1 -
hw/ppc/ppc440_uc.c | 21 -
hw/ppc/sam460ex.c | 17 ++
QOM prefers to call the parent field parent_obj, change
PPC460EXPCIEState ro match that convention.
Signed-off-by: BALATON Zoltan
Reviewed-by: Philippe Mathieu-Daudé
---
hw/ppc/ppc440_uc.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/ppc/ppc440_uc.c b/hw/ppc/ppc440_uc.
On Wed, 5 Jul 2023, BALATON Zoltan wrote:
These are some small misc clean ups to PPC440 related device models
which is all I have ready for now.
Sorry, typo in email addresses in cc. Should I send it again or you can
pick up from the list?
Regards,
BALATON Zoltan
v2:
- Added R-b tags from
On 5/7/23 17:23, Cédric Le Goater wrote:
It is useful to extend the number of available PCI devices to KVM guests
for passthrough scenarios and also to expose these models to a different
(big endian) architecture. Include models for Intel Ethernet adapters
and one USB controller, which all suppor
On 5/7/23 22:12, BALATON Zoltan wrote:
The iomem memory region is better used for the PCI IO space but
currently used for registers. Stop using it for that to allow this to
be cleaned up in the next patch.
Signed-off-by: BALATON Zoltan
---
hw/ppc/ppc440_pcix.c | 7 ---
1 file changed, 4
On 5/7/23 22:12, BALATON Zoltan wrote:
Add separate memory regions for the mem and io spaces of the PCIe bus
to avoid different buses using the same system io region.
Signed-off-by: BALATON Zoltan
---
hw/ppc/ppc440_uc.c | 9 ++---
1 file changed, 6 insertions(+), 3 deletions(-)
Reviewe
Hi Konstantin,
On 5/7/23 16:12, Konstantin Kostiuk wrote:
Signed-off-by: Konstantin Kostiuk
---
qga/vss-win32/vss-debug.h | 31 +++
1 file changed, 31 insertions(+)
create mode 100644 qga/vss-win32/vss-debug.h
+#define PRINT_DEBUG(fmt, ...) {
On 5/7/23 16:12, Konstantin Kostiuk wrote:
Signed-off-by: Konstantin Kostiuk
---
qga/vss-win32/install.cpp | 13 +++--
qga/vss-win32/requester.cpp | 9 +
2 files changed, 12 insertions(+), 10 deletions(-)
diff --git a/qga/vss-win32/install.cpp b/qga/vss-win32/install.cpp
Richard Henderson writes:
> On 7/4/23 17:44, Peter Maydell wrote:
>>> IIUC tcg_enabled(), this guard shouldn't be necessary; if CONFIG_TCG
>>> is not defined, tcg_enabled() evaluates to 0, and the compiler should
>>> elide the whole block.
>>
>> IME it's a bit optimistic to assume that the compi
Peter Xu writes:
> migrate_set_error() used one error_copy() so it always copy an error.
> However that's not the major use case - the major use case is one would
> like to pass the error to migrate_set_error() without further touching the
> error.
>
> It can be proved if we see most of the calle
Peter Xu writes:
> Introduce a helper to detect whether MigrationState.error is set for
> whatever reason. It is intended to not taking the error_mutex here because
> neither do we reference the pointer, nor do we modify the pointer. State
> why it's safe to do so.
>
> This is preparation work
AF_XDP is a network socket family that allows communication directly
with the network device driver in the kernel, bypassing most or all
of the kernel networking stack. In the essence, the technology is
pretty similar to netmap. But, unlike netmap, AF_XDP is Linux-native
and works with any networ
On 6/7/2023 11:58 AM, Peter Xu wrote:
> On Wed, Jun 07, 2023 at 07:35:32AM -0700, Steve Sistare wrote:
>> Modify migrate_add_blocker and migrate_del_blocker to take an Error **
>> reason. This allows migration to own the Error object, so that if
>> an error occurs, migration code can free the Erro
Following the same logic used with 'mvendorid' let's also restrict
'mimpid' for named CPUs. Generic CPUs keep setting the value freely.
Note that we're getting rid of the default RISCV_CPU_MARCHID value. The
reason is that this is not a good default since it's dynamic, changing
with with every QEM
As it is today it's not possible to use '-cpu host' if the RISC-V host
has RVH enabled. This is the resulting error:
$ ./qemu/build/qemu-system-riscv64 \
-machine virt,accel=kvm -m 2G -smp 1 \
-nographic -snapshot -kernel ./guest_imgs/Image \
-initrd ./guest_imgs/rootfs_kvm_riscv64.im
Using all TCG user properties in KVM is tricky. First because KVM
supports only a small subset of what TCG provides, so most of the
cpu->cfg flags do nothing for KVM.
Second, and more important, we don't have a way of telling if any given
value is an user input or not. For TCG this has a small imp
KVM-specific properties are being created inside target/riscv/kvm.c. But
at this moment we're gathering all the remaining properties from TCG and
adding them as is when running KVM. This creates a situation where
non-KVM properties are setting flags to 'true' due to its default
settings (e.g. Zawr
Next patch will add KVM specific user properties for both MISA and
multi-letter extensions. For MISA extensions we want to make use of what
is already available in misa_ext_cfgs[] to avoid code repetition.
misa_ext_info_arr[] array will hold name and description for each MISA
extension that misa_e
We're now ready to update the multi-letter extensions status for KVM.
kvm_riscv_update_cpu_cfg_isa_ext() is called called during vcpu creation
time to verify which user options changes host defaults (via the 'user_set'
flag) and tries to write them back to KVM.
Failure to commit a change to KVM i
'marchid' shouldn't be set to a different value as previously set for
named CPUs.
For all other CPUs it shouldn't be freely set either - the spec requires
that 'marchid' can't have the MSB (most significant bit) set and every
other bit set to zero, i.e. 0x8000 is an invalid 'marchid' value for
Allow 'marchid' and 'mimpid' to also be initialized in
kvm_riscv_init_machine_ids().
After this change, the handling of mvendorid/marchid/mimpid for the
'host' CPU type will be equal to what we already have for TCG named
CPUs, i.e. the user is not able to set these values to a different val
than t
Certain validations, such as the validations done for the machine IDs
(mvendorid/marchid/mimpid), are done before starting the CPU.
Non-dynamic (named) CPUs tries to match user input with a preset
default. As it is today we can't prefetch a KVM default for these cases
because we're only able to rea
riscv_isa_string_ext() is being used by riscv_isa_string(), which is
then used by boards to retrieve the 'riscv,isa' string to be written in
the FDT. All this happens after riscv_cpu_realize(), meaning that we're
already past riscv_cpu_validate_set_extensions() and, more important,
riscv_cpu_disabl
On 7/5/2023 5:33 PM, Steven Sistare wrote:
> On 6/7/2023 11:58 AM, Peter Xu wrote:
>> On Wed, Jun 07, 2023 at 07:35:32AM -0700, Steve Sistare wrote:
>>> Modify migrate_add_blocker and migrate_del_blocker to take an Error **
>>> reason. This allows migration to own the Error object, so that if
>>>
riscv_cpu_add_user_properties() ended up with an excess of "#ifndef
CONFIG_USER_ONLY" blocks after changes that added KVM properties
handling.
KVM specific properties are required to be created earlier than their
TCG counterparts, but the remaining props can be created at any order.
Move riscv_add
There are 2 places in which we need to get a pointer to a certain
property of the cpu->cfg struct based on property offset. Next patch
will add a couple more.
Create a helper to avoid repeating this code over and over.
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Andrew Jones
---
target
After changing user validation for mvendorid/marchid/mimpid to guarantee
that the value is validated on user input time, coupled with the work in
fetching KVM default values for them by using a scratch CPU, we're
certain that the values in cpu->cfg.(mvendorid|marchid|mimpid) are
already good to be
Update to commit ac9a78681b92 ("Linux 6.4-rc1").
Signed-off-by: Daniel Henrique Barboza
Acked-by: Alistair Francis
---
include/standard-headers/linux/const.h| 2 +-
include/standard-headers/linux/virtio_blk.h | 18 +++
.../standard-headers/linux/virtio_config.h| 6 +++
inclu
At this moment we're retrieving env->misa_ext during
kvm_arch_init_cpu(), leaving env->misa_ext_mask behind.
We want to set env->misa_ext_mask, and we want to set it as early as
possible. The reason is that we're going to use it in the validation
process of the KVM MISA properties we're going to a
The absence of a satp mode in riscv_host_cpu_init() is causing the
following error:
$ ./qemu/build/qemu-system-riscv64 -machine virt,accel=kvm \
-m 2G -smp 1 -nographic -snapshot \
-kernel ./guest_imgs/Image \
-initrd ./guest_imgs/rootfs_kvm_riscv64.img \
-append "earlycon=sbi ro
Our design philosophy with KVM properties can be resumed in two main
decisions based on KVM interface availability and what the user wants to
do:
- if the user disables an extension that the host KVM module doesn't
know about (i.e. it doesn't implement the kvm_get_one_reg() interface),
keep bootin
We're going to change the handling of mvendorid/marchid/mimpid by the
KVM driver. Since these are always present in all CPUs let's put the
same validation for everyone.
It doesn't make sense to allow 'mvendorid' to be different than it
is already set in named (vendor) CPUs. Generic (dynamic) CPUs
If we don't set a proper cbom_blocksize|cboz_blocksize in the FDT the
Linux Kernel will fail to detect the availability of the CBOM/CBOZ
extensions, regardless of the contents of the 'riscv,isa' DT prop.
The FDT is being written using the cpu->cfg.cbom|z_blocksize attributes,
so let's expose them
's riscv-to-apply.next.
Patches missing review: 14
Changes from v7:
- Patch 14:
- use 'errno' to check the error code from ioctl()
- test for ENOENT instead of EINVAL
- v7 link:
https://lore.kernel.org/qemu-devel/20230630100811.287315-1-dbarb...@ventanamicro.com/
[1] https://
Let's add KVM user properties for the multi-letter extensions that KVM
currently supports: zicbom, zicboz, zihintpause, zbb, ssaia, sstc,
svinval and svpbmt.
As with MISA extensions, we're using the KVMCPUConfig type to hold
information about the state of each extension. However, multi-letter
exte
p, as the
generic binding sets out no requirements. I think you would want to link
to the RISC-V specific cpus binding.
That said, things like FreeBSD and U-Boot appear to require mmu-type
https://lore.kernel.org/all/20230705-fondue-bagginess-66c25f1a4135@spud/
so I am wondering if we should in fac
Am 5. Juli 2023 10:01:21 UTC schrieb Olaf Hering :
>Tue, 4 Jul 2023 08:38:33 +0200 Paolo Bonzini :
>
>> I agree that calling pci_device_reset() would be a better match for
>> pci_xen_ide_unplug().
>
>This change works as well:
Nice!
>
>--- a/hw/i386/xen/xen_platform.c
>+++ b/hw/i386/xen/xen_p
Peter Xu writes:
> There're a lot of cases where we only have an errno set in last_error but
> without a detailed error description. When this happens, try to generate
> an error contains the errno as a descriptive error.
>
> This will be helpful in cases where one relies on the Error*. E.g.,
>
cific cpus binding.
You mean this link?
https://github.com/torvalds/linux/blob/master/Documentation/devicetree/bindings/riscv/cpus.yaml
That said, things like FreeBSD and U-Boot appear to require mmu-type
https://lore.kernel.org/all/20230705-fondue-bagginess-66c25f1a4135@spud/
so I am wo
Peter Xu writes:
> Provide an explicit reason for qemu_file_shutdown()s, which can be
> displayed in query-migrate when used.
>
Can we consider this to cover the TODO:
* TODO: convert to propagate Error objects instead of squashing
* to a fixed errno value
or would that need something fancie
g.
>
> You mean this link?
>
> https://github.com/torvalds/linux/blob/master/Documentation/devicetree/bindings/riscv/cpus.yaml
Yeah, that's the correct file. Should probably have linked it, sorry
about that. And in case it was not clear, not suggesting that this would
require a re
> -Original Message-
> From: Matheus Tavares Bernardino
> Sent: Wednesday, July 5, 2023 12:35 PM
> To: qemu-devel@nongnu.org
> Cc: quic_mathb...@quicinc.com; bc...@quicinc.com;
> ltaylorsimp...@gmail.com; quic_mlie...@quicinc.com;
> richard.hender...@linaro.org
> Subject: [PATCH v2] Hex
eal gentlemann and amend the
commit msg for us :D
That said, things like FreeBSD and U-Boot appear to require mmu-type
https://lore.kernel.org/all/20230705-fondue-bagginess-66c25f1a4135@spud/
so I am wondering if we should in fact make the mmu-type a required
property in the RISC-V specific bind
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