When running on a 64kB page size host and protecting a VFIO device
with the virtio-iommu, qemu crashes with this kind of message:
qemu-kvm: virtio-iommu page mask 0xf000 is incompatible
with mask 0x2001
qemu: hardware error: vfio: DMA mapping failed, unable to continue
This is due
The current error messages in virtio_iommu_set_page_size_mask()
sound quite similar for different situations and miss the IOMMU
memory region that causes the issue.
Clarify them and rework the comment.
Also remove the trace when the new page_size_mask is not applied as
the current frozen granule
When assigning a host device and protecting it with the virtio-iommu we may
end up with qemu crashing with
qemu-kvm: virtio-iommu page mask 0xf000 is incompatible
with mask 0x2001
qemu: hardware error: vfio: DMA mapping failed, unable to continue
This happens if the ho
On 7/4/23 12:57, Sittisak Sinprem wrote:
Hi Cédric,
Please stop this patch,
after the test, the eeprom content is incorrect,
root@bmc:~# weutil -l
bmc_eeprom /sys/bus/i2c/devices/i2c-8/8-0051/eeprom
chassis_eeprom /sys/bus/i2c/devices/i2c-6/6-0053/eeprom
dummy_eeprom /etc/weutil/meta_e
On 7/4/23 13:06, ~ssinprem wrote:
From: Sittisak Sinprem
- I2C list follow I2C Tree v1.6 20230320
- fru eeprom data use FB FRU format version 4
Signed-off-by: Sittisak Sinprem
You shoot too fast :) Please add some description for the EEPROM contents.
What they enable when the OS/FW boots is
On Monday, July 3, 2023 4:50:42 PM CEST Greg Kurz wrote:
> On Mon, 3 Jul 2023 16:34:17 +0200
> Christian Schoenebeck wrote:
>
> > Change status of 9p from 'Odd Fixes' to 'Maintained', as this better
> > reflects current situation. I already take care of 9p patches for a
> > while, which included
Patches 1-4:
Fix tests so that devices do not use non-zero slots on the pcie root
ports. PCIE ports only have one slot, so PCIE devices can only be
plugged into slot 0 on a PCIE port.
Patch 5:
Enforce only one slot on PCIE port.
Patch 6: add a cosmetic comment addition for better clarity of the c
We are going to fix bio-tables-test in the next patch and hence need to
make sure the acpi tests continue to pass.
Signed-off-by: Ani Sinha
Acked-by: Igor Mammedov
---
tests/qtest/bios-tables-test-allowed-diff.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/tests/qtest/bios-tables-test-al
PCIE ports only have one slot, slot 0. Hence, non-zero slots are not available
for PCIE devices on PCIE root ports. Fix test_acpi_q35_tcg_no_acpi_hotplug()
so that the test does not use them.
Signed-off-by: Ani Sinha
Reviewed-by: Igor Mammedov
---
tests/qtest/bios-tables-test.c | 4 ++--
1 file
The test attaches a SCSI controller to a non-zero slot and a pcie-to-pci bridge
on slot 0 on the same pcie-root-port. Since a downstream device can be attached
to a pcie-root-port only on slot 0, the above test configuration is not allowed.
Additionally using pcie.0 as id for pcie-to-pci bridge is
This change is cosmetic. A comment is added explaining why we need to check for
the availability of function 0 when we hotplug a device.
CC: m...@redhat.com
Signed-off-by: Ani Sinha
---
hw/pci/pci.c | 12 +---
1 file changed, 9 insertions(+), 3 deletions(-)
diff --git a/hw/pci/pci.c b/h
PCI Express ports only have one slot, so PCI Express devices can only be
plugged into slot 0 on a PCIE port. Add a warning to let users know when the
invalid configuration is used. We may enforce this more strongly later on once
we get more clarity on whether we are introducing a bad regression for
Some fixes were committed in bios-tables-test in the previous commit. Update
the acpi blob and clear bios-tables-test-allowed-diff.h so that the test
continues to pass with the changes in the bios-tables-test.
Following is the asl diff between the old and the newly updated blob:
@@ -1,30 +1,30 @@
On Sat, 1 Jul 2023 16:28:30 +0900
Akihiko Odaki wrote:
> On 2023/07/01 0:29, Michael S. Tsirkin wrote:
> > On Fri, Jun 30, 2023 at 08:36:38PM +0900, Akihiko Odaki wrote:
> >> On 2023/06/30 19:37, Ani Sinha wrote:
> >>>
> >>>
> On 30-Jun-2023, at 3:30 PM, Michael S. Tsirkin wrote:
> >>
> On 04-Jul-2023, at 4:55 PM, Ani Sinha wrote:
>
> PCI Express ports only have one slot, so PCI Express devices can only be
> plugged into slot 0 on a PCIE port. Add a warning to let users know when the
> invalid configuration is used. We may enforce this more strongly later on once
> we get m
On 30/06/2023 11.17, Pierre Morel wrote:
On interception of STSI(15.1.x) the System Information Block
(SYSIB) is built from the list of pre-ordered topology entries.
Signed-off-by: Pierre Morel
---
...
diff --git a/target/s390x/cpu.h b/target/s390x/cpu.h
index 7ebd5e05b6..6e7d041b01 100644
--
On 2023/07/04 20:38, Igor Mammedov wrote:
On Sat, 1 Jul 2023 16:28:30 +0900
Akihiko Odaki wrote:
On 2023/07/01 0:29, Michael S. Tsirkin wrote:
On Fri, Jun 30, 2023 at 08:36:38PM +0900, Akihiko Odaki wrote:
On 2023/06/30 19:37, Ani Sinha wrote:
On 30-Jun-2023, at 3:30 PM, Michael S. Tsi
On 2023/07/04 20:25, Ani Sinha wrote:
PCI Express ports only have one slot, so PCI Express devices can only be
plugged into slot 0 on a PCIE port. Add a warning to let users know when the
invalid configuration is used. We may enforce this more strongly later on once
we get more clarity on whether
> On 04-Jul-2023, at 5:24 PM, Akihiko Odaki wrote:
>
> On 2023/07/04 20:25, Ani Sinha wrote:
>> PCI Express ports only have one slot, so PCI Express devices can only be
>> plugged into slot 0 on a PCIE port. Add a warning to let users know when the
>> invalid configuration is used. We may enfo
It is useful to extend the number of available PCI devices to KVM guests
for passthrough scenarios and also to expose these models to a different
(big endian) architecture. Include models for Intel Ethernet adapters
and one USB controller, which all support MSI-X. Devices only supporting
INTx won't
On 2023/07/04 20:59, Ani Sinha wrote:
On 04-Jul-2023, at 5:24 PM, Akihiko Odaki wrote:
On 2023/07/04 20:25, Ani Sinha wrote:
PCI Express ports only have one slot, so PCI Express devices can only be
plugged into slot 0 on a PCIE port. Add a warning to let users know when the
invalid configur
On Sun, 2 Jul 2023 21:02:27 +0900
Akihiko Odaki wrote:
> The current implementers of ARI are all SR-IOV devices. The ARI next
> function number field is undefined for VF. The PF should end the linked
> list formed with the field by specifying 0.
this should also describe compat behavior changes
Andreas Schwab writes:
> I think the issue is that the value returned from brk(0) is no longer
> page aligned.
>
> $ ./qemu-riscv64 -strace ../exe1
> 18329 brk(NULL) = 0x00303000
> 18329 faccessat(AT_FDCWD,"/etc/ld.so.preload",R_OK,0x3010d0) = -1 errno=2 (No
> such file or directory)
On 4/7/23 11:32, Cédric Le Goater wrote:
It is useful to extend the number of available PCI devices to KVM guests
for passthrough scenarios and also to expose these models to a different
(big endian) architecture.
Signed-off-by: Cédric Le Goater
---
hw/s390x/Kconfig | 4
1 file changed,
> On 04-Jul-2023, at 5:32 PM, Akihiko Odaki wrote:
>
> On 2023/07/04 20:59, Ani Sinha wrote:
>>> On 04-Jul-2023, at 5:24 PM, Akihiko Odaki wrote:
>>>
>>> On 2023/07/04 20:25, Ani Sinha wrote:
PCI Express ports only have one slot, so PCI Express devices can only be
plugged into slot
On 2023/07/04 21:08, Ani Sinha wrote:
On 04-Jul-2023, at 5:32 PM, Akihiko Odaki wrote:
On 2023/07/04 20:59, Ani Sinha wrote:
On 04-Jul-2023, at 5:24 PM, Akihiko Odaki wrote:
On 2023/07/04 20:25, Ani Sinha wrote:
PCI Express ports only have one slot, so PCI Express devices can only be
plu
On 4/7/23 14:01, Cédric Le Goater wrote:
It is useful to extend the number of available PCI devices to KVM guests
for passthrough scenarios and also to expose these models to a different
(big endian) architecture. Include models for Intel Ethernet adapters
and one USB controller, which all suppor
On Tue, 4 Jul 2023 16:55:55 +0530
Ani Sinha wrote:
> This change is cosmetic. A comment is added explaining why we need to check
> for
> the availability of function 0 when we hotplug a device.
>
> CC: m...@redhat.com
> Signed-off-by: Ani Sinha
> ---
> hw/pci/pci.c | 12 +---
> 1 fil
On 30/06/2023 11.17, Pierre Morel wrote:
When the host supports the CPU topology facility, the PTF
instruction with function code 2 is interpreted by the SIE,
provided that the userland hypervisor activates the interpretation
by using the KVM_CAP_S390_CPU_TOPOLOGY KVM extension.
The PTF instruct
Currently the only implementers of ARI is SR-IOV devices, and they
behave similar. Share the ARI next function number.
Signed-off-by: Akihiko Odaki
---
docs/pcie_sriov.txt | 4 ++--
include/hw/pci/pcie.h | 2 +-
hw/net/igb.c | 2 +-
hw/net/igbvf.c| 2 +-
hw/nvme/ctrl.c
The ARI next function number field is undefined for VF. The PF should
end the linked list formed with the field by specifying 0.
Supersedes: <20230701070133.24877-1-akihiko.od...@daynix.com>
("[PATCH 0/4] pci: Compare function number and ARI next function number")
V3 -> V4:
Corrected the defaul
The current implementers of ARI are all SR-IOV devices. The ARI next
function number field is undefined for VF. The PF should end the linked
list formed with the field by specifying 0.
For migration, the field will keep having 1 as its value on the old
virt models.
Fixes: 2503461691 ("pcie: Add s
On 04/07/2023 13.40, Thomas Huth wrote:
...
Also, what about protected virtualization? Do you have to use
s390_cpu_pv_mem_write() in case PV is enabled?
Never mind, I keep forgetting that CPU topology can't be used together with
PV (I just noticed after reading patch 07/20).
Not sure ... but
On Tue, 4 Jul, 2023, 5:39 pm Akihiko Odaki,
wrote:
> On 2023/07/04 21:08, Ani Sinha wrote:
> >
> >
> >> On 04-Jul-2023, at 5:32 PM, Akihiko Odaki
> wrote:
> >>
> >> On 2023/07/04 20:59, Ani Sinha wrote:
> On 04-Jul-2023, at 5:24 PM, Akihiko Odaki
> wrote:
>
> On 2023/07/04 20:25,
On Tue, 4 Jul, 2023, 5:45 pm Igor Mammedov, wrote:
> On Tue, 4 Jul 2023 16:55:55 +0530
> Ani Sinha wrote:
>
> > This change is cosmetic. A comment is added explaining why we need to
> check for
> > the availability of function 0 when we hotplug a device.
> >
> > CC: m...@redhat.com
> > Signed-o
On 7/4/23 14:09, Philippe Mathieu-Daudé wrote:
On 4/7/23 14:01, Cédric Le Goater wrote:
It is useful to extend the number of available PCI devices to KVM guests
for passthrough scenarios and also to expose these models to a different
(big endian) architecture. Include models for Intel Ethernet a
When QEMU is built with --enable-modules, the module_block.py script
parses block/*.c to find block drivers that are built as modules. The
script generates a table of block drivers called block_driver_modules[].
This table is used for block driver module loading.
The blkio.c driver uses macros to
On Mon, 3 Jul 2023 at 12:55, Stefano Garzarella wrote:
>
> On Mon, Jul 03, 2023 at 12:35:24PM +0200, Stefan Hajnoczi wrote:
> >When QEMU is built with --enable-modules, the module_block.py script
> >parses block/*.c to find block drivers that are built as modules. The
> >script generates a table o
Currently QEMU has to know some details about the back-end to be able
to setup the guest. While various parts of the setup can be delegated
to the backend (for example config handling) this is a very piecemeal
approach.
This patch suggests a new feature flag (VHOST_USER_PROTOCOL_F_STANDALONE)
whic
On Tue, 4 Jul 2023 20:50:49 +0900
Akihiko Odaki wrote:
> On 2023/07/04 20:38, Igor Mammedov wrote:
> > On Sat, 1 Jul 2023 16:28:30 +0900
> > Akihiko Odaki wrote:
> >
> >> On 2023/07/01 0:29, Michael S. Tsirkin wrote:
> >>> On Fri, Jun 30, 2023 at 08:36:38PM +0900, Akihiko Odaki wrote:
> >
On Tue, Jul 04, 2023 at 02:34:36PM +0200, Stefan Hajnoczi wrote:
When QEMU is built with --enable-modules, the module_block.py script
parses block/*.c to find block drivers that are built as modules. The
script generates a table of block drivers called block_driver_modules[].
This table is used f
On Tue, 4 Jul 2023 21:02:09 +0900
Akihiko Odaki wrote:
> On 2023/07/04 20:59, Ani Sinha wrote:
> >
> >
> >> On 04-Jul-2023, at 5:24 PM, Akihiko Odaki wrote:
> >>
> >> On 2023/07/04 20:25, Ani Sinha wrote:
> >>> PCI Express ports only have one slot, so PCI Express devices can only be
> >>>
On 2023/07/04 21:36, Igor Mammedov wrote:
On Tue, 4 Jul 2023 20:50:49 +0900
Akihiko Odaki wrote:
On 2023/07/04 20:38, Igor Mammedov wrote:
On Sat, 1 Jul 2023 16:28:30 +0900
Akihiko Odaki wrote:
On 2023/07/01 0:29, Michael S. Tsirkin wrote:
On Fri, Jun 30, 2023 at 08:36:38PM +0900, Akih
On 30/06/2023 11.17, Pierre Morel wrote:
The modification of the CPU attributes are done through a monitor
command.
It allows to move the core inside the topology tree to optimize
the cache usage in the case the host's hypervisor previously
moved the CPU.
The same command allows to modify the C
On 30/06/2023 11.17, Pierre Morel wrote:
S390x provides two more topology attributes, entitlement and dedication.
Let's add these CPU attributes to the QAPI command query-cpu-fast.
Signed-off-by: Pierre Morel
---
qapi/machine.json | 9 -
target/s390x/cpu.c | 4
2 files change
On 30/06/2023 11.17, Pierre Morel wrote:
S390 topology adds books and drawers topology containers.
Let's add these to the HMP information for hotpluggable cpus.
Signed-off-by: Pierre Morel
Reviewed-by: Nina Schoetterl-Glausch
---
hw/core/machine-hmp-cmds.c | 6 ++
1 file changed, 6 inse
On 30/06/2023 11.17, Pierre Morel wrote:
When the guest asks to change the polarization this change
is forwarded to the upper layer using QAPI.
The upper layer is supposed to take according decisions concerning
CPU provisioning.
Signed-off-by: Pierre Morel
---
qapi/machine-target.json | 33 ++
We already squash the ID register field for FEAT_SPE (the Statistical
Profiling Extension) because TCG does not implement it and if we
advertise it to the guest the guest will crash trying to look at
non-existent system registers. Do the same for some other features
which a real hardware Neoverse-
Now that we have implemented support for FEAT_LSE2, we can define
a CPU model for the Neoverse-V1, and enable it for the virt and
sbsa-ref boards.
Signed-off-by: Peter Maydell
---
If you're checking the values against the TRM, note that the
summary tables differ from the register description in t
This patchset implements the Cortex Neoverse-V1 CPU type, as a
representative Armv8.3 (+ some extras from 8.4) CPU matching real
hardware. The main thing we were waiting for to be able to define
this was FEAT_LSE2, and that is now supported.
There are a few things the real hardware implements t
On Wed, 28 Jun 2023 at 21:28, Vikram Garhwal wrote:
>
> Following are done to fix the coverity issues:
> 1. Change read_data to fix the CID 1512899: Out-of-bounds access (OVERRUN)
> 2. Fix match_rx_tx_data to fix CID 1512900: Logically dead code (DEADCODE)
> 3. Replace rand() in generate_random_da
On 30/06/2023 11.17, Pierre Morel wrote:
Introduction of the s390x cpu topology core functions and
basic tests.
We test the corelation between the command line and
the QMP results in query-cpus-fast for various CPU topology.
Signed-off-by: Pierre Morel
---
MAINTAINERS|
From: Jeuk Kim
Since v3:
- Replace softmmu_ss -> system_ss in meson
Since v2:
Addressed review comment from Stefan Hajnoczi. The main fixes are as
follows.
- Use of SPDX licence identifiers
- fixed endianness error
- removed memory leak
- fixed DMA error handling logic
Since v1:
- use macros of
On Wed, 28 Jun 2023 at 17:48, Fabiano Rosas wrote:
>
> This code is only relevant when TCG is present in the build. Building
> with --disable-tcg --enable-xen on an x86 host we get:
>
> $ ../configure --target-list=x86_64-softmmu,aarch64-softmmu --disable-tcg
> --enable-xen
> $ make -j$(nproc)
>
From: Jeuk Kim
This commit adds support for ufs logical unit.
The LU handles processing for the SCSI command,
unit descriptor query request.
This commit enables the UFS device to process
IO requests.
Signed-off-by: Jeuk Kim
---
hw/ufs/lu.c | 1441 +
From: Jeuk Kim
This commit makes the UFS device support query
and nop out transfer requests.
The next patch would be support for UFS logical
unit and scsi command transfer request.
Signed-off-by: Jeuk Kim
---
hw/ufs/trace-events |1 +
hw/ufs/ufs.c| 1005 +++
From: Jeuk Kim
Universal Flash Storage (UFS) is a high-performance mass storage device
with a serial interface. It is primarily used as a high-performance
data storage device for embedded applications.
This commit contains code for UFS device to be recognized
as a UFS PCI device.
Patches to hand
luzhipeng writes:
> Signed-off-by: luzhipeng
> ---
> contrib/gitdm/domain-map | 1 +
> 1 file changed, 1 insertion(+)
Queued to gitdm/next, thanks.
--
Alex Bennée
Virtualisation Tech Lead @ Linaro
On Tue, 27 Jun 2023 at 14:27, Peter Maydell wrote:
>
> On Tue, 27 Jun 2023 at 13:52, Leif Lindholm wrote:
> >
> > On 2023-06-27 13:12, Peter Maydell wrote:
> > > On Mon, 26 Jun 2023 at 08:52, Marcin Juszkiewicz
> > > wrote:
> > >>
> > >> Add PCI Express information into DeviceTree as part of SBS
On Wed, 28 Jun 2023 at 12:09, Akihiko Odaki wrote:
>
> AwSRAMCClass is larger than SysBusDeviceClass so the class size must be
> advertised accordingly.
>
> Fixes: 05def917e1 ("hw: arm: allwinner-sramc: Add SRAM Controller support for
> R40")
> Signed-off-by: Akihiko Odaki
> --
Applied to tar
Laurent, ping? This patch has been reviewed.
thanks
-- PMM
On Fri, 23 Jun 2023 at 15:44, Peter Maydell wrote:
>
> In the code for TARGET_NR_clock_adjtime, we set the pointer phtx to
> the address of the local variable htx. This means it can never be
> NULL, but later in the code we check it for
Hi Meta Team,
the FRU EEPROM content, I think for now detail still be confidential,
Please confirm, Can we add the description in Qemu upstream following
Cedric's request?
On Tue, Jul 4, 2023 at 6:19 PM Cédric Le Goater wrote:
> On 7/4/23 13:06, ~ssinprem wrote:
> > From: Sittisak Sinprem
> >
On Sat, 24 Jun 2023 at 01:20, Max Filippov wrote:
>
> On Fri, Jun 23, 2023 at 8:41 AM Peter Maydell
> wrote:
> >
> > In handle_interrupt() we use level as an index into the interrupt_vector[]
> > array. This is safe because we have checked it against env->config->nlevel,
> > but Coverity can't s
On 4/7/23 14:32, Cédric Le Goater wrote:
On 7/4/23 14:09, Philippe Mathieu-Daudé wrote:
On 4/7/23 14:01, Cédric Le Goater wrote:
It is useful to extend the number of available PCI devices to KVM guests
for passthrough scenarios and also to expose these models to a different
(big endian) archite
W dniu 4.07.2023 o 15:06, Peter Maydell pisze:
This patchset implements the Cortex Neoverse-V1 CPU type, as a
representative Armv8.3 (+ some extras from 8.4) CPU matching real
hardware. The main thing we were waiting for to be able to define
this was FEAT_LSE2, and that is now supported.
Now
W dniu 4.07.2023 o 15:21, Peter Maydell pisze:
Just to be clear about the status of this patch, I don't
have a problem with the code changes, but it does definitely
need a much clearer commit message to explain why we're changing
the way we handle the PCI controller. So I'm dropping this from
my
vfio_realize() has the following flow:
1. vfio_bars_prepare() -- sets VFIOBAR->size.
2. msix_early_setup().
3. vfio_bars_register() -- allocates VFIOBAR->mr.
After vfio_bars_prepare() is called msix_early_setup() can fail. If it
does fail, vfio_bars_register() is never called and VFIOBAR->mr is no
On Fri, 9 Jun 2023 at 18:23, Aaron Lindsay wrote:
>
> Signed-off-by: Aaron Lindsay
Something weird seems to have happened with the different versions
of this series. There is also a "v3" of this patch that was
sent to the list back in March, it's the same text as this one,
and Richard reviewed i
On Fri, 9 Jun 2023 at 18:24, Aaron Lindsay wrote:
>
> Signed-off-by: Aaron Lindsay
> ---
> target/arm/cpu.h | 1 +
> target/arm/cpu64.c | 48 +++---
> 2 files changed, 34 insertions(+), 15 deletions(-)
This patch also got RTH's reviewed-by tag in the "
Akihiko Odaki writes:
> AwSRAMCClass is larger than SysBusDeviceClass so the class size must be
> advertised accordingly.
>
> Fixes: 05def917e1 ("hw: arm: allwinner-sramc: Add SRAM Controller support for
> R40")
> Signed-off-by: Akihiko Odaki
Reviewed-by: Alex Bennée
--
Alex Bennée
Virtua
Peter Maydell writes:
> We already squash the ID register field for FEAT_SPE (the Statistical
> Profiling Extension) because TCG does not implement it and if we
> advertise it to the guest the guest will crash trying to look at
> non-existent system registers. Do the same for some other featur
Hello,
Here are changes improving multisocket support of the XIVE models
(POWER9 only). When a source has an END target on another chip, the
XIVE IC will use an MMIO store to forward the notification to the
remote chip. The long term plan is to get rid of pnv_xive_get_remote()
whic is a modeling s
The notify page of the interrupt controller can either be used to
receive trigger events from the HW controllers (PHB, PSI) or to
reroute interrupts between Interrupt Controller. In which case, the
VSD table is used to determine the address of the notify page of the
remote IC and the store data is
It will help us model the END triggers on the PowerNV machine, which
can be rerouted from another interrupt controller.
Signed-off-by: Cédric Le Goater
---
include/hw/ppc/xive.h | 2 ++
hw/intc/xive.c| 28 ++--
2 files changed, 20 insertions(+), 10 deletions(-)
> On 04-Jul-2023, at 6:18 PM, Igor Mammedov wrote:
>
> On Tue, 4 Jul 2023 21:02:09 +0900
> Akihiko Odaki wrote:
>
>> On 2023/07/04 20:59, Ani Sinha wrote:
>>>
>>>
On 04-Jul-2023, at 5:24 PM, Akihiko Odaki wrote:
On 2023/07/04 20:25, Ani Sinha wrote:
> PCI Express por
Associated with each NVT is a CI page address that is intended for use
by privileged interrupt management code to adjust the backlog counts
of a logical server and interrupt pending buffer for a specific
virtual processor. This backlog count adjustment function is valuable
to avoid extraneous physi
POWER systems have a degenerative interrupt path used during system
bring up. It doesn't rely on the XIVE routing logic and all thread 0
of each core are notified.
TODO: Need a new OS driver to check modeling.
Signed-off-by: Cédric Le Goater
---
include/hw/ppc/pnv_xive.h | 15 ++
include/h
> On 04-Jul-2023, at 5:20 PM, Akihiko Odaki wrote:
>
> On 2023/07/04 20:38, Igor Mammedov wrote:
>> On Sat, 1 Jul 2023 16:28:30 +0900
>> Akihiko Odaki wrote:
>>> On 2023/07/01 0:29, Michael S. Tsirkin wrote:
On Fri, Jun 30, 2023 at 08:36:38PM +0900, Akihiko Odaki wrote:
> On 2023/06/
On 7/4/23 15:27, Sittisak Sinprem wrote:
Hi Meta Team,
the FRU EEPROM content, I think for now detail still be confidential,
Please confirm, Can we add the description in Qemu upstream following Cedric's
request?
We don't need all the details, and not the confidential part of course.
C.
O
On 4/7/23 15:39, Avihai Horon wrote:
vfio_realize() has the following flow:
1. vfio_bars_prepare() -- sets VFIOBAR->size.
2. msix_early_setup().
3. vfio_bars_register() -- allocates VFIOBAR->mr.
After vfio_bars_prepare() is called msix_early_setup() can fail. If it
does fail, vfio_bars_register(
On Tue, Jul 4, 2023 at 6:27 AM Peter Maydell wrote:
>
> On Sat, 24 Jun 2023 at 01:20, Max Filippov wrote:
> >
> > On Fri, Jun 23, 2023 at 8:41 AM Peter Maydell
> > wrote:
> > >
> > > In handle_interrupt() we use level as an index into the interrupt_vector[]
> > > array. This is safe because we
Hi Mark,
we have a bug [1] possibly related to this patch.
I saw this Oracle Linux errata [2] where you reverted this patch, but
there are no details.
Do you think we should revert it upstream as well?
Do you have any details about the problem it causes in Linux?
[1] https://bugzilla.redhat.com/
On Thu, Jun 29, 2023 at 5:25 PM Hawkins Jiawei wrote:
>
> According to VirtIO standard, "The driver MUST follow
> the VIRTIO_NET_CTRL_MAC_TABLE_SET command by a le32 number,
> followed by that number of non-multicast MAC addresses,
> followed by another le32 number, followed by that number
> of mu
On Tue, 4 Jul 2023 21:22:14 +0900
Akihiko Odaki wrote:
> The current implementers of ARI are all SR-IOV devices. The ARI next
> function number field is undefined for VF .
^
add a reference to a spec (spec name, rev, chapter) where it's declared
so revi
On 8/6/23 17:09, Peter Maydell wrote:
On Wed, 31 May 2023 at 21:37, Philippe Mathieu-Daudé wrote:
SysBus IRQ are *output* IRQs. As some sort of simplification
to avoid to forward it, IcpPitState misuses it as ARM timer
input IRQ. Fix that by using a simple IRQ forwarder handler.
Signed-off-by
On Tue, 4 Jul 2023 19:20:00 +0530
Ani Sinha wrote:
> > On 04-Jul-2023, at 6:18 PM, Igor Mammedov wrote:
> >
> > On Tue, 4 Jul 2023 21:02:09 +0900
> > Akihiko Odaki wrote:
> >
> >> On 2023/07/04 20:59, Ani Sinha wrote:
> >>>
> >>>
> On 04-Jul-2023, at 5:24 PM, Akihiko Odaki
> >>
On 8/6/23 17:00, Peter Maydell wrote:
On Wed, 31 May 2023 at 21:37, Philippe Mathieu-Daudé wrote:
Both SP804State/IcpPitState peek at ArmTimerState internal state.
This is fine so far but we want to convert ArmTimerState to QOM
where peeking at QOM state internal should be avoided.
ArmTimerSta
On Wed, Jun 21, 2023 at 02:54:52PM +, Yong-Xuan Wang wrote:
> Remove M mode AIA devices when using KVM acceleration
>
> Signed-off-by: Yong-Xuan Wang
> Reviewed-by: Jim Shu
> ---
> hw/riscv/virt.c | 207 +---
> 1 file changed, 108 insertions(+), 9
On 8/6/23 16:41, Peter Maydell wrote:
On Wed, 31 May 2023 at 21:36, Philippe Mathieu-Daudé wrote:
Release the IRQs allocated in sp804_realize() in the
corresponding sp804_unrealize() handler.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/timer/arm_timer.c | 10 ++
1 file changed, 1
On Wed, Jun 21, 2023 at 02:54:53PM +, Yong-Xuan Wang wrote:
> We check the in-kernel irqchip support when using KVM acceleration.
>
> Signed-off-by: Yong-Xuan Wang
> Reviewed-by: Jim Shu
> Reviewed-by: Daniel Henrique Barboza
> ---
> target/riscv/kvm.c | 13 -
> 1 file changed,
We currently only allow 64-bit operations on the ESB CI pages. There's
no real reason for that limitation, skiboot/linux didn't need
more. However the hardware supports any size, so this patch relaxes
that restriction. It impacts both the ESB pages for "normal"
interrupts as well as the ESB pages f
This series converts the ARM_TIMER model to QOM.
Doing so we also correct an abuse of SysBus IRQ in
the ICP PIT model.
Since v1:
- Added pm215's R-b tags
- Addressed Mark/Peter review comments
- Drop '*State' suffix from structure names
- Use OR-IRQ gate
- Drop sp804_unrealize()
- Impleme
When multiple QOM types are registered in the same file,
it is simpler to use the the DEFINE_TYPES() macro. Replace
the type_init() / type_register_static() combination.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Peter Maydell
---
hw/timer/arm_timer.c | 35 +++---
Following docs/devel/style.rst guidelines, rename icp_pit_state
using CamelCase as IntegratorPIT (PIT is an acronym).
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Peter Maydell
---
hw/timer/arm_timer.c | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/hw/tim
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Peter Maydell
---
hw/timer/arm_timer.c | 16
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/hw/timer/arm_timer.c b/hw/timer/arm_timer.c
index e410b37a23..30a34a9a92 100644
--- a/hw/timer/arm_timer.c
+++ b/hw/timer
Following docs/devel/style.rst guidelines, rename arm_timer_state
as ArmTimer.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Peter Maydell
---
hw/timer/arm_timer.c | 30 +++---
1 file changed, 15 insertions(+), 15 deletions(-)
diff --git a/hw/timer/arm_timer.c b/hw
Move sp804_properties[] and sp804_class_init() around
with the rest of SP804 code code. What follows the
"Integrator/CP timer module." is strictly ICP related.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Peter Maydell
---
hw/timer/arm_timer.c | 30 +++---
1 file c
In order to simplify the QOM convertion of ARM_TIMER in a few
commits, start converting the read/write() handlers to follow
the MemoryRegionOps::read/write() prototypes.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/timer/arm_timer.c | 16
1 file changed, 8 insertions(+), 8 delet
In preparation of accessing ArmTimer::freq as a QOM property,
convert it to uint32_t (so we'll be able to use DEFINE_PROP_UINT32).
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Peter Maydell
---
hw/timer/arm_timer.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/tim
Instead of manually forwarding MMIO accesses to each ARM_TIMER,
let have the generic memory code dispatch that for us.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/timer/arm_timer.c | 23 ++-
1 file changed, 2 insertions(+), 21 deletions(-)
diff --git a/hw/timer/arm_timer.c
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