[PATCH RFC v2 2/2] vdpa: Allow VIRTIO_NET_F_CTRL_RX_EXTRA in SVQ

Enable SVQ with VIRTIO_NET_F_CTRL_RX_EXTRA feature. Signed-off-by: Hawkins Jiawei Acked-by: Eugenio Pérez --- net/vhost-vdpa.c | 1 + 1 file changed, 1 insertion(+) diff --git a/net/vhost-vdpa.c b/net/vhost-vdpa.c index 4919e18208..e10a0128c3 100644 --- a/net/vhost-vdpa.c +++ b/net/vhost-vdpa.

[PATCH RFC v2 1/2] vdpa: Restore packet receive filtering state relative with _F_CTRL_RX_EXTRA feature

This patch refactors vhost_vdpa_net_load_rx() to restore the packet receive filtering state in relation to VIRTIO_NET_F_CTRL_RX_EXTRA feature at device's startup. Signed-off-by: Hawkins Jiawei --- v2: - avoid sending CVQ command in default state suggested by Eugenio v1: https://lists.nongnu.or

[PATCH v3 0/1] target/riscv: Add support for BF16 extensions

Specification for BF16 extensions can be found in: https://github.com/riscv/riscv-bfloat16 The port is available here: https://github.com/plctlab/plct-qemu/tree/plct-bf16-upstream-v3 v3: * Remove applied Patch 1~5 * Rebase on alistair23/riscv-to-apply.next v2: * Update dependancy check for BF16

[PATCH v3 1/1] target/riscv: Add disas support for BF16 extensions

Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang --- disas/riscv.c | 44 1 file changed, 44 insertions(+) diff --git a/disas/riscv.c b/disas/riscv.c index 94e568a7e9..9f0195be30 100644 --- a/disas/riscv.c +++ b/disas/riscv.c @@ -819,6 +819,16 @@

[PATCH v6 4/7] vfio/migration: Change vIOMMU blocker from global to per device

Contrary to multiple device blocker which needs to consider already-attached devices to unblock/block dynamically, the vIOMMU migration blocker is a device specific config. Meaning it only needs to know whether the device is bypassing or not the vIOMMU (via machine property, or per pxb-pcie::bypass

[PATCH v6 3/7] vfio/pci: Disable INTx in vfio_realize error path

When vfio realize fails, INTx isn't disabled if it has been enabled. This may confuse host side with unhandled interrupt report. Fixes: c5478fea27ac ("vfio/pci: Respond to KVM irqchip change notifier") Signed-off-by: Zhenzhong Duan Reviewed-by: Joao Martins Reviewed-by: Cédric Le Goater --- hw

[PATCH v6 5/7] vfio/migration: Free resources when vfio_migration_realize fails

When vfio_realize() succeeds, hot unplug will call vfio_exitfn() to free resources allocated in vfio_realize(); when vfio_realize() fails, vfio_exitfn() is never called and we need to free resources in vfio_realize(). In the case that vfio_migration_realize() fails, e.g: with -only-migratable & en

[PATCH v6 6/7] vfio/migration: Remove print of "Migration disabled"

Property enable_migration supports [on/off/auto]. In ON mode, error pointer is passed to errp and logged. In OFF mode, we doesn't need to log "Migration disabled" as it's intentional. In AUTO mode, we should only ever see errors or warnings if the device supports migration and an error or incompati

[PATCH v6 0/7] VFIO migration related refactor and bug fix

Hello, PATCH4,6,7 refactors the VFIO migration blocker related code based on suggestions from Joao and Cedric, so that code is simpler and redundant "Migration disabled" isn't printed. But before that works, also found some hotplug bugs when testing blocker adding failed case. PATCH1-3,5 fix them

[PATCH v6 7/7] vfio/migration: Return bool type for vfio_migration_realize()

Make vfio_migration_realize() adhere to the convention of other realize() callbacks(like qdev_realize) by returning bool instead of int. Suggested-by: Cédric Le Goater Suggested-by: Joao Martins Signed-off-by: Zhenzhong Duan --- hw/vfio/migration.c | 15 ++- hw/vfio/pci.c

Re: How do you represent a host gcc and a cross gcc in lcitool?

Alistair Francis writes: > On Fri, Jun 23, 2023 at 8:29 PM Alex Bennée wrote: >> >> >> Alistair Francis writes: >> >> > On Thu, Jun 1, 2023 at 4:58 AM Alex Bennée wrote: >> >> >> >> >> >> Brian Cain writes: >> >> >> >> >> -Original Message- >> >> >> From: Alex Bennée >> >> >> Sent:

[PATCH v2] os-posix: Allow 'chroot' via '-run-with' and deprecate the old '-chroot' option

We recently introduced "-run-with" for options that influence the runtime behavior of QEMU. This option has the big advantage that it can group related options (so that it is easier for the users to spot them) and that the options become introspectable via QMP this way. So let's start moving more s

Re: [PATCH] riscv: Generate devicetree only after machine initialization is complete

On 3/7/23 05:46, Guenter Roeck wrote: If the devicetree is created before machine initialization is complete, it misses dynamic devices. Specifically, the tpm device is not added to the devicetree file and is therefore not instantiated in Linux. Create devicetree in virt_machine_done() to solve t

Re: [PATCH 01/21] q800-glue.c: convert to Resettable interface

On 2/7/23 17:48, Mark Cave-Ayland wrote: Convert the GLUE device to 3-phase reset. The legacy method doesn't do anything that's invalid in the hold phase, so the conversion is simple and not a behaviour change. Signed-off-by: Mark Cave-Ayland --- hw/m68k/q800-glue.c | 7 --- 1 file chang

Re: [PATCH 03/21] q800: add machine id register

On 2/7/23 17:48, Mark Cave-Ayland wrote: MacOS reads this address to identify the hardware. This is a basic implementation returning the ID of Quadra 800. Details: http://mess.redump.net/mess/driver_info/mac_technical_notes "There are 3 ID schemes [...] The third and most scalable is a m

[RISC-V] ERROR:../accel/tcg/cpu-exec.c:1028:cpu_exec_setjmp: assertion failed: (cpu == current_cpu)

This is a regression in 8.0. It causes the testsuite of mold to fail: https://build.opensuse.org/package/live_build_log/openSUSE:Factory:RISCV/mold/standard/riscv64 + out/test/elf/riscv64/section-start/exe2 ** ERROR:../accel/tcg/cpu-exec.c:1028:cpu_exec_setjmp: assertion failed: (cpu == current

[PATCH] qemu-options.hx: Fix indentation of some option descriptions

The description of the options starts at column 16, so fix this in some runaway lines for a more uniform output. While we're at it, replace the capital "NOTE" with "Note" since this seems to be the more common capitalization in qemu-options.hx. Signed-off-by: Thomas Huth --- qemu-options.hx | 6

Re: [PATCH v4 28/38] gdbstub: lightly refactor connection to avoid snprintf

On 6/30/23 20:04, Alex Bennée wrote: This may be a bit too much to avoid an snprintf and the slightly dodgy assign to a const variable. But hopefully not. Signed-off-by: Alex Bennée --- v2 - fix checkpatch warning --- gdbstub/softmmu.c | 19 +-- 1 file changed, 9 insertion

Re: [PATCH 06/21] q800: allow accesses to RAM area even if less memory is available

On 2/7/23 17:48, Mark Cave-Ayland wrote: MacOS attempts a series of writes and reads over the entire RAM area in order to determine the amount of RAM within the machine. Allow accesses to the entire RAM area ignoring writes and always reading zero for areas where there is no physical RAM installe

Re: [PATCH v4 14/38] tests/lcitool: introduce qemu-minimal

On 6/30/23 20:03, Alex Bennée wrote: This is a very bare bones set of dependencies for a minimal build of QEMU. This will be useful for minimal cross-compile sanity check based on things like Debian Sid where stuff isn't always in sync. Message-Id:<20230623122100.1640995-16-alex.ben...@linaro.or

Re: [PATCH v4 15/38] tests/docker: convert riscv64-cross to lcitool

On 6/30/23 20:04, Alex Bennée wrote: We still need to base this on Debian Sid until riscv64 is promoted to a release architecture (or another distro provides a full cross compile target). We use the new qemu-minimal project description to avoid bringing in all the extra dependencies because every

Re: [PATCH v2] hw/ide/piix: properly initialize the BMIBA register

Sun, 02 Jul 2023 22:18:50 + Bernhard Beschow : > Do you know if that command calls pci_device_reset() (which would eventually > call piix_ide_reset())? The function is pci_xen_ide_unplug, which calls device_cold_reset. Olaf pgpcLzDeO7ZPB.pgp Description: Digitale Signatur von OpenPGP

Re: [PATCH v4 08/38] tests/qtests: clean-up and fix leak in generic_fuzz

On 6/30/23 20:03, Alex Bennée wrote: An update to the clang tooling detects more issues with the code including a memory leak from the g_string_new() allocation. Clean up the code to avoid the allocation and use ARRAY_SIZE while we are at it. Signed-off-by: Alex Bennée --- v3 - use g_strconc

[PATCH v2] pnv/xive2: Fix TIMA offset for indirect access

Direct TIMA operations can be done through 4 pages, each with a different privilege level dictating what fields can be accessed. On the other hand, indirect TIMA accesses on P10 are done through a single page, which is the equivalent of the most privileged page of direct TIMA accesses. The offset

[PATCH v2 0/2] Fix PSIHB interrupts init PQ state

On P9 and 10, the real hardware defines the PQ state of the PSIHB interrupts to be 0b00. Qemu defaults to 0b01. It doesn't matter to skiboot, which doesn't rely on it and explicitly masks the interrupts during intialization. But this patch fixes it, just in case some other hypervisor checks it. C

[PATCH v2 2/2] pnv/psi: Initialize the PSIHB interrupts to match hardware

On the powernv9 and powernv10 machines, the PSIHB interrupts are currently initialized with a PQ state of 0b01, i.e. interrupts are disabled. However real hardware initializes them to 0b00 for the PSIHB. This patch updates it, in case an hypervisor is in the mood of checking it. Signed-off-by: Fre

[PATCH v2 1/2] pnv/xive: Add property on xive sources to define PQ state on reset

The PQ state of a xive interrupt is always initialized to Q=1, which means the interrupt is disabled. Since a xive source can be embedded in many objects, this patch adds a property to allow that behavior to be refined if needed. Signed-off-by: Frederic Barrat --- hw/intc/xive.c| 8 +

Re: How do you represent a host gcc and a cross gcc in lcitool?

[...] > > >> >> RiscV guys, > > >> >> > > >> >> It's clear that relying on Debian Sid for the QEMU cross build for > > >> >> RiscV > > >> >> is pretty flakey. Are you guys aware of any other distros that better > > >> >> support cross compiling to a riscv64 target or is Debian still the > > >> >>

Re: [PATCH v2] pnv/xive2: Fix TIMA offset for indirect access

On 7/3/23 10:08, Frederic Barrat wrote: Direct TIMA operations can be done through 4 pages, each with a different privilege level dictating what fields can be accessed. On the other hand, indirect TIMA accesses on P10 are done through a single page, which is the equivalent of the most privileged

Re: [PATCH v2 1/2] pnv/xive: Add property on xive sources to define PQ state on reset

On 7/3/23 10:12, Frederic Barrat wrote: The PQ state of a xive interrupt is always initialized to Q=1, which means the interrupt is disabled. Since a xive source can be embedded in many objects, this patch adds a property to allow that behavior to be refined if needed. Signed-off-by: Frederic Ba

Re: [PATCH v2 2/2] pnv/psi: Initialize the PSIHB interrupts to match hardware

On 7/3/23 10:12, Frederic Barrat wrote: On the powernv9 and powernv10 machines, the PSIHB interrupts are currently initialized with a PQ state of 0b01, i.e. interrupts are disabled. However real hardware initializes them to 0b00 for the PSIHB. This patch updates it, in case an hypervisor is in th

Re: [PATCH v5 0/2] vhost: register and change IOMMU flag depending on ATS state

On Mon, Jun 26, 2023 at 12:13 PM Viktor Prutyanov wrote: > > When IOMMU and vhost are enabled together, QEMU tracks IOTLB or > Device-TLB unmap events depending on whether Device-TLB is enabled. But > even if Device-TLB and PCI ATS is enabled, the guest can reject to use > it. For example, this si

Re: [PATCH 11/21] swim: add trace events for IWM and ISM registers

On 2/7/23 17:48, Mark Cave-Ayland wrote: Signed-off-by: Mark Cave-Ayland --- hw/block/swim.c | 14 ++ hw/block/trace-events | 7 +++ 2 files changed, 21 insertions(+) @@ -267,6 +275,7 @@ static void iwmctrl_write(void *opaque, hwaddr reg, uint64_t value, reg

Re: [PATCH 14/21] mac_via: work around underflow in TimeDBRA timing loop in SETUPTIMEK

On 2/7/23 17:48, Mark Cave-Ayland wrote: The MacOS toolbox ROM calculates the number of branches that can be executed per millisecond as part of its timer calibration. Since modern hosts are considerably quicker than original hardware, the negative counter reaches zero before the calibration comp

Re: [PATCH] qemu-options.hx: Fix indentation of some option descriptions

Applied to my trivial-patches tree, thank you! /mjt

Re: [PATCH 01/24] linux-user: Use assert in mmap_fork_start

Richard Henderson writes: > Assert is preferred over if+abort for the error message. > > Signed-off-by: Richard Henderson Reviewed-by: Alex Bennée -- Alex Bennée Virtualisation Tech Lead @ Linaro

Re: [PATCH 02/24] linux-user: Fix formatting of mmap.c

Richard Henderson writes: > Fix all checkpatch.pl errors within mmap.c. Reviewed-by: Alex Bennée -- Alex Bennée Virtualisation Tech Lead @ Linaro

Re: [PATCH] net: add initial support for AF_XDP network backend

On Fri, 30 Jun 2023 at 09:41, Jason Wang wrote: > > On Thu, Jun 29, 2023 at 8:36 PM Stefan Hajnoczi wrote: > > > > On Thu, 29 Jun 2023 at 07:26, Jason Wang wrote: > > > > > > On Wed, Jun 28, 2023 at 4:25 PM Stefan Hajnoczi > > > wrote: > > > > > > > > On Wed, 28 Jun 2023 at 10:19, Jason Wang

Re: [PATCH] ui: Link dbus-display with pixman again

Hi On Sat, Jul 1, 2023 at 1:49 AM Philippe Mathieu-Daudé wrote: > Since its introduction in commit 142ca628a7 ("ui: add a D-Bus > display backend"), dbus_display1 depends on pixman. > Unfortunatly the refactor commit 1222070e77 ("meson: ensure > dbus-display generated code is built before other

Re: [PATCH 03/24] linux-user/strace: Expand struct flags to hold a mask

Richard Henderson writes: > A zero bit value does not make sense -- it must relate to > some field in some way. > > Define FLAG_BASIC with a build-time sanity check. > Adjust FLAG_GENERIC and FLAG_TARGET to use it. > Add FLAG_GENERIC_MASK and FLAG_TARGET_MASK. > > Fix up the existing flag defin

Re: [PATCH 04/24] linux-user: Split TARGET_MAP_* out of syscall_defs.h

Richard Henderson writes: > Move the values into the per-target target_mman.h headers > > Signed-off-by: Richard Henderson Reviewed-by: Alex Bennée -- Alex Bennée Virtualisation Tech Lead @ Linaro

Re: [PATCH] ui: Link dbus-display with pixman again

On 7/3/23 11:21, Marc-André Lureau wrote: Hi On Sat, Jul 1, 2023 at 1:49 AM Philippe Mathieu-Daudé > wrote: Since its introduction in commit 142ca628a7 ("ui: add a D-Bus display backend"), dbus_display1 depends on pixman. Unfortunatly the refactor commit 1

Re: [PATCH 05/24] linux-user: Split TARGET_PROT_* out of syscall_defs.h

Richard Henderson writes: > Move the values into the per-target target_mman.h headers > > Signed-off-by: Richard Henderson > --- > linux-user/aarch64/target_mman.h | 3 +++ > linux-user/generic/target_mman.h | 4 > linux-user/mips/target_mman.h| 2 ++ > linux-user/syscall_defs.h

Re: [PATCH v4] target: ppc: Use MSR_HVB bit to get the target endianness for memory dump

On Fri, 23 Jun 2023 03:25:06 -0400 Narayana Murty N wrote: > Currently on PPC64 qemu always dumps the guest memory in > Big Endian (BE) format even though the guest running in Little Endian > (LE) mode. So crash tool fails to load the dump as illustrated below: > > Log : > $ virsh dump DOMAIN --

Re: [PATCH 06/24] linux-user: Populate more bits in mmap_flags_tbl

Richard Henderson writes: > Fix translation of TARGET_MAP_SHARED and TARGET_MAP_PRIVATE, > which are types not single bits. Add TARGET_MAP_SHARED_VALIDATE, > TARGET_MAP_SYNC, TARGET_MAP_NONBLOCK, TARGET_MAP_POPULATE, > TARGET_MAP_FIXED_NOREPLACE, and TARGET_MAP_UNINITIALIZED. > > Update strace

Re: [PATCH 07/24] accel/tcg: Introduce page_check_range_empty

Richard Henderson writes: > Examine the interval tree to validate that a region > has no existing mappings. > > Signed-off-by: Richard Henderson > --- > include/exec/cpu-all.h | 11 +++ > accel/tcg/user-exec.c | 7 +++ > 2 files changed, 18 insertions(+) > > diff --git a/include

Re: [PATCH v2 0/2] Fix PSIHB interrupts init PQ state

On 3/7/23 10:12, Frederic Barrat wrote: Frederic Barrat (2): pnv/xive: Add property on xive sources to define PQ state on reset pnv/psi: Initialize the PSIHB interrupts to match hardware Reviewed-by: Philippe Mathieu-Daudé

Re: [PATCH 09/24] linux-user: Implement MAP_FIXED_NOREPLACE

Richard Henderson writes: > Signed-off-by: Richard Henderson > --- > linux-user/mmap.c | 14 +++--- > 1 file changed, 11 insertions(+), 3 deletions(-) > > diff --git a/linux-user/mmap.c b/linux-user/mmap.c > index cb5369d2d1..41c2f09fd5 100644 > --- a/linux-user/mmap.c > +++ b/linux-u

[PATCH v4 13/37] host/include/aarch64: Implement aes-round.h

Detect AES in cpuinfo; implement the accel hooks. Signed-off-by: Richard Henderson --- meson.build | 9 + host/include/aarch64/host/cpuinfo.h | 1 + host/include/aarch64/host/crypto/aes-round.h | 205 +++ util/cpuinfo-aarch64.c

[PATCH v4 06/37] crypto: Add aesdec_ISB_ISR_AK

Add a primitive for InvSubBytes + InvShiftRows + AddRoundKey. Reviewed-by: Daniel P. Berrangé Signed-off-by: Richard Henderson --- host/include/generic/host/crypto/aes-round.h | 4 ++ include/crypto/aes-round.h | 21 + crypto/aes.c | 45

[PATCH v4 15/37] target/ppc: Use aesenc_SB_SR_AK

This implements the VCIPHERLAST instruction. Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Daniel Henrique Barboza Signed-off-by: Richard Henderson --- target/ppc/int_helper.c | 9 ++--- 1 file changed, 2 insertions(+), 7 deletions(-) diff --git a/target/ppc/int_helper.c b/target/ppc/i

[PATCH v4 30/37] target/riscv: Use aesdec_ISB_ISR_AK

This implements the AES64DS instruction. Signed-off-by: Richard Henderson --- target/riscv/crypto_helper.c | 7 ++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/target/riscv/crypto_helper.c b/target/riscv/crypto_helper.c index b072fed3e2..e61f7fe1e5 100644 --- a/target/riscv/

[PATCH v4 12/37] host/include/i386: Implement aes-round.h

Detect AES in cpuinfo; implement the accel hooks. Signed-off-by: Richard Henderson --- host/include/i386/host/cpuinfo.h| 1 + host/include/i386/host/crypto/aes-round.h | 152 host/include/x86_64/host/crypto/aes-round.h | 1 + util/cpuinfo-i386.c

[PATCH v4 22/37] target/i386: Use aesenc_SB_SR_MC_AK

This implements the AESENC instruction. Signed-off-by: Richard Henderson --- target/i386/ops_sse.h | 14 +- 1 file changed, 5 insertions(+), 9 deletions(-) diff --git a/target/i386/ops_sse.h b/target/i386/ops_sse.h index 893913ebf8..93a4e0cf16 100644 --- a/target/i386/ops_sse.h +++

[PATCH v4 17/37] target/ppc: Use aesenc_SB_SR_MC_AK

This implements the VCIPHER instruction. Reviewed-by: Daniel Henrique Barboza Signed-off-by: Richard Henderson --- target/ppc/int_helper.c | 14 -- 1 file changed, 4 insertions(+), 10 deletions(-) diff --git a/target/ppc/int_helper.c b/target/ppc/int_helper.c index 15f07fca2b..1e47

[PATCH v4 10/37] crypto: Add aesdec_ISB_ISR_IMC_AK

Add a primitive for InvSubBytes + InvShiftRows + InvMixColumns + AddRoundKey. Acked-by: Daniel P. Berrangé Signed-off-by: Richard Henderson --- host/include/generic/host/crypto/aes-round.h | 3 + include/crypto/aes-round.h | 21 +++ crypto/aes.c

[PATCH v4 11/37] crypto: Add aesdec_ISB_ISR_AK_IMC

Add a primitive for InvSubBytes + InvShiftRows + AddRoundKey + InvMixColumns. Acked-by: Daniel P. Berrangé Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- host/include/generic/host/crypto/aes-round.h | 3 +++ include/crypto/aes-round.h | 21 +

[PATCH v4 01/37] util: Add cpuinfo-ppc.c

Move the code from tcg/. Fix a bug in that PPC_FEATURE2_ARCH_3_10 is actually spelled PPC_FEATURE2_ARCH_3_1. Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Daniel Henrique Barboza Signed-off-by: Richard Henderson --- host/include/ppc/host/cpuinfo.h | 29 host/include/ppc6

[PATCH v4 33/37] target/riscv: Use aesdec_ISB_ISR_IMC_AK

This implements the AES64DSM instruction. This was the last use of aes64_operation and its support macros, so remove them all. Signed-off-by: Richard Henderson --- target/riscv/crypto_helper.c | 101 --- 1 file changed, 10 insertions(+), 91 deletions(-) diff --g

[PATCH v4 26/37] target/arm: Use aesdec_ISB_ISR_AK

This implements the AESD instruction. Signed-off-by: Richard Henderson --- target/arm/tcg/crypto_helper.c | 37 +++--- 1 file changed, 16 insertions(+), 21 deletions(-) diff --git a/target/arm/tcg/crypto_helper.c b/target/arm/tcg/crypto_helper.c index 00f3b21507..d2c

[PATCH v4 32/37] target/riscv: Use aesenc_SB_SR_MC_AK

This implements the AES64ESM instruction. Signed-off-by: Richard Henderson --- target/riscv/crypto_helper.c | 7 ++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/target/riscv/crypto_helper.c b/target/riscv/crypto_helper.c index 505166ce5a..c036fe8632 100644 --- a/target/riscv

[PATCH v4 04/37] crypto/aes: Add AES_SH, AES_ISH macros

These macros will constant fold and avoid the indirection through memory when fully unrolling some new primitives. Acked-by: Daniel P. Berrangé Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- crypto/aes.c | 16 ++-- 1 file changed, 14 insertions(+), 2 delet

[PATCH v4 05/37] crypto: Add aesenc_SB_SR_AK

Start adding infrastructure for accelerating guest AES. Begin with a SubBytes + ShiftRows + AddRoundKey primitive. Acked-by: Daniel P. Berrangé Signed-off-by: Richard Henderson --- MAINTAINERS | 1 + host/include/generic/host/crypto/aes-round.h | 16 +++ in

[PATCH v4 27/37] target/arm: Use aesenc_MC

This implements the AESMC instruction. Signed-off-by: Richard Henderson --- target/arm/tcg/crypto_helper.c | 15 ++- 1 file changed, 14 insertions(+), 1 deletion(-) diff --git a/target/arm/tcg/crypto_helper.c b/target/arm/tcg/crypto_helper.c index d2cb74e7fc..1952aaac58 100644 --- a

Re: [PATCH v3 00/14] Misc clean ups to target/ppc exception handling

On 7/2/23 09:36, BALATON Zoltan wrote: On Sat, 1 Jul 2023, Daniel Henrique Barboza wrote: On 7/1/23 06:39, BALATON Zoltan wrote: On Sat, 1 Jul 2023, Daniel Henrique Barboza wrote: On 6/30/23 19:57, BALATON Zoltan wrote: On Fri, 30 Jun 2023, Daniel Henrique Barboza wrote: Patches 1, 2, 3,

[PATCH v4 02/37] tests/multiarch: Add test-aes

Use a shared driver and backends for i386, aarch64, ppc64, riscv64. Acked-by: Alex Bennée Signed-off-by: Richard Henderson --- tests/tcg/aarch64/test-aes.c| 58 tests/tcg/i386/test-aes.c | 68 + tests/tcg/ppc64/test-aes.c | 116 +

[PATCH v4 35/37] crypto: Implement aesdec_IMC with AES_imc_rot

This method uses one uint32_t * 256 table instead of 4, which means its data cache overhead is less. Acked-by: Daniel P. Berrangé Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- crypto/aes.c | 42 +- 1 file changed, 21 insertions

[PATCH v4 23/37] target/i386: Use aesdec_ISB_ISR_IMC_AK

This implements the AESDEC instruction. Signed-off-by: Richard Henderson --- target/i386/ops_sse.h | 14 +- 1 file changed, 5 insertions(+), 9 deletions(-) diff --git a/target/i386/ops_sse.h b/target/i386/ops_sse.h index 93a4e0cf16..a0e425733f 100644 --- a/target/i386/ops_sse.h +++

[PATCH v4 36/37] crypto: Remove AES_imc

This array is no longer used. Acked-by: Daniel P. Berrangé Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- include/crypto/aes.h | 7 -- crypto/aes.c | 264 --- 2 files changed, 271 deletions(-) diff --git a/include/cry

[PATCH v4 19/37] target/i386: Use aesenc_SB_SR_AK

This implements the AESENCLAST instruction. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/i386/ops_sse.h | 11 ++- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/target/i386/ops_sse.h b/target/i386/ops_sse.h index fb63af7afa..63fdecbe03 1

[PATCH v4 34/37] crypto: Remove AES_shifts, AES_ishifts

These arrays are no longer used, replaced by AES_SH_*, AES_ISH_*. Acked-by: Daniel P. Berrangé Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- include/crypto/aes.h | 4 crypto/aes.c | 14 -- 2 files changed, 18 deletions(-) diff --git a/inclu

[PATCH v4 29/37] target/riscv: Use aesenc_SB_SR_AK

This implements the AES64ES instruction. Signed-off-by: Richard Henderson --- target/riscv/crypto_helper.c | 10 +- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/target/riscv/crypto_helper.c b/target/riscv/crypto_helper.c index 2ef30281b1..b072fed3e2 100644 --- a/target/ri

[PATCH v4 08/37] crypto: Add aesdec_IMC

Add a primitive for InvMixColumns. Acked-by: Daniel P. Berrangé Signed-off-by: Richard Henderson --- host/include/generic/host/crypto/aes-round.h | 2 + include/crypto/aes-round.h | 18 ++ crypto/aes.c | 59 3 files cha

[PATCH v4 14/37] host/include/ppc: Implement aes-round.h

Detect CRYPTO in cpuinfo; implement the accel hooks. Reviewed-by: Daniel Henrique Barboza Signed-off-by: Richard Henderson --- host/include/ppc/host/cpuinfo.h| 1 + host/include/ppc/host/crypto/aes-round.h | 182 + host/include/ppc64/host/crypto/aes-round.h |

[PATCH v4 20/37] target/i386: Use aesdec_ISB_ISR_AK

This implements the AESDECLAST instruction. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/i386/ops_sse.h | 10 +- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/target/i386/ops_sse.h b/target/i386/ops_sse.h index 63fdecbe03..0a37bde595 10

[PATCH v4 25/37] target/arm: Use aesenc_SB_SR_AK

This implements the AESE instruction. Signed-off-by: Richard Henderson --- target/arm/tcg/crypto_helper.c | 24 +++- 1 file changed, 23 insertions(+), 1 deletion(-) diff --git a/target/arm/tcg/crypto_helper.c b/target/arm/tcg/crypto_helper.c index 75882d9ea3..00f3b21507 1006

[PATCH v4 18/37] target/ppc: Use aesdec_ISB_ISR_AK_IMC

This implements the VNCIPHER instruction. Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Daniel Henrique Barboza Signed-off-by: Richard Henderson --- target/ppc/int_helper.c | 19 --- 1 file changed, 4 insertions(+), 15 deletions(-) diff --git a/target/ppc/int_helper.c b/tar

Re: [PATCH 10/24] linux-user: Split out target_to_host_prot

Richard Henderson writes: > Split out from validate_prot_to_pageflags, as there is not > one single host_prot for the entire range. We need to adjust > prot for every host page that overlaps multiple guest pages. > > Signed-off-by: Richard Henderson Reviewed-by: Alex Bennée -- Alex Bennée

[PATCH v4 03/37] target/arm: Move aesmc and aesimc tables to crypto/aes.c

We do not currently have a table in crypto/ for just MixColumns. Move both tables for consistency. Acked-by: Daniel P. Berrangé Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- include/crypto/aes.h | 6 ++ crypto/aes.c | 140 +++

[PATCH v4 28/37] target/arm: Use aesdec_IMC

This implements the AESIMC instruction. We have converted everything to crypto/aes-round.h; crypto/aes.h is no longer needed. Signed-off-by: Richard Henderson --- target/arm/tcg/crypto_helper.c | 33 ++--- 1 file changed, 14 insertions(+), 19 deletions(-) diff --git

[PATCH v4 21/37] target/i386: Use aesdec_IMC

This implements the AESIMC instruction. Signed-off-by: Richard Henderson --- target/i386/ops_sse.h | 11 +++ 1 file changed, 3 insertions(+), 8 deletions(-) diff --git a/target/i386/ops_sse.h b/target/i386/ops_sse.h index 0a37bde595..893913ebf8 100644 --- a/target/i386/ops_sse.h +++ b/t

[PATCH v4 16/37] target/ppc: Use aesdec_ISB_ISR_AK

This implements the VNCIPHERLAST instruction. Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Daniel Henrique Barboza Signed-off-by: Richard Henderson --- target/ppc/int_helper.c | 8 +--- 1 file changed, 1 insertion(+), 7 deletions(-) diff --git a/target/ppc/int_helper.c b/target/ppc/in

[PATCH v4 00/37] crypto: Provide aes-round.h and host accel

Inspired by Ard Biesheuvel's RFC patches for accelerating AES under emulation, provide a set of primitives that maps between the guest and host fragments. Changes for v4: * Fix typo in AESState (Max Chou) * Define AES_SH/ISH as macros (Ard Biesheuvel) * Group patches by subsystem. Patches l

[PATCH v4 31/37] target/riscv: Use aesdec_IMC

This implements the AES64IM instruction. Signed-off-by: Richard Henderson --- target/riscv/crypto_helper.c | 15 +-- 1 file changed, 5 insertions(+), 10 deletions(-) diff --git a/target/riscv/crypto_helper.c b/target/riscv/crypto_helper.c index e61f7fe1e5..505166ce5a 100644 --- a/ta

[PATCH v4 24/37] target/arm: Demultiplex AESE and AESMC

Split these helpers so that we are not passing 'decrypt' within the simd descriptor. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/arm/helper.h | 2 ++ target/arm/tcg/sve.decode | 4 ++-- target/arm/tcg/crypto_helper.c | 37

[PATCH v4 09/37] crypto: Add aesenc_SB_SR_MC_AK

Add a primitive for SubBytes + ShiftRows + MixColumns + AddRoundKey. Acked-by: Daniel P. Berrangé Signed-off-by: Richard Henderson --- host/include/generic/host/crypto/aes-round.h | 3 + include/crypto/aes-round.h | 21 +++ crypto/aes.c | 5

[PATCH v4 37/37] crypto: Unexport AES_*_rot, AES_TeN, AES_TdN

These arrays are no longer used outside of aes.c. Acked-by: Daniel P. Berrangé Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- include/crypto/aes.h | 25 - crypto/aes.c | 33 + 2 files changed, 21 insertio

[PATCH v4 07/37] crypto: Add aesenc_MC

Add a primitive for MixColumns. Acked-by: Daniel P. Berrangé Signed-off-by: Richard Henderson --- host/include/generic/host/crypto/aes-round.h | 2 + include/crypto/aes-round.h | 18 ++ crypto/aes.c | 61 3 files change

[PATCH 1/4] target/ppc: Add LPAR-per-core vs per-thread mode flag

The Power ISA has the concept of sub-processors: Hardware is allowed to sub-divide a multi-threaded processor into "sub-processors" that appear to privileged programs as multi-threaded processors with fewer threads. POWER9 and POWER10 have two modes, either every thread is a sub-processor o

[PATCH 0/4] ppc/pnv: SMT support for powernv

These patches implement enough to install a distro, boot, run SMP KVM guests with libvirt with good performance using MTTCG (as reported by Cedric). There are a few more SPRs that need to be done, and per-LPAR SPRs are mostly not annotated yet so it can't run in 1 LPAR mode. But those can be added

[PATCH 4/4] tests/avocado: Add powernv machine test script

This copies ppc_pseries.py to start a set of powernv tests, including a Linux boot test for the newly added SMT mode. Signed-off-by: Nicholas Piggin --- tests/avocado/ppc_powernv.py | 86 1 file changed, 86 insertions(+) create mode 100644 tests/avocado/ppc_

[PATCH 2/4] target/ppc: SMT support for the HID SPR

HID is a per-core shared register, skiboot sets this (e.g., setting HILE) on one thread and that must affect all threads of the core. Tested-by: Cédric Le Goater Signed-off-by: Nicholas Piggin --- target/ppc/cpu_init.c| 2 +- target/ppc/helper.h | 1 + target/ppc/misc_helper.c | 21 +

[PATCH 3/4] ppc/pnv: SMT support for powernv

Set the TIR default value with the SMT thread index, and place some standard limits on SMT configurations. Now powernv is able to boot skiboot and Linux with a SMT topology, including booting a KVM guest. There are several SPRs and other features (e.g., broadcast msgsnd) that are not implemented,

Re: [PATCH v2 2/5] test-throttle: use enum ThrottleType

On Tue 27 Jun 2023 03:24:28 PM +08, zhenwei pi wrote: > Use enum ThrottleType instead in the throttle test codes. > > Signed-off-by: zhenwei pi Reviewed-by: Alberto Garcia Berto

Re: [PATCH v2 1/5] throttle: introduce enum ThrottleType

On Tue 27 Jun 2023 03:24:27 PM +08, zhenwei pi wrote: > Use enum ThrottleType instead of number index. > > Signed-off-by: zhenwei pi Reviewed-by: Alberto Garcia Berto

Re: [PATCH v2 3/5] throttle: support read-only and write-only

On Tue 27 Jun 2023 03:24:29 PM +08, zhenwei pi wrote: > Only one direction is necessary in several scenarios: > - a read-only disk > - operations on a device are considered as *write* only. For example, > encrypt/decrypt/sign/verify operations on a cryptodev use a single > *write* timer(read ti

Re: [PATCH v2 5/5] cryptodev: use NULL throttle timer cb for read direction

On Tue 27 Jun 2023 03:24:31 PM +08, zhenwei pi wrote: > Operations on a crytpodev are considered as *write* only, the callback > of read direction is never invoked. Use NULL instead of an unreachable > path(cryptodev_backend_throttle_timer_cb on read direction). > > Signed-off-by: zhenwei pi Revi

Re: [PATCH v2 4/5] test-throttle: test read only and write only

On Tue 27 Jun 2023 03:24:30 PM +08, zhenwei pi wrote: > Signed-off-by: zhenwei pi Reviewed-by: Alberto Garcia Berto

Re: [PATCH 07/24] accel/tcg: Introduce page_check_range_empty

On 7/3/23 11:45, Alex Bennée wrote: Richard Henderson writes: Examine the interval tree to validate that a region has no existing mappings. Signed-off-by: Richard Henderson --- include/exec/cpu-all.h | 11 +++ accel/tcg/user-exec.c | 7 +++ 2 files changed, 18 insertions(+

[PATCH] block/blkio: fix module_block.py parsing

When QEMU is built with --enable-modules, the module_block.py script parses block/*.c to find block drivers that are built as modules. The script generates a table of block drivers called block_driver_modules[]. This table is used for block driver module loading. The blkio.c driver uses macros to

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