Re: [PATCH v3 0/6] eBPF RSS through QMP support.

On Thu, Jun 15, 2023 at 6:29 AM Andrew Melnychenko wrote: > > This series of patches provides the ability to retrieve eBPF program > through qmp, so management application may load bpf blob with proper > capabilities. > Now, virtio-net devices can accept eBPF programs and maps through properties

[QEMU PATCH v2 1/1] virtgpu: do not destroy resources when guest suspend

After suspending and resuming guest VM, you will get a black screen, and the display can't come back. This is because when guest did suspending, it called into qemu to call virtio_gpu_gl_reset. In function virtio_gpu_gl_reset, it destroyed resources and reset renderer, which were used for display.

[QEMU PATCH v2 0/1] S3 support

v2: Hi all, Thanks to Marc-André Lureau, Robert Beckett and Gerd Hoffmann for their advice and guidance. V2 makes below changes: * Change VIRTIO_CPU_CMD_STATUS_FREEZING to 0x0400 (<0x1000) * Add virtio_gpu_device_unrealize to destroy resources to solve potential memory leak problem. This also

Re: [QEMU PATCH 1/1] virtgpu: do not destroy resources when guest suspend

Hi Dongwon, On 2023/6/30 00:53, Kim, Dongwon wrote: > This method - letting QEMU not remove resources would work on S3 case but > with S4, the QEMU would lose all the resources anyway as the process will be > terminated. So objects restoring was only option for us as My patch is for S3 function

Re: [PATCH v6 11/20] target/riscv/cpu: add misa_ext_info_arr[]

On Thu, Jun 29, 2023 at 07:04:28PM -0300, Daniel Henrique Barboza wrote: > Drew, > > On 6/29/23 05:59, Andrew Jones wrote: > > On Wed, Jun 28, 2023 at 06:30:24PM -0300, Daniel Henrique Barboza wrote: > > > Next patch will add KVM specific user properties for both MISA and > > > multi-letter extens

Re: [PULL 18/42] tests: avocado: boot_linux_console: Add test case for bpim2u

On 30/06/2023 08.15, qianfan wrote: 在 2023/6/29 19:35, Thomas Huth 写道: On 06/06/2023 11.47, Peter Maydell wrote: From: qianfan Zhao Add test case for booting from initrd and sd card. Signed-off-by: qianfan Zhao Reviewed-by: Niek Linnenbank Tested-by: Niek Linnenbank Signed-off-by: Peter

[PATCH] target/mips: enable GINVx support for I6400 and I6500

GINVI and GINVT operations are supported on MIPS I6400 and I6500 cores, so indicate that properly in CP0.Config5 register bits [16:15]. Signed-off-by: Marcin Nowakowski --- target/mips/cpu-defs.c.inc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/mips/cpu-defs.c.i

Re: [PATCH v2] piix: fix regression during unplug in Xen HVM domUs

Wed, 28 Jun 2023 09:27:16 + Bernhard Beschow : > Would you mind sending a patch fixing the BMIBA register to be reset as 32 > bit? Will do so next week. Are the specs for this chipset available, does this address really need to be accessed in quantities of u32, or is perhaps u16 required? I

Re: [PATCH 3/4] ppc/pnv: Add P10 quad ops

On 30/06/2023 05:55, Joel Stanley wrote: diff --git a/hw/ppc/pnv_core.c b/hw/ppc/pnv_core.c index b9a57463aec4..7fff2fd9e298 100644 --- a/hw/ppc/pnv_core.c +++ b/hw/ppc/pnv_core.c +static uint64_t pnv_quad_power10_xscom_read(void *opaque, hwaddr addr, ... +qemu_log_mask(LOG_UNIMP,

Re: [PATCH v6 02/20] hw/riscv/virt.c: skip 'mmu-type' FDT if satp mode not set

29.06.2023 00:30, Daniel Henrique Barboza wrote: The absence of a satp mode in riscv_host_cpu_init() is causing the following error: $ sudo ./qemu/build/qemu-system-riscv64 -machine virt,accel=kvm \ -m 2G -smp 1 -nographic -snapshot \ -kernel ./guest_imgs/Image \ -initrd ./guest

Re: [PATCH 3/4] ppc/pnv: Add P10 quad ops

On Fri, 30 Jun 2023 at 07:30, Frederic Barrat wrote: > > > > On 30/06/2023 05:55, Joel Stanley wrote: > > diff --git a/hw/ppc/pnv_core.c b/hw/ppc/pnv_core.c > > index b9a57463aec4..7fff2fd9e298 100644 > > --- a/hw/ppc/pnv_core.c > > +++ b/hw/ppc/pnv_core.c > > > +static uint64_t pnv_quad_power10_x

[PATCH v3 02/17] hw/pci-host/q35: Fix double, contradicting .endianness assignment

Fixes the following clangd warning (-Winitializer-overrides): q35.c:297:19: Initializer overrides prior initialization of this subobject q35.c:292:19: previous initialization is here Settle on little endian which is consistent with using pci_host_conf_le_ops. Fixes: bafc90bdc594 ("q35: imple

[PATCH v3 07/17] hw/i386/pc_piix: Turn some local variables into initializers

Eliminates an else branch. Suggested-by: Igor Mammedov Signed-off-by: Bernhard Beschow Reviewed-by: Philippe Mathieu-Daudé --- hw/i386/pc_piix.c | 13 - 1 file changed, 4 insertions(+), 9 deletions(-) diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c index f9947fbc10..6a5b6dad2f

[PATCH v3 08/17] hw/pci-host/i440fx: Add "i440fx" child property in board code

The parent-child relation is usually established near a child's qdev_new(). For i440fx this allows for reusing the machine parameter, thus avoiding qdev_get_machine() which relies on a global variable. Suggested-by: Philippe Mathieu-Daudé Signed-off-by: Bernhard Beschow --- hw/i386/pc_piix.c

[PATCH v3 15/17] hw/pci-host/i440fx: Add I440FX_HOST_PROP_PCI_TYPE property

I440FX needs a different PCI device model if the "igd-passthru" property is enabled. The type name is currently passed as a parameter to i440fx_init(). This parameter will be replaced by a property assignment once i440fx_init() gets resolved. Signed-off-by: Bernhard Beschow --- include/hw/pci-ho

[PATCH v3 00/17] Q35 and I440FX host bridge QOM cleanup

This series resolves the legacy i440fx_init() function and instantiates the I440FX host bridge the QOM way. As a preparation the Q35 host bridge receives some cleanup as well. Most of the Q35 patches have been submitted under [1] before. This series incorporates only the changes making the two dev

[PATCH v3 05/17] hw/pci-host/q35: Initialize PCI_HOST_BYPASS_IOMMU property from board code

The Q35 PCI host already has a PCI_HOST_BYPASS_IOMMU property. However, the host initializes this property itself by accessing global machine state, thereby assuming it to be a PC machine. Avoid this by having board code set this property. Signed-off-by: Bernhard Beschow Reviewed-by: Igor Mammedo

[PATCH v3 14/17] hw/pci-host/i440fx: Add PCI_HOST_{ABOVE, BELOW}_4G_MEM_SIZE properties

Introduce the properties in anticipation of QOM'ification; Q35 has the same properties. Note that we want to avoid a "ram size" property in the QOM interface since it seems redundant to both properties introduced in this change. Thus the removal of the ram_size parameter. We assume the invariant o

[PATCH v3 01/17] hw/i386/pc_q35: Resolve redundant q35_host variable

The variable is redundant to "phb" and is never used by its real type. Signed-off-by: Bernhard Beschow Reviewed-by: Thomas Huth Reviewed-by: Philippe Mathieu-Daudé --- hw/i386/pc_q35.c | 27 +-- 1 file changed, 13 insertions(+), 14 deletions(-) diff --git a/hw/i386/pc_

[PATCH v3 16/17] hw/pci-host/i440fx: Resolve i440fx_init()

i440fx_init() is a legacy init function. The previous patches worked towards TYPE_I440FX_PCI_HOST_BRIDGE to be instantiated the QOM way. Do this now by transforming the parameters passed to i440fx_init() into property assignments. Signed-off-by: Bernhard Beschow --- include/hw/pci-host/i440fx.h

[PATCH v3 03/17] hw/pci-host/q35: Initialize PCMachineState::bus in board code

The Q35 PCI host currently sets the PC machine's PCI bus attribute through global state, thereby assuming the machine to be a PC machine. The Q35 machine code already holds on to Q35's pci bus attribute, so can easily set its own property while preserving encapsulation. Signed-off-by: Bernhard Bes

[PATCH v3 11/17] hw/pci-host/i440fx: Move i440fx_realize() into PCII440FXState section

i440fx_realize() realizes the PCI device inside the host bridge (PCII440FXState), but is implemented between i440fx_pcihost_realize() and i440fx_init() which deal with the host bridge itself (I440FXState). Since we want to append i440fx_init() to i440fx_pcihost_realize() later let's move i440fx_rea

[PATCH v3 06/17] hw/pci-host/q35: Make some property name macros reusable by i440fx

Signed-off-by: Bernhard Beschow --- include/hw/i386/pc.h | 4 include/hw/pci-host/q35.h | 5 - hw/i386/pc_q35.c | 8 hw/pci-host/q35.c | 8 4 files changed, 12 insertions(+), 13 deletions(-) diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h

[PATCH v3 17/17] hw/i386/pc_piix: Move i440fx' realize near its qdev_new()

I440FX realization is currently mixed with PIIX3 creation. Furthermore, it is common practice to only set properties between a device's qdev_new() and qdev_realize(). Clean up to resolve both issues. Since I440FX spawns a PCI bus let's also move the pci_bus initialization there. Note that when ru

[PATCH v3 04/17] hw/pci/pci_host: Introduce PCI_HOST_BYPASS_IOMMU macro

Introduce a macro to avoid copy and pasting strings which can easily cause typos. Suggested-by: Michael S. Tsirkin Signed-off-by: Bernhard Beschow Reviewed-by: Igor Mammedov --- include/hw/pci/pci_host.h | 2 ++ hw/pci/pci_host.c | 2 +- 2 files changed, 3 insertions(+), 1 deletion(-)

[PATCH v3 09/17] hw/pci-host/i440fx: Replace magic values by existing constants

Signed-off-by: Bernhard Beschow Reviewed-by: Igor Mammedov Reviewed-by: Philippe Mathieu-Daudé --- hw/pci-host/i440fx.c | 8 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/hw/pci-host/i440fx.c b/hw/pci-host/i440fx.c index d95d9229d3..b7c24a4e1d 100644 --- a/hw/pci-host/i

[PATCH v3 13/17] hw/pci-host/i440fx: Add PCI_HOST_PROP_IO_MEM property

Introduce the property in anticipation of QOM'ification; Q35 has the same property. Signed-off-by: Bernhard Beschow --- hw/pci-host/i440fx.c | 14 ++ 1 file changed, 10 insertions(+), 4 deletions(-) diff --git a/hw/pci-host/i440fx.c b/hw/pci-host/i440fx.c index b9530fc3a0..de14c75e9

[PATCH v3 10/17] hw/pci-host/i440fx: Have common names for some local variables

`PCIHostState` is often referred to as `phb`, own device state usually as `s`. Signed-off-by: Bernhard Beschow Reviewed-by: Philippe Mathieu-Daudé --- hw/pci-host/i440fx.c | 26 -- 1 file changed, 12 insertions(+), 14 deletions(-) diff --git a/hw/pci-host/i440fx.c b/hw/

[PATCH v3 12/17] hw/pci-host/i440fx: Make MemoryRegion pointers accessible as properties

The goal is to eliminate i440fx_init() which is a legacy init function. This neccessitates the memory regions to be properties, like in Q35, which will be assigned in board code. Since i440fx needs different PCI devices in Xen mode, and since i440fx shall be self-contained, the PCI device will be

Re: [PATCH v6 5/5] hw/pci: ensure PCIE devices are plugged into only slot 0 of PCIE port

> On 30-Jun-2023, at 8:13 AM, Akihiko Odaki wrote: > > On 2023/06/29 23:18, Ani Sinha wrote: >>> On 29-Jun-2023, at 2:19 PM, Akihiko Odaki wrote: >>> >>> On 2023/06/29 17:05, Ani Sinha wrote: On Thu, 29 Jun, 2023, 12:17 pm Akihiko Odaki, >>> > wrote: >>>

Re: [PATCH] net: add initial support for AF_XDP network backend

On Thu, Jun 29, 2023 at 8:36 PM Stefan Hajnoczi wrote: > > On Thu, 29 Jun 2023 at 07:26, Jason Wang wrote: > > > > On Wed, Jun 28, 2023 at 4:25 PM Stefan Hajnoczi wrote: > > > > > > On Wed, 28 Jun 2023 at 10:19, Jason Wang wrote: > > > > > > > > On Wed, Jun 28, 2023 at 4:15 PM Stefan Hajnoczi

Re: [PATCH 3/4] ppc/pnv: Add P10 quad ops

On 6/30/23 09:35, Joel Stanley wrote: On Fri, 30 Jun 2023 at 07:30, Frederic Barrat wrote: On 30/06/2023 05:55, Joel Stanley wrote: diff --git a/hw/ppc/pnv_core.c b/hw/ppc/pnv_core.c index b9a57463aec4..7fff2fd9e298 100644 --- a/hw/ppc/pnv_core.c +++ b/hw/ppc/pnv_core.c +static uint64_t

Re: [PATCH] net: add initial support for AF_XDP network backend

On Wed, Jun 28, 2023 at 7:14 PM Ilya Maximets wrote: > > On 6/28/23 05:27, Jason Wang wrote: > > On Wed, Jun 28, 2023 at 6:45 AM Ilya Maximets wrote: > >> > >> On 6/27/23 04:54, Jason Wang wrote: > >>> On Mon, Jun 26, 2023 at 9:17 PM Ilya Maximets wrote: > > On 6/26/23 08:32, Jason Wan

Re: [QEMU PATCH v2 0/1] S3 support

Hi all, V2 patch of kernel is https://lore.kernel.org/lkml/20230630073448.842767-1-jiqian.c...@amd.com/T/#t. On 2023/6/30 15:00, Jiqian Chen wrote: > v2: > > Hi all, > > Thanks to Marc-André Lureau, Robert Beckett and Gerd Hoffmann for > their advice and guidance. V2 makes below changes: > >

Re: [PATCH v6 02/20] hw/riscv/virt.c: skip 'mmu-type' FDT if satp mode not set

On 6/30/23 04:36, Michael Tokarev wrote: 29.06.2023 00:30, Daniel Henrique Barboza wrote: The absence of a satp mode in riscv_host_cpu_init() is causing the following error: $ sudo ./qemu/build/qemu-system-riscv64  -machine virt,accel=kvm \ -m 2G -smp 1  -nographic -snapshot \ -ker

[PATCH v5 3/7] vfio/pci: Disable INTx in vfio_realize error path

When vfio realize fails, INTx isn't disabled if it has been enabled. This may confuse host side with unhandled interrupt report. Fixes: c5478fea27ac ("vfio/pci: Respond to KVM irqchip change notifier") Signed-off-by: Zhenzhong Duan --- hw/vfio/pci.c | 3 +++ 1 file changed, 3 insertions(+) diff

[PATCH v5 5/7] vfio/migration: Change vIOMMU blocker from global to per device

vIOMMU migration blocker can be consolidated to per device default blocker, then some vIOMMU global blocker related functions and data could be removed. This change also makes vfio_mig_active() more accurate as it doesn't check for global blocker. Signed-off-by: Zhenzhong Duan --- hw/vfio/commo

[PATCH v5 6/7] vfio/migration: Free resources when vfio_migration_realize fails

When vfio_realize() succeeds, hot unplug will call vfio_exitfn() to free resources allocated in vfio_realize(); when vfio_realize() fails, vfio_exitfn() is never called and we need to free resources in vfio_realize(). In the case that vfio_migration_realize() fails, e.g: with -only-migratable & en

[PATCH v5 4/7] vfio/migration: Return bool type for some vfio migration related functions

Include: vfio_block_multiple_devices_migration(), vfio_block_giommu_migration(), vfio_block_migration(), vfio_migration_realize(). Suggested-by: Cédric Le Goater Signed-off-by: Zhenzhong Duan --- hw/vfio/common.c | 16 hw/vfio/migration.c | 19 +++

[PATCH v5 7/7] vfio/migration: Remove print of "Migration disabled"

Property enable_migration supports [on/off/auto]. In ON mode, error pointer is passed to errp and logged. In OFF mode, we doesn't need to log "Migration disabled" as it's intentional. In AUTO mode, we should only ever see errors or warnings if the device supports migration and an error or incompati

[PATCH v5 0/7] VFIO migration related refactor and bug fix

Hello, PATCH4,5,7 refactors the VFIO migration blocker related code based on suggestions from Joao and Cedric, so that code is simpler and redundant "Migration disabled" isn't printed. But before that works, also found some hotplug bugs when testing blocker adding failed case. PATCH1-3,6 fix them

Re: [PATCH v6 02/20] hw/riscv/virt.c: skip 'mmu-type' FDT if satp mode not set

30.06.2023 10:46, Daniel Henrique Barboza wrote: On 6/30/23 04:36, Michael Tokarev wrote: .. I find it a bit worrying to see people run development as root and the recipes to run it as root ens up in even in commit messages.  I think it's not good practice to do it like this, but more importan

[PATCH v2 00/46] Add LoongArch LASX instructions

Hi, This series adds LoongArch LASX instructions. About test: We use RISU test the LoongArch LASX instructions. QEMU: https://github.com/loongson/qemu/tree/tcg-old-abi-support-lasx RISU: https://github.com/loongson/risu/tree/loongarch-suport-lasx Please review, Thanks. Changes for v2:

[PATCH v2 02/46] target/loongarch: meson.build support build LASX

Signed-off-by: Song Gao --- target/loongarch/insn_trans/trans_lasx.c.inc | 6 ++ target/loongarch/translate.c | 1 + 2 files changed, 7 insertions(+) create mode 100644 target/loongarch/insn_trans/trans_lasx.c.inc diff --git a/target/loongarch/insn_trans/trans_lasx.c.inc b/

[PATCH v2 41/46] target/loongarch: Implement xvinsgr2vr xvpickve2gr

This patch includes: - XVINSGR2VR.{W/D}; - XVPICKVE2GR.{W/D}[U]. Signed-off-by: Song Gao --- target/loongarch/disas.c | 18 target/loongarch/insn_trans/trans_lasx.c.inc | 30 target/loongarch/insns.decode| 7 + 3 files ch

[PATCH v2 08/46] target/loongarch: Implement xvsadd/xvssub

This patch includes: - XVSADD.{B/H/W/D}[U]; - XVSSUB.{B/H/W/D}[U]. Signed-off-by: Song Gao --- target/loongarch/disas.c | 17 + target/loongarch/insn_trans/trans_lasx.c.inc | 17 + target/loongarch/insns.decode| 18 +

[PATCH v2 23/46] target/loognarch: Implement xvldi

This patch includes: - XVLDI. Signed-off-by: Song Gao --- target/loongarch/disas.c | 7 +++ target/loongarch/insn_trans/trans_lasx.c.inc | 2 ++ target/loongarch/insn_trans/trans_lsx.c.inc | 6 -- target/loongarch/insns.decode| 2 ++ 4 files changed,

[PATCH v2 46/46] target/loongarch: CPUCFG support LASX

Signed-off-by: Song Gao --- target/loongarch/cpu.c | 1 + 1 file changed, 1 insertion(+) diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c index c9f9cbb19d..aeccbb42e6 100644 --- a/target/loongarch/cpu.c +++ b/target/loongarch/cpu.c @@ -392,6 +392,7 @@ static void loongarch_la464_init

[PATCH v2 29/46] target/loongarch: Implement xvsrlrn xvsrarn

This patch includes: - XVSRLRN.{B.H/H.W/W.D}; - XVSRARN.{B.H/H.W/W.D}; - XVSRLRNI.{B.H/H.W/W.D/D.Q}; - XVSRARNI.{B.H/H.W/W.D/D.Q}. Signed-off-by: Song Gao --- target/loongarch/disas.c | 16 ++ target/loongarch/helper.h| 30 +-- target/loongarch/insn_tran

[PATCH v2 06/46] target/loongarch: Implement xvaddi/xvsubi

This patch includes: - XVADDI.{B/H/W/D}U; - XVSUBI.{B/H/W/D}U. Signed-off-by: Song Gao --- target/loongarch/disas.c | 14 ++ target/loongarch/insn_trans/trans_lasx.c.inc | 9 ++ target/loongarch/insn_trans/trans_lsx.c.inc | 136 +-- target/loongarch/insns.

[PATCH v2 22/46] target/loongarch: Implement xvmskltz/xvmskgez/xvmsknz

This patch includes: - XVMSKLTZ.{B/H/W/D}; - XVMSKGEZ.B; - XVMSKNZ.B. Signed-off-by: Song Gao --- target/loongarch/disas.c | 7 ++ target/loongarch/helper.h| 12 +- target/loongarch/insn_trans/trans_lasx.c.inc | 7 ++ target/loongarch/insns.decode

[PATCH v2 14/46] target/loongarch: Implement xvmax/xvmin

This patch includes: - XVMAX[I].{B/H/W/D}[U]; - XVMIN[I].{B/H/W/D}[U]. Signed-off-by: Song Gao --- target/loongarch/disas.c | 34 ++ target/loongarch/insn_trans/trans_lasx.c.inc | 36 target/loongarch/insns.decode| 36 +

[PATCH v2 40/46] target/loongarch: Implement xvbitsel xvset

This patch includes: - XVBITSEL.V; - XVBITSELI.B; - XVSET{EQZ/NEZ}.V; - XVSETANYEQZ.{B/H/W/D}; - XVSETALLNEZ.{B/H/W/D}. Signed-off-by: Song Gao --- target/loongarch/disas.c | 19 + target/loongarch/helper.h| 16 target/loongarch/insn_trans

[PATCH v2 01/46] target/loongarch: Add LASX data support

Signed-off-by: Song Gao --- linux-user/loongarch64/signal.c | 1 + target/loongarch/cpu.c | 1 + target/loongarch/cpu.h | 24 +++- target/loongarch/gdbstub.c | 1 + target/loongarch/internals.h| 22 -- target/loongarch/lsx_helper.c |

[PATCH v2 04/46] target/loongarch: Implement xvadd/xvsub

This patch includes: - XVADD.{B/H/W/D/Q}; - XVSUB.{B/H/W/D/Q}. Signed-off-by: Song Gao --- target/loongarch/disas.c | 23 + target/loongarch/insn_trans/trans_lasx.c.inc | 52 +- target/loongarch/insn_trans/trans_lsx.c.inc | 511 +-- target/loongarch/insns.d

[PATCH v2 39/46] target/loongarch: Implement xvfcmp

This patch includes: - XVFCMP.cond.{S/D}. Signed-off-by: Song Gao --- target/loongarch/disas.c | 94 target/loongarch/helper.h| 8 +- target/loongarch/insn_trans/trans_lasx.c.inc | 3 + target/loongarch/insn_trans/trans_lsx.c.inc |

[PATCH v2 05/46] target/loongarch: Implement xvreplgr2vr

This patch includes: - XVREPLGR2VR.{B/H/W/D}. Signed-off-by: Song Gao --- target/loongarch/disas.c | 10 ++ target/loongarch/insn_trans/trans_lasx.c.inc | 5 + target/loongarch/insn_trans/trans_lsx.c.inc | 13 +++-- target/loongarch/insns.decode

[PATCH v2 36/46] target/loongarch: Implement LASX fpu arith instructions

This patch includes: - XVF{ADD/SUB/MUL/DIV}.{S/D}; - XVF{MADD/MSUB/NMADD/NMSUB}.{S/D}; - XVF{MAX/MIN}.{S/D}; - XVF{MAXA/MINA}.{S/D}; - XVFLOGB.{S/D}; - XVFCLASS.{S/D}; - XVF{SQRT/RECIP/RSQRT}.{S/D}. Signed-off-by: Song Gao --- target/loongarch/disas.c | 46 +++ target

[PATCH v2 07/46] target/loongarch: Implement xvneg

This patch includes: - XVNEG.{B/H/W/D}. Signed-off-by: Song Gao --- target/loongarch/disas.c | 10 ++ target/loongarch/insn_trans/trans_lasx.c.inc | 5 + target/loongarch/insn_trans/trans_lsx.c.inc | 12 ++-- target/loongarch/insns.decode

[PATCH v2 34/46] target/loongarch: Implement xvbitclr xvbitset xvbitrev

This patch includes: - XVBITCLR[I].{B/H/W/D}; - XVBITSET[I].{B/H/W/D}; - XVBITREV[I].{B/H/W/D}. Signed-off-by: Song Gao --- target/loongarch/disas.c | 25 ++ target/loongarch/insn_trans/trans_lasx.c.inc | 27 target/loongarch/insns.decode

[PATCH v2 13/46] target/loongarch: Implement xvadda

This patch includes: - XVADDA.{B/H/W/D}. Signed-off-by: Song Gao --- target/loongarch/disas.c | 5 + target/loongarch/insn_trans/trans_lasx.c.inc | 5 + target/loongarch/insns.decode| 5 + target/loongarch/vec.h | 2 ++ target

[PATCH v2 17/46] target/loongarch; Implement xvdiv/xvmod

This patch includes: - XVDIV.{B/H/W/D}[U]; - XVMOD.{B/H/W/D}[U]. Signed-off-by: Song Gao --- target/loongarch/disas.c | 17 +++ target/loongarch/helper.h| 32 ++-- target/loongarch/insn_trans/trans_lasx.c.inc | 17 +++ targe

[PATCH v2 09/46] target/loongarch: Implement xvhaddw/xvhsubw

This patch includes: - XVHADDW.{H.B/W.H/D.W/Q.D/HU.BU/WU.HU/DU.WU/QU.DU}; - XVHSUBW.{H.B/W.H/D.W/Q.D/HU.BU/WU.HU/DU.WU/QU.DU}. Signed-off-by: Song Gao --- target/loongarch/disas.c | 17 ++ target/loongarch/helper.h | 34 +-- target/loongarch/insn_trans/

[PATCH v2 35/46] target/loongarch: Implement xvfrstp

This patch includes: - XVFRSTP[I].{B/H}. Signed-off-by: Song Gao --- target/loongarch/disas.c | 5 ++ target/loongarch/helper.h| 8 +-- target/loongarch/insn_trans/trans_lasx.c.inc | 5 ++ target/loongarch/insns.decode| 5 ++ target/loo

[PATCH v2 24/46] target/loongarch: Implement LASX logic instructions

This patch includes: - XV{AND/OR/XOR/NOR/ANDN/ORN}.V; - XV{AND/OR/XOR/NOR}I.B. Signed-off-by: Song Gao --- target/loongarch/disas.c | 12 target/loongarch/insn_trans/trans_lasx.c.inc | 11 +++ target/loongarch/insn_trans/trans_lsx.c.inc | 5 +++-- targe

[PATCH v2 31/46] target/loongarch: Implement xvssrlrn xvssrarn

This patch includes: - XVSSRLRN.{B.H/H.W/W.D}; - XVSSRARN.{B.H/H.W/W.D}; - XVSSRLRN.{BU.H/HU.W/WU.D}; - XVSSRARN.{BU.H/HU.W/WU.D}; - XVSSRLRNI.{B.H/H.W/W.D/D.Q}; - XVSSRARNI.{B.H/H.W/W.D/D.Q}; - XVSSRLRNI.{BU.H/HU.W/WU.D/DU.Q}; - XVSSRARNI.{BU.H/HU.W/WU.D/DU.Q}. Signed-off-by: Song Gao --- targe

[PATCH v2 10/46] target/loongarch: Implement xvaddw/xvsubw

This patch includes: - XVADDW{EV/OD}.{H.B/W.H/D.W/Q.D}[U]; - XVSUBW{EV/OD}.{H.B/W.H/D.W/Q.D}[U]; - XVADDW{EV/OD}.{H.BU.B/W.HU.H/D.WU.W/Q.DU.D}. Signed-off-by: Song Gao --- target/loongarch/disas.c | 43 ++ target/loongarch/insn_trans/trans_lasx.c.inc | 45 +++

[PATCH v2 43/46] target/loongarch: Implement xvpack xvpick xvilv{l/h}

This patch includes: - XVPACK{EV/OD}.{B/H/W/D}; - XVPICK{EV/OD}.{B/H/W/D}; - XVILV{L/H}.{B/H/W/D}. Signed-off-by: Song Gao --- target/loongarch/disas.c | 27 +++ target/loongarch/helper.h| 52 ++--- target/loongarch/insn_trans/trans_lasx.c.inc | 27 +++

[PATCH v2 45/46] target/loongarch: Implement xvld xvst

This patch includes: - XVLD[X], XVST[X]; - XVLDREPL.{B/H/W/D}; - XVSTELM.{B/H/W/D}. Signed-off-by: Song Gao --- target/loongarch/disas.c | 24 target/loongarch/helper.h| 3 + target/loongarch/insn_trans/trans_lasx.c.inc | 49 tar

[PATCH v2 16/46] target/loongarch: Implement xvmadd/xvmsub/xvmaddw{ev/od}

This patch includes: - XVMADD.{B/H/W/D}; - XVMSUB.{B/H/W/D}; - XVMADDW{EV/OD}.{H.B/W.H/D.W/Q.D}[U]; - XVMADDW{EV/OD}.{H.BU.B/W.HU.H/D.WU.W/Q.DU.D}. Signed-off-by: Song Gao --- target/loongarch/disas.c | 34 ++ target/loongarch/insn_trans/trans_lasx.c.inc | 69

[PATCH v2 19/46] target/loongarch: Implement xvexth

This patch includes: - XVEXTH.{H.B/W.H/D.W/Q.D}; - XVEXTH.{HU.BU/WU.HU/DU.WU/QU.DU}. Signed-off-by: Song Gao --- target/loongarch/disas.c | 9 + target/loongarch/helper.h| 16 +- target/loongarch/insn_trans/trans_lasx.c.inc | 9 + target/loongarch/ins

[PATCH v2 38/46] target/loongarch: Implement xvseq xvsle xvslt

This patch includes: - XVSEQ[I].{B/H/W/D}; - XVSLE[I].{B/H/W/D}[U]; - XVSLT[I].{B/H/W/D/}[U]. Signed-off-by: Song Gao --- target/loongarch/disas.c | 43 +++ target/loongarch/insn_trans/trans_lasx.c.inc | 43 +++ target/loongarch/insn_trans/trans_lsx.c.inc | 263 ++-

[PATCH v2 28/46] target/loongarch: Implement xvsrln xvsran

This patch includes: - XVSRLN.{B.H/H.W/W.D}; - XVSRAN.{B.H/H.W/W.D}; - XVSRLNI.{B.H/H.W/W.D/D.Q}; - XVSRANI.{B.H/H.W/W.D/D.Q}. Signed-off-by: Song Gao --- target/loongarch/disas.c | 16 ++ target/loongarch/helper.h| 48 ++--- target/loongarch/insn_trans/

[PATCH v2 12/46] target/loongarch: Implement xvabsd

This patch includes: - XVABSD.{B/H/W/D}[U]. Signed-off-by: Song Gao --- target/loongarch/disas.c | 9 + target/loongarch/insn_trans/trans_lasx.c.inc | 9 + target/loongarch/insns.decode| 9 + target/loongarch/vec.h

[PATCH v2 42/46] target/loongarch: Implement xvreplve xvinsve0 xvpickve xvb{sll/srl}v

This patch includes: - XVREPLVE.{B/H/W/D}; - XVREPL128VEI.{B/H/W/D}; - XVREPLVE0.{B/H/W/D/Q}; - XVINSVE0.{W/D}; - XVPICKVE.{W/D}; - XVBSLL.V, XVBSRL.V. Signed-off-by: Song Gao --- target/loongarch/disas.c | 28 + target/loongarch/helper.h| 5 + targ

[PATCH v2 37/46] target/loongarch: Implement LASX fpu fcvt instructions

This patch includes: - XVFCVT{L/H}.{S.H/D.S}; - XVFCVT.{H.S/S.D}; - XVFRINT[{RNE/RZ/RP/RM}].{S/D}; - XVFTINT[{RNE/RZ/RP/RM}].{W.S/L.D}; - XVFTINT[RZ].{WU.S/LU.D}; - XVFTINT[{RNE/RZ/RP/RM}].W.D; - XVFTINT[{RNE/RZ/RP/RM}]{L/H}.L.S; - XVFFINT.{S.W/D.L}[U]; - X[CVFFINT.S.L, VFFINT{L/H}.D.W. Signed-off

[PATCH v2 03/46] target/loongarch: Add CHECK_ASXE maccro for check LASX enable

Reviewed-by: Richard Henderson Signed-off-by: Song Gao --- target/loongarch/cpu.c | 2 ++ target/loongarch/cpu.h | 2 ++ target/loongarch/insn_trans/trans_lasx.c.inc | 10 ++ 3 files changed, 14 insertions(+) diff --git a/target/loongarch/cp

[PATCH v2 32/46] target/loongarch: Implement xvclo xvclz

This patch includes: - XVCLO.{B/H/W/D}; - XVCLZ.{B/H/W/D}. Signed-off-by: Song Gao --- target/loongarch/disas.c | 9 ++ target/loongarch/helper.h| 16 +- target/loongarch/insn_trans/trans_lasx.c.inc | 9 ++ target/loongarch/insns.decode

[PATCH v2 26/46] target/loongarch: Implement xvsllwil xvextl

This patch includes: - XVSLLWIL.{H.B/W.H/D.W}; - XVSLLWIL.{HU.BU/WU.HU/DU.WU}; - XVEXTL.Q.D, VEXTL.QU.DU. Signed-off-by: Song Gao --- target/loongarch/disas.c | 9 ++ target/loongarch/helper.h| 16 +- target/loongarch/insn_trans/trans_lasx.c.inc | 9 +

[PATCH v2 11/46] target/loongarch: Implement xavg/xvagr

This patch includes: - XVAVG.{B/H/W/D/}[U]; - XVAVGR.{B/H/W/D}[U]. Signed-off-by: Song Gao --- target/loongarch/disas.c | 17 + target/loongarch/insn_trans/trans_lasx.c.inc | 17 + target/loongarch/insns.decode| 17 +

Re: [PATCH 2/2] accel/tcg: add assert() check in tb_invalidate_phys_page_range__locked()

29.06.2023 11:25, Mark Cave-Ayland wrote: Add an assert() check in tb_invalidate_phys_page_range__locked() to ensure that both the start and last addresses are within the same target page. Note that due to performance concerns the check is only enabled when QEMU is configured with --enable-debug-

[PATCH v2 27/46] target/loongarch: Implement xvsrlr xvsrar

This patch includes: - XVSRLR[I].{B/H/W/D}; - XVSRAR[I].{B/H/W/D}. Signed-off-by: Song Gao --- target/loongarch/disas.c | 18 +++ target/loongarch/helper.h| 34 ++-- target/loongarch/insn_trans/trans_lasx.c.inc | 18 +++ tar

Re: [PATCH 0/4] fpu: Add float64_to_int{32,64}_modulo

On Sat, May 27, 2023 at 4:19 PM Richard Henderson wrote: > > Extract some common code from Alpha and Arm, and which will > shortly also be required by the RISC-V Zfa extension. > Added a new test for Alpha; I already had a RISU test for Arm. Thank you for providing a generic implementation of thi

[PATCH v2 30/46] target/loongarch: Implement xvssrln xvssran

This patch includes: - XVSSRLN.{B.H/H.W/W.D}; - XVSSRAN.{B.H/H.W/W.D}; - XVSSRLN.{BU.H/HU.W/WU.D}; - XVSSRAN.{BU.H/HU.W/WU.D}; - XVSSRLNI.{B.H/H.W/W.D/D.Q}; - XVSSRANI.{B.H/H.W/W.D/D.Q}; - XVSSRLNI.{BU.H/HU.W/WU.D/DU.Q}; - XVSSRANI.{BU.H/HU.W/WU.D/DU.Q}. Signed-off-by: Song Gao --- target/loonga

[PATCH v2 18/46] target/loongarch: Implement xvsat

This patch includes: - XVSAT.{B/H/W/D}[U]. Signed-off-by: Song Gao --- target/loongarch/disas.c | 9 + target/loongarch/insn_trans/trans_lasx.c.inc | 9 + target/loongarch/insns.decode| 9 + target/loongarch/vec_helper.c

[PATCH v2 33/46] target/loongarch: Implement xvpcnt

This patch includes: - VPCNT.{B/H/W/D}. Signed-off-by: Song Gao --- target/loongarch/disas.c | 5 + target/loongarch/helper.h| 8 +++ target/loongarch/insn_trans/trans_lasx.c.inc | 5 + target/loongarch/insns.decode| 5 +

[PATCH v2 20/46] target/loongarch: Implement vext2xv

This patch includes: - VEXT2XV.{H/W/D}.B, VEXT2XV.{HU/WU/DU}.BU; - VEXT2XV.{W/D}.B, VEXT2XV.{WU/DU}.HU; - VEXT2XV.D.W, VEXT2XV.DU.WU. Signed-off-by: Song Gao --- target/loongarch/disas.c | 13 + target/loongarch/helper.h| 13 + target/loong

Re: [PATCH v3 0/6] eBPF RSS through QMP support.

On Fri, Jun 30, 2023 at 01:06:22PM +0800, Jason Wang wrote: > On Thu, Jun 15, 2023 at 6:29 AM Andrew Melnychenko wrote: > > > > This series of patches provides the ability to retrieve eBPF program > > through qmp, so management application may load bpf blob with proper > > capabilities. > > Now,

[PATCH v2 21/46] target/loongarch: Implement xvsigncov

This patch includes: - XVSIGNCOV.{B/H/W/D}. Signed-off-by: Song Gao --- target/loongarch/disas.c | 5 + target/loongarch/insn_trans/trans_lasx.c.inc | 5 + target/loongarch/insns.decode| 5 + target/loongarch/vec.h | 2 ++ tar

[PATCH v2 44/46] target/loongarch: Implement xvshuf xvperm{i} xvshuf4i xvextrins

This patch includes: - XVSHUF.{B/H/W/D}; - XVPERM.W; - XVSHUF4i.{B/H/W/D}; - XVPERMI.{W/D/Q}; - XVEXTRINS.{B/H/W/D}. Signed-off-by: Song Gao --- target/loongarch/disas.c | 21 +++ target/loongarch/helper.h| 33 ++-- target/loongarch/insn_trans/trans_lasx

[PATCH v2 15/46] target/loongarch: Implement xvmul/xvmuh/xvmulw{ev/od}

This patch includes: - XVMUL.{B/H/W/D}; - XVMUH.{B/H/W/D}[U]; - XVMULW{EV/OD}.{H.B/W.H/D.W/Q.D}[U]; - XVMULW{EV/OD}.{H.BU.B/W.HU.H/D.WU.W/Q.DU.D}. Signed-off-by: Song Gao --- target/loongarch/disas.c | 38 +++ target/loongarch/insn_trans/trans_lasx.c.inc | 68

Re: [PATCH v2] piix: fix regression during unplug in Xen HVM domUs

Am 30. Juni 2023 07:29:21 UTC schrieb Olaf Hering : >Wed, 28 Jun 2023 09:27:16 + Bernhard Beschow : > >> Would you mind sending a patch fixing the BMIBA register to be reset as 32 >> bit? > >Will do so next week. Great! Perhaps it could then be picked up by maintainers together with my oth

[PATCH v2 25/46] target/loongarch: Implement xvsll xvsrl xvsra xvrotr

This patch includes: - XVSLL[I].{B/H/W/D}; - XVSRL[I].{B/H/W/D}; - XVSRA[I].{B/H/W/D}; - XVROTR[I].{B/H/W/D}. Signed-off-by: Song Gao --- target/loongarch/disas.c | 36 target/loongarch/insn_trans/trans_lasx.c.inc | 36 target/loongar

Re: [PATCH v3 25/36] docs/devel: introduce some key concepts for QOM development

Philippe Mathieu-Daudé writes: > On 27/6/23 18:09, Alex Bennée wrote: >> Using QOM correctly is increasingly important to maintaining a modern >> code base. However the current documentation skips some important >> concepts before launching into a simple example. Lets: >>- at least mention

Re: [RFC PATCH 1/3] target/ppc: Add LPAR-per-core vs per-thread mode flag

On Thu, 29 Jun 2023 at 02:17, Nicholas Piggin wrote: > > The Power ISA has the concept of sub-processors: > > Hardware is allowed to sub-divide a multi-threaded processor into > "sub-processors" that appear to privileged programs as multi-threaded > processors with fewer threads. > > POWER9

Re: [PATCH v3 0/6] eBPF RSS through QMP support.

On Fri, Jun 30, 2023 at 4:04 PM Daniel P. Berrangé wrote: > > On Fri, Jun 30, 2023 at 01:06:22PM +0800, Jason Wang wrote: > > On Thu, Jun 15, 2023 at 6:29 AM Andrew Melnychenko > > wrote: > > > > > > This series of patches provides the ability to retrieve eBPF program > > > through qmp, so manag

Re: [PATCH v6 5/5] hw/pci: ensure PCIE devices are plugged into only slot 0 of PCIE port

On Fri, Jun 30, 2023 at 01:11:33PM +0530, Ani Sinha wrote: > > > > Thus the check for unoccupied function 0 needs to use pci_is_vf() instead > > of checking ARI capability, and that can happen in do_pci_register_device(). > > > >> Also where do you propose we move the check? > > > > In pci_qdev

Re: [PATCH v6 5/5] hw/pci: ensure PCIE devices are plugged into only slot 0 of PCIE port

> On 30-Jun-2023, at 2:02 PM, Michael S. Tsirkin wrote: > > On Fri, Jun 30, 2023 at 01:11:33PM +0530, Ani Sinha wrote: >>> >>> Thus the check for unoccupied function 0 needs to use pci_is_vf() instead >>> of checking ARI capability, and that can happen in do_pci_register_device(). >>>

Re: [PATCH v6 5/5] hw/pci: ensure PCIE devices are plugged into only slot 0 of PCIE port

On Fri, Jun 30, 2023 at 02:06:59PM +0530, Ani Sinha wrote: > > > > On 30-Jun-2023, at 2:02 PM, Michael S. Tsirkin wrote: > > > > On Fri, Jun 30, 2023 at 01:11:33PM +0530, Ani Sinha wrote: > >>> > >>> Thus the check for unoccupied function 0 needs to use pci_is_vf() instead > >>> of checking A

Re: [PULL 18/42] tests: avocado: boot_linux_console: Add test case for bpim2u

在 2023/6/30 15:27, Thomas Huth 写道: On 30/06/2023 08.15, qianfan wrote: 在 2023/6/29 19:35, Thomas Huth 写道: On 06/06/2023 11.47, Peter Maydell wrote: From: qianfan Zhao Add test case for booting from initrd and sd card. Signed-off-by: qianfan Zhao Reviewed-by: Niek Linnenbank Tested-by

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