From: Philippe Mathieu-Daudé
Instead of having "virtio/virtio-bus.h" implicitly included,
explicitly include it, to avoid when rearranging headers:
hw/virtio/vhost-vsock-common.c: In function ‘vhost_vsock_common_start’:
hw/virtio/vhost-vsock-common.c:51:5: error: unknown type name
‘VirtioBu
From: Suravee Suthikulpanit
Currently, pc-q35 and pc-i44fx machine models are default to use SMBIOS 2.8
(32-bit entry point). Since SMBIOS 3.0 (64-bit entry point) is now fully
supported since QEMU 7.0, default to use SMBIOS 3.0 for newer machine
models. This is necessary to avoid the following m
On Fri, 16 Jun 2023 11:23:10 +0800
Tao Su wrote:
> From: Qian Wen
>
> Emerald Rapids (EMR) is the next generation of Xeon server processor
> after Sapphire Rapids (SPR).
>
> Currently, regarding the feature set that can be exposed to guest, there
> isn't any one new comparing with SPR cpu mode
On Mon, May 22, 2023 at 04:00:39PM +0530, Ani Sinha wrote:
> Currently the meson based QEMU build process locates the iasl binary from the
> current PATH and other locations [1] and uses that to set CONFIG_IASL in
> config-host.h header.This is then used at compile time by bios-tables-test to
> set
> This is implementation-dependent : if the
> implementation reports CTR_EL0.{DIC,IDC} == {1,1} then
> it doesn't need icache invalidation or data cache clean
> to provide data-to-instruction or instruction-to-data
> coherence. This is currently not true for any CPU QEMU
> models, but the Neoverse-
On Fri, 16 Jun 2023 11:23:07 +0800
Tao Su wrote:
> MCDT_NO bit indicates HW contains the security fix and doesn't need to
> be mitigated to avoid data-dependent behaviour for certain instructions.
> It needs no hypervisor support. Treat it as supported regardless of what
> KVM reports.
>
> Signe
> On 26-Jun-2023, at 6:28 PM, Michael S. Tsirkin wrote:
>
> On Mon, May 22, 2023 at 04:00:39PM +0530, Ani Sinha wrote:
>> Currently the meson based QEMU build process locates the iasl binary from the
>> current PATH and other locations [1] and uses that to set CONFIG_IASL in
>> config-host.h h
Richard Henderson wrote:
> On 6/26/23 00:01, Juan Quintela wrote:
>> Richard Henderson wrote:
>>> On 6/22/23 18:54, Juan Quintela wrote:
The following changes since commit
b455ce4c2f300c8ba47cba7232dd03261368a4cb:
Merge tag 'q800-for-8.1-pull-request'
ofhttps://github.com
Richard Henderson wrote:
> On 6/22/23 18:54, Juan Quintela wrote:
>> The following changes since commit b455ce4c2f300c8ba47cba7232dd03261368a4cb:
>>Merge tag 'q800-for-8.1-pull-request'
>> ofhttps://github.com/vivier/qemu-m68k into staging (2023-06-22
>> 10:18:32 +0200)
>> are available in th
On 6/26/23 08:32, Jason Wang wrote:
> On Sun, Jun 25, 2023 at 3:06 PM Jason Wang wrote:
>>
>> On Fri, Jun 23, 2023 at 5:58 AM Ilya Maximets wrote:
>>>
>>> AF_XDP is a network socket family that allows communication directly
>>> with the network device driver in the kernel, bypassing most or all
>
On Fri, 16 Jun 2023 11:23:08 +0800
Tao Su wrote:
> Currently, bit 13, 14, 15 and 24 of MSR_IA32_ARCH_CAPABILITIES are
> disclosed for fixing security issues, so add those bit definitions
> and feature names.
>
> Signed-off-by: Tao Su
Reviewed-by: Igor Mammedov
> ---
> target/i386/cpu.c | 4
On Sun, 25 Jun 2023 at 20:17, Nicholas Piggin wrote:
>
> Apple sungem devices are expected to have WOL MMIO registers.
> Add a region to prevent transaction failures, and implement the
> WOL-disable CSR write because the Linux driver reset writes
> this.
>
> Signed-off-by: Nicholas Piggin
Review
From: Shiju Jose
Add avocado tests for aarch64 S-EL2, include booting and
run xtest on linux terminal.
The prebuilt S-EL2 images are corresponding to the
https://github.com/jenswi-linaro/manifest.git \
-m qemu_v8.xml -b qemu_sel2
How to run
==
"make check-avocado" in qemu/build
or
with
On Fri, 16 Jun 2023 11:23:09 +0800
Tao Su wrote:
> From: Lei Wang
>
> Latest stepping (8) of SapphireRapids has bit 13, 14 and 15 of
> MSR_IA32_ARCH_CAPABILITIES enabled, which are related to some security
> fixes.
>
> Add version 2 of SapphireRapids CPU model with those bits enabled also.
do
On Mon, Jun 26, 2023 at 06:33:14PM +0530, Ani Sinha wrote:
>
>
> > On 26-Jun-2023, at 6:28 PM, Michael S. Tsirkin wrote:
> >
> > On Mon, May 22, 2023 at 04:00:39PM +0530, Ani Sinha wrote:
> >> Currently the meson based QEMU build process locates the iasl binary from
> >> the
> >> current PATH
Hello Avihai,
On 6/26/23 10:23, Avihai Horon wrote:
The major parts of VFIO migration are supported today in QEMU. This
includes basic VFIO migration, device dirty page tracking and precopy
support.
Thus, at this point in time, it seems appropriate to make VFIO migration
non-experimental: remov
On Mon, 26 Jun 2023 08:29:19 -0400
"Michael S. Tsirkin" wrote:
> From: BALATON Zoltan
>
> On pegasos2 which has ACPI as part of VT8231 south bridge the board
> firmware writes PM control register by accessing the second byte so
> addr will be 1. This wasn't handled correctly and the write went
The stack array is only referenced from the start-up code (which is
shared between the s390-ccw.img and the s390-netboot.img), but it is
currently declared twice, once in main.c and once in netmain.c.
It makes more sense to declare this in start.S instead - which will
also be helpful in the next pa
start.S currently cannot be compiled with Clang 16 and binutils 2.40:
ld: start.o(.text+0x8): misaligned symbol `__bss_start' (0xc1e5) for
relocation R_390_PC32DBL
According to the built-in linker script of ld, the symbol __bss_start
can actually point *before* the .bss section and does not
Providing the space of a stack frame is the duty of the caller,
so we should reserve 160 bytes before jumping into the main function.
Otherwise the main() function might write past the stack array.
While we're at it, add a proper STACK_SIZE macro for the stack size
instead of using magic numbers (
Main motivation of this series was a bug that showed up when compiling
with Clang 16 and binutils 2.40 (which has been reported in Fedora ELN, see
https://bugzilla.redhat.com/show_bug.cgi?id=2216662). This is fixed in
the fourth patch.
While working on this issue, I came accross some other issues
start.S is currently indented with a mixture of spaces and tabs, which
is quite ugly. QEMU coding style says indentation should be 4 spaces,
and this is also what we are using in the assembler files in the
tests/tcg/s390x/ folder already, so let's adjust start.S accordingly.
Signed-off-by: Thomas
On 6/23/23 14:21, Alex Bennée wrote:
Using QOM correctly is increasingly important to maintaining a modern
code base. However the current documentation skips some important
concepts before launching into a simple example. Lets:
- at least mention properties
- mention TYPE_OBJECT and TYPE_D
On 6/26/23 15:05, Juan Quintela wrote:
The "full logs" are
https://gitlab.com/qemu-project/qemu/-/jobs/4527202764/artifacts/download?file_type=trace
Not useful. I was hoping that there is something like when one runs
./tests/qtest/migration-test
I thought I saw some patch today that to save
On Mon, 26 Jun 2023 18:13:05 +0530
Ani Sinha wrote:
> The test attaches both a SCSI controller and a pcie-to-pci bridge on the same
> pcie-root-port.
at slot addresses ...
> This is incorrect since only one downstream device can be
> attached to a pcie-root-port.
not true in case of multifunctio
On 6/23/23 14:37, Cédric Le Goater wrote:
On 6/23/23 11:10, Peter Maydell wrote:
On Fri, 23 Jun 2023 at 09:21, Nicholas Piggin wrote:
ppc has always silently ignored access to real (physical) addresses
with nothing behind it, which can make debugging difficult at times.
It looks like the way
Paolo Bonzini writes:
> On 6/23/23 14:21, Alex Bennée wrote:
>> Using QOM correctly is increasingly important to maintaining a modern
>> code base. However the current documentation skips some important
>> concepts before launching into a simple example. Lets:
>>- at least mention propertie
On 6/26/23 15:21, Thomas Huth wrote:
start.S is currently indented with a mixture of spaces and tabs, which
is quite ugly. QEMU coding style says indentation should be 4 spaces,
and this is also what we are using in the assembler files in the
tests/tcg/s390x/ folder already, so let's adjust start
On 26/06/2023 14:20, Cédric Le Goater wrote:
> Hello Avihai,
>
> On 6/26/23 10:23, Avihai Horon wrote:
>> The major parts of VFIO migration are supported today in QEMU. This
>> includes basic VFIO migration, device dirty page tracking and precopy
>> support.
>>
>> Thus, at this point in time, it s
On 6/26/23 15:21, Thomas Huth wrote:
Providing the space of a stack frame is the duty of the caller,
so we should reserve 160 bytes before jumping into the main function.
Otherwise the main() function might write past the stack array.
While we're at it, add a proper STACK_SIZE macro for the stac
> From: Shaoqin Huang
> Sent: Monday, June 26, 2023 7:49 AM
> To: qemu-devel@nongnu.org; qemu-...@nongnu.org
> Cc: oliver.up...@linux.dev; Salil Mehta ;
> james.mo...@arm.com; gs...@redhat.com; Shaoqin Huang ;
> Cornelia Huck ; k...@vger.kernel.org; Michael S. Tsirkin
> ; Paolo Bonzini ; Peter May
On Tue, 20 Jun 2023 18:39:55 +0800
Zhao Liu wrote:
> From: Zhao Liu
>
> The number of cores/threads per socket are needed for smbios, and are
> also useful for other modules.
>
> Provide the helpers to wrap the calculation of cores/threads per socket
> so that we can avoid calculation errors c
On Tue, 20 Jun 2023 18:39:57 +0800
Zhao Liu wrote:
> From: Zhao Liu
>
> From SMBIOS 3.0 specification, thread count field means:
>
> Thread Count is the total number of threads detected by the BIOS for
> this processor socket. It is a processor-wide count, not a
> thread-per-core count. [1]
>
On Tue, 20 Jun 2023 18:39:54 +0800
Zhao Liu wrote:
> From: Zhao Liu
>
> Hi all,
>
> This is my v3 patch series based on 48ab886d3da4f ("Merge tag 'pull-
> target-arm-20230619' of https://git.linaro.org/people/pmaydell/qemu-arm
> into staging").
>
> Compared with v2 [1], v3 introduces 2 helper
On Mon, Jun 26, 2023 at 03:20:09PM +0200, Igor Mammedov wrote:
> On Mon, 26 Jun 2023 08:29:19 -0400
> "Michael S. Tsirkin" wrote:
>
> > From: BALATON Zoltan
> >
> > On pegasos2 which has ACPI as part of VT8231 south bridge the board
> > firmware writes PM control register by accessing the secon
On Mon, Jun 26, 2023 at 08:27:49AM -0400, Michael S. Tsirkin wrote:
> The following changes since commit b455ce4c2f300c8ba47cba7232dd03261368a4cb:
>
> Merge tag 'q800-for-8.1-pull-request' of
> https://github.com/vivier/qemu-m68k into staging (2023-06-22 10:18:32 +0200)
>
> are available in th
PCIE ports only have one slot, slot 0. Hence, non-zero slots are not available
for PCIE devices on PCIE root ports. Fix test_acpi_q35_tcg_no_acpi_hotplug()
so that the test does not use them.
Signed-off-by: Ani Sinha
Reviewed-by: Igor Mammedov
---
tests/qtest/bios-tables-test.c | 4 ++--
1 file
We are going to fix bio-tables-test in the next patch and hence need to
make sure the acpi tests continue to pass.
Signed-off-by: Ani Sinha
Acked-by: Igor Mammedov
---
tests/qtest/bios-tables-test-allowed-diff.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/tests/qtest/bios-tables-test-al
On Mon, Jun 26, 2023 at 03:30:14PM +0200, Igor Mammedov wrote:
> On Mon, 26 Jun 2023 18:13:05 +0530
> Ani Sinha wrote:
>
> > The test attaches both a SCSI controller and a pcie-to-pci bridge on the
> > same
> > pcie-root-port.
>
> at slot addresses ...
> > This is incorrect since only one downs
Patches 1-4:
Fix tests so that devices do not use non-zero slots on the pcie root
ports. PCIE ports only have one slot, so PCIE devices can only be
plugged into slot 0 on a PCIE port.
Patch 5:
Enforce only one slot on PCIE port.
The test fixes must be applied before the QEMU change that checks fo
PCI Express ports only have one slot, so PCI Express devices can only be
plugged into slot 0 on a PCIE port. Enforce it.
CC: jus...@redhat.com
CC: imamm...@redhat.com
Resolves: https://bugzilla.redhat.com/show_bug.cgi?id=2128929
Signed-off-by: Ani Sinha
Reviewed-by: Julia Suvorova
---
hw/pci/pc
The test attaches both a SCSI controller and a pcie-to-pci bridge on the same
pcie-root-port on slot 0. This is incorrect since a single downstream device
can be attached to a non-multifunction pcie-root-port on slot 0. Additionally
using pcie.0 as id for pcie-root-port is incorrect as that id is r
Some fixes were committed in bios-tables-test in the previous commit. Update
the acpi blob and clear bios-tables-test-allowed-diff.h so that the test
continues to pass with the changes in the bios-tables-test.
Following is the asl diff between the old and the newly updated blob:
@@ -1,30 +1,30 @@
Ani, two versions a day is too much, pls don't unless first one
has been sent by mistake or something. then explain what
it was pls.
On Mon, Jun 26, 2023 at 07:23:19PM +0530, Ani Sinha wrote:
> Patches 1-4:
> Fix tests so that devices do not use non-zero slots on the pcie root
> ports. PCIE ports
> On 26-Jun-2023, at 7:24 PM, Michael S. Tsirkin wrote:
>
> Ani, two versions a day is too much,
So you suggesting I slow down my CPU freq? :-)
> pls don't unless first one
> has been sent by mistake or something. then explain what
> it was pls.
I did say
v4: reword commit log for patch
> On 26-Jun-2023, at 7:26 PM, Ani Sinha wrote:
>
>
>
>> On 26-Jun-2023, at 7:24 PM, Michael S. Tsirkin wrote:
>>
>> Ani, two versions a day is too much,
>
> So you suggesting I slow down my CPU freq? :-)
Btw, the libvirt guys does this better in this respect I think. The maintainer
tak
On 6/21/23 15:56, Anton Johansson via wrote:
Use vaddr for guest virtual addresses for functions dealing with page
flags.
Signed-off-by: Anton Johansson
Reviewed-by: Richard Henderson
---
accel/tcg/user-exec.c| 44 +---
include/exec/cpu-all.h |
No need to generate TCG-specific decodetree files
when TCG is disabled.
Signed-off-by: Philippe Mathieu-Daudé
---
target/ppc/meson.build | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/ppc/meson.build b/target/ppc/meson.build
index a69f174f41..4c2635039e 100644
--- a/t
The guest address, raddr, should be unsigned, aka abi_ulong.
The host addresses should be cast via *intptr_t not long.
Drop the inline and fix two other whitespace issues.
Signed-off-by: Richard Henderson
---
linux-user/syscall.c | 13 ++---
1 file changed, 6 insertions(+), 7 deletions(-
On 6/26/23 13:14, Paolo Bonzini wrote:
The following changes since commit 79dbd910c9ea6ca38f8e1b2616b1e5e885b85bd3:
Merge tag 'hppa-boot-reboot-fixes-pull-request'
ofhttps://github.com/hdeller/qemu-hppa into staging (2023-06-25 08:58:49 +0200)
are available in the Git repository at:
ht
On Mon, 26 Jun 2023 09:53:40 -0400
"Michael S. Tsirkin" wrote:
> On Mon, Jun 26, 2023 at 03:30:14PM +0200, Igor Mammedov wrote:
> > On Mon, 26 Jun 2023 18:13:05 +0530
> > Ani Sinha wrote:
> >
> > > The test attaches both a SCSI controller and a pcie-to-pci bridge on the
> > > same
> > > pcie
From: John Högberg
https://gitlab.com/qemu-project/qemu/-/issues/1034
Signed-off-by: John Högberg
---
tests/tcg/aarch64/Makefile.target | 3 +-
tests/tcg/aarch64/icivau.c| 189 ++
2 files changed, 191 insertions(+), 1 deletion(-)
create mode 100644 tests/
Changes since v3:
1) Reworded the first commit comment to note that the need to clear
cache is implementation-dependent.
2) CTR_EL0.DIC is now cleared in user mode to indicate that IC IVAU
must be used.
3) The test case now only uses DC CVAU / IC IVAU when this is
required, as indicated b
From: John Högberg
Unlike architectures with precise self-modifying code semantics
(e.g. x86) ARM processors do not maintain coherency for instruction
execution and memory, requiring an instruction synchronization
barrier on every core that will execute the new code, and on many
models also the e
On Mon, 26 Jun 2023 19:23:23 +0530
Ani Sinha wrote:
> The test attaches both a SCSI controller and a pcie-to-pci bridge on the same
> pcie-root-port on slot 0.
statement is right only for bridge, while it's still incorrect for storage part
(see add_scsi_controller/add_virtio_disk)
they try to use
On 6/8/23 19:49, ~jhogberg wrote:
From: John Högberg
Unlike architectures with precise self-modifying code semantics
(e.g. x86) ARM processors do not maintain coherency for instruction
execution and memory, requiring an instruction synchronization
barrier on every core that will execute the new
Am 26.06.23 um 15:21 schrieb Thomas Huth:
Providing the space of a stack frame is the duty of the caller,
so we should reserve 160 bytes before jumping into the main function.
Otherwise the main() function might write past the stack array.
While we're at it, add a proper STACK_SIZE macro for the
Am 26.06.23 um 15:21 schrieb Thomas Huth:
diff --git a/pc-bios/s390-ccw/start.S b/pc-bios/s390-ccw/start.S
index 29b0a9ece0..47ef6e8aa8 100644
--- a/pc-bios/s390-ccw/start.S
+++ b/pc-bios/s390-ccw/start.S
@@ -120,3 +120,8 @@ external_new_mask:
.quad 0x00018000
io_new_mask:
On 6/26/23 15:59, Richard Henderson wrote:
On 6/21/23 15:56, Anton Johansson via wrote:
Use vaddr for guest virtual addresses for functions dealing with page
flags.
Signed-off-by: Anton Johansson
Reviewed-by: Richard Henderson
---
accel/tcg/user-exec.c | 44 +---
On 6/26/23 16:02, Richard Henderson wrote:
The guest address, raddr, should be unsigned, aka abi_ulong.
The host addresses should be cast via *intptr_t not long.
Drop the inline and fix two other whitespace issues.
Signed-off-by: Richard Henderson
---
linux-user/syscall.c | 13 ++---
On 6/26/23 16:54, Christian Borntraeger wrote:
Am 26.06.23 um 15:21 schrieb Thomas Huth:
diff --git a/pc-bios/s390-ccw/start.S b/pc-bios/s390-ccw/start.S
index 29b0a9ece0..47ef6e8aa8 100644
--- a/pc-bios/s390-ccw/start.S
+++ b/pc-bios/s390-ccw/start.S
@@ -120,3 +120,8 @@ external_new_mask:
On 6/26/23 15:40, Joao Martins wrote:
On 26/06/2023 14:20, Cédric Le Goater wrote:
Hello Avihai,
On 6/26/23 10:23, Avihai Horon wrote:
The major parts of VFIO migration are supported today in QEMU. This
includes basic VFIO migration, device dirty page tracking and precopy
support.
Thus, at th
On 6/26/23 14:27, Michael S. Tsirkin wrote:
The following changes since commit b455ce4c2f300c8ba47cba7232dd03261368a4cb:
Merge tag 'q800-for-8.1-pull-request' ofhttps://github.com/vivier/qemu-m68k
into staging (2023-06-22 10:18:32 +0200)
are available in the Git repository at:
https://
On Mon, Jun 26, 2023 at 07:29:26PM +0530, Ani Sinha wrote:
>
>
> > On 26-Jun-2023, at 7:26 PM, Ani Sinha wrote:
> >
> >
> >
> >> On 26-Jun-2023, at 7:24 PM, Michael S. Tsirkin wrote:
> >>
> >> Ani, two versions a day is too much,
> >
> > So you suggesting I slow down my CPU freq? :-)
>
>
s/pull-tcg-20230626
for you to fetch changes up to a0eaae08c7c6a59c185cf646b02f4167b2ac6ec0:
accel/tcg: Renumber TLB_DISCARD_WRITE (2023-06-26 17:33:00 +0200)
accel/tcg: Replace target_ulong in some APIs
accel/tcg: Remove CONFIG_PROF
From: Anton Johansson
Functions accessing MMULookupPageData are also updated.
Signed-off-by: Anton Johansson
Reviewed-by: Richard Henderson
Message-Id: <20230621135633.1649-6-a...@rev.ng>
Signed-off-by: Richard Henderson
---
accel/tcg/cputlb.c | 30 +++---
1 file chan
From: Anton Johansson
Update atomic_mmu_lookup() and cpu_mmu_lookup() to take the guest
virtual address as a vaddr instead of a target_ulong.
Signed-off-by: Anton Johansson
Reviewed-by: Richard Henderson
Message-Id: <20230621135633.1649-10-a...@rev.ng>
Signed-off-by: Richard Henderson
---
ac
From: Anton Johansson
Related functions dealing with the jump cache are also updated.
Signed-off-by: Anton Johansson
Reviewed-by: Richard Henderson
Message-Id: <20230621135633.1649-8-a...@rev.ng>
Signed-off-by: Richard Henderson
---
accel/tcg/tb-hash.h | 12 ++--
accel/tcg/tb-jm
From: Anton Johansson
Functions for probing memory accesses (and functions that call these)
are updated to take a vaddr for guest virtual addresses over
target_ulong.
Signed-off-by: Anton Johansson
Reviewed-by: Richard Henderson
Message-Id: <20230621135633.1649-9-a...@rev.ng>
Signed-off-by: Ri
From: Anton Johansson
Use vaddr for guest virtual address in translator_use_goto_tb() and
translator_loop().
Signed-off-by: Anton Johansson
Reviewed-by: Richard Henderson
Message-Id: <20230621135633.1649-11-a...@rev.ng>
Signed-off-by: Richard Henderson
---
include/exec/translator.h | 6 +++-
This frees up one bit of the primary tlb flags without
impacting the TLB_NOTDIRTY logic.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
include/exec/cpu-all.h | 8
accel/tcg/cputlb.c | 18 ++
2 files changed, 18 insertions(+), 8 deletions(
From: Alex Bennée
Balton discovered that asserts for the extract/deposit calls had a
significant impact on a lame benchmark on qemu-ppc. Replicating with:
./qemu-ppc64 ~/lsrc/tests/lame.git-svn/builds/ppc64/frontend/lame \
-h pts-trondheim-3.wav pts-trondheim-3.mp3
showed up the pack/unpa
From: Anton Johansson
Replaces target_ulong with vaddr for guest virtual addresses in tlb_*()
functions and auxilliary structs.
Signed-off-by: Anton Johansson
Reviewed-by: Richard Henderson
Message-Id: <20230621135633.1649-2-a...@rev.ng>
Signed-off-by: Richard Henderson
---
include/exec/cpu-
Move to fill a hole in the set of bits.
Reduce the total number of tlb bits by 1.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
include/exec/cpu-all.h | 4 ++--
tcg/tcg-op-ldst.c | 2 +-
2 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/include/exec/
This is a perfectly natural occurrence for x86 "rep movb",
where the "rep" prefix forms a counted loop of the one insn.
During the tests/tcg/multiarch/memory test, this logging is
triggered over 35 times. Within the context of cross-i386-tci
build, which is already slow by nature, the logging
From: Anton Johansson
Signed-off-by: Anton Johansson
Reviewed-by: Richard Henderson
Message-Id: <20230621135633.1649-3-a...@rev.ng>
Signed-off-by: Richard Henderson
---
accel/tcg/internal.h | 6 +++---
accel/tcg/translate-all.c | 10 +-
2 files changed, 8 insertions(+), 8 deleti
The virtio devices require proper memory ordering between
the vcpus and the iothreads.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
tcg/tcg-op.c | 14 +-
1 file changed, 13 insertions(+), 1 deletion(-)
diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c
index c07de
From: Anton Johansson
Signed-off-by: Anton Johansson
Reviewed-by: Richard Henderson
Message-Id: <20230621135633.1649-13-a...@rev.ng>
Signed-off-by: Richard Henderson
---
include/exec/exec-all.h | 2 +-
cpu.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --gi
From: Max Chou
The 5th parameter of tcg_gen_gvec_2s should be replaced by the
temporary tmp variable in the tcg_gen_gvec_andcs function.
Reviewed-by: Daniel Henrique Barboza
Signed-off-by: Max Chou
Message-Id: <20230622161646.32005-9-max.c...@sifive.com>
Signed-off-by: Richard Henderson
---
We have run out of bits we can use within the CPUTLBEntry comparators,
as TLB_FLAGS_MASK cannot overlap alignment.
Store slow_flags[] in CPUTLBEntryFull, and merge with the flags from
the comparator. A new TLB_FORCE_SLOW bit is set within the comparator
as an indication that the slow path must be
From: Anton Johansson
Signed-off-by: Anton Johansson
Reviewed-by: Richard Henderson
Message-Id: <20230621135633.1649-7-a...@rev.ng>
Signed-off-by: Richard Henderson
---
accel/tcg/cpu-exec.c | 34 +-
1 file changed, 17 insertions(+), 17 deletions(-)
diff --git
Bring the helpers into line with the rest of tcg in respecting
guest memory ordering.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
accel/tcg/internal.h | 34 ++
accel/tcg/cputlb.c| 10 ++
accel/tcg/user-exec.c | 10 +++
The microblaze architecture does not reorder instructions.
While there is an MBAR wait-for-data-access instruction,
this concerns synchronizing with DMA.
This should have been defined when enabling MTTCG.
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Edgar E. Iglesias
Fixes: d449561b130 ("co
On 6/26/23 15:39, Alex Bennée wrote:
There were review comments on this series that haven't been applied.
Sorry I'd missed those. I've fixed that for the respin which is
currently checking on CI.
Still not exactly what I asked for; please remove the "The Device Class"
heading (just the headin
From: Anton Johansson
Signed-off-by: Anton Johansson
Reviewed-by: Richard Henderson
Message-Id: <20230621135633.1649-5-a...@rev.ng>
Signed-off-by: Richard Henderson
---
include/exec/cpu_ldst.h | 10 +-
accel/tcg/cputlb.c | 8
2 files changed, 9 insertions(+), 9 deletion
We now issue host memory barriers to match the guest memory order.
Continue to disable MTTCG only if the guest has not been ported.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
accel/tcg/tcg-all.c | 39 ++-
1 file changed, 10 inser
From: Fei Wu
TBStats will be introduced to replace CONFIG_PROFILER totally, here
remove all CONFIG_PROFILER related stuffs first.
Signed-off-by: Vanderson M. do Rosario
Signed-off-by: Alex Bennée
Signed-off-by: Fei Wu
Reviewed-by: Richard Henderson
Message-Id: <20230607122411.3394702-2-fei2.
From: Anton Johansson
Signed-off-by: Anton Johansson
Reviewed-by: Richard Henderson
Message-Id: <20230621135633.1649-4-a...@rev.ng>
Signed-off-by: Richard Henderson
---
target/alpha/cpu.h| 4 ++--
target/arm/cpu.h | 4 ++--
target/avr/cpu.h | 4 ++--
target/cris/cpu.
26.06.2023 15:30, Michael S. Tsirkin wrote:
From: Ani Sinha
When a peer nic is still attached to the vdpa backend, it is too early to free
up the vhost-net and vdpa structures. If these structures are freed here, then
QEMU crashes when the guest is being shut down. The following call chain
woul
We are going to fix bio-tables-test in the next patch and hence need to
make sure the acpi tests continue to pass.
Signed-off-by: Ani Sinha
Acked-by: Igor Mammedov
---
tests/qtest/bios-tables-test-allowed-diff.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/tests/qtest/bios-tables-test-al
Patches 1-4:
Fix tests so that devices do not use non-zero slots on the pcie root
ports. PCIE ports only have one slot, so PCIE devices can only be
plugged into slot 0 on a PCIE port.
Patch 5:
Enforce only one slot on PCIE port.
The test fixes must be applied before the QEMU change that checks fo
From: Peter Maydell
This reverts commit d7ee93e24359703debf4137f4cc632563aa4e8d1.
That commit tries to make a field in the CPUState struct not be
present when CONFIG_USER_ONLY is set. Unfortunately, you can't
conditionally omit fields in structs like this based on ifdefs that
are set per-target
PCIE ports only have one slot, slot 0. Hence, non-zero slots are not available
for PCIE devices on PCIE root ports. Fix test_acpi_q35_tcg_no_acpi_hotplug()
so that the test does not use them.
Signed-off-by: Ani Sinha
Reviewed-by: Igor Mammedov
---
tests/qtest/bios-tables-test.c | 4 ++--
1 file
The test attaches a SCSI controller to a non-zero slot and a pcie-to-pci bridge
on slot 0 on the same pcie-root-port. Since a downstream device can be attached
to a pcie-root-port only on slot 0, the above test configuration is not allowed.
Additionally using pcie.0 as id for pcie-root-port is inco
Some fixes were committed in bios-tables-test in the previous commit. Update
the acpi blob and clear bios-tables-test-allowed-diff.h so that the test
continues to pass with the changes in the bios-tables-test.
Following is the asl diff between the old and the newly updated blob:
@@ -1,30 +1,30 @@
> On 26-Jun-2023, at 7:52 PM, Igor Mammedov wrote:
>
> On Mon, 26 Jun 2023 19:23:23 +0530
> Ani Sinha wrote:
>
>> The test attaches both a SCSI controller and a pcie-to-pci bridge on the same
>> pcie-root-port on slot 0.
> statement is right only for bridge, while it's still incorrect for st
Scratch this … I will resend …
> On 26-Jun-2023, at 9:31 PM, Ani Sinha wrote:
>
> Patches 1-4:
> Fix tests so that devices do not use non-zero slots on the pcie root
> ports. PCIE ports only have one slot, so PCIE devices can only be
> plugged into slot 0 on a PCIE port.
>
> Patch 5:
> Enforce
This is going to be used in the subsequent commit as requests alignment
(in particular, during copy-on-read). This value only makes sense for
the formats which support subclusters (currently QCOW2 only). If this
field isn't set by driver's own bdrv_get_info() implementation, we
simply set it equa
This series makes IO requests performed with copy-on-read to be aligned
to subclusters rather than clusters. It also affects mirror job requests
alignment.
The initial reason for that change is the following crash discovered:
qemu-img create -f qcow2 base.qcow2 64K
qemu-img create -f qcow2 -o
e
When target image is using subclusters, and we align the request during
copy-on-read, it makes sense to align to subcluster_size rather than
cluster_size. Otherwise we end up with unnecessary allocations.
This commit renames bdrv_round_to_clusters() to bdrv_round_to_subclusters()
and utilizes sub
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