AMD supports both 32-bit and 64-bit SYSCALL/SYSRET, but the TCG only
exposes it for 64-bit targets. For system emulation just reuse the
helper; for user-mode emulation the ABI is the same as "int $80".
The BSDs does not support any fast system call mechanism in 32-bit
mode so add to bsd-user the
Suggested-by: Richard Henderson
Signed-off-by: Paolo Bonzini
---
target/i386/tcg/translate.c | 8
1 file changed, 8 insertions(+)
diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c
index 0de068d4b79..4ef45bbd71e 100644
--- a/target/i386/tcg/translate.c
+++ b/target/
Reviewed-by: Richard Henderson
Signed-off-by: Paolo Bonzini
---
target/i386/cpu.c | 4
target/i386/tcg/translate.c | 9 -
2 files changed, 12 insertions(+), 1 deletion(-)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 695e01582bf..978d24b5ec7 100644
--- a/target
XSAVEERPTR is actually a fix for an errata; TCG does not have the issue.
Reviewed-by: Richard Henderson
Signed-off-by: Paolo Bonzini
---
target/i386/cpu.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index fc4246223d4..bce0cb73e85
WBNOINVD is the same as INVD or WBINVD as far as TCG is concerned,
since there is no cache in TCG and therefore no invalidation side effect
in WBNOINVD.
With respect to SVM emulation, processors that do not support WBNOINVD
will ignore the prefix and treat it as WBINVD, while those that support
it
Nicholas Piggin writes:
> From: BALATON Zoltan
>
> All powerpc exception handlers share some code when handling machine
> check exceptions. Move this to a common function.
>
Maybe Machine Check is simple enough, but this kind of sharing of code
has historically caused pain when people want to c
On Thu, 22 Jun 2023 13:41:32 +0200
Thomas Huth wrote:
> It's good style to clean up temporary directories when they
> are not needed anymore.
>
> Signed-off-by: Thomas Huth
Acked-by: Jonathan Cameron
> ---
> tests/qtest/cxl-test.c | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/
On Mon, 7 Nov 2022 at 22:49, Michael S. Tsirkin wrote:
>
> From: Jonathan Cameron
>
> This Data Object Exchange Mailbox allows software to query the
> latency and bandwidth between ports on the switch. For now
> only provide information on routes between the upstream port and
> each downstream po
Enable SVQ with VIRTIO_NET_F_CTRL_RX_EXTRA feature.
Signed-off-by: Hawkins Jiawei
---
net/vhost-vdpa.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/net/vhost-vdpa.c b/net/vhost-vdpa.c
index 9b929762c5..cdfe8e454e 100644
--- a/net/vhost-vdpa.c
+++ b/net/vhost-vdpa.c
@@ -100,6 +100,7 @@ sta
This patch refactors vhost_vdpa_net_load_rx() to
restore the packet receive filtering state in relation to
VIRTIO_NET_F_CTRL_RX_EXTRA feature at device's startup.
Signed-off-by: Hawkins Jiawei
---
net/vhost-vdpa.c | 30 ++
1 file changed, 30 insertions(+)
diff --git
This series enables shadowed CVQ to intercept rx commands related to
VIRTIO_NET_F_CTRL_RX_EXTRA feature through shadowed CVQ, update the virtio
NIC device model so qemu send it in a migration, and the restore of
that rx state in the destination.
To test this patch series, I modify the `n->parent_o
On Thu, 6 Apr 2023 at 17:25, Woodhouse, David wrote:
>
> On Thu, 2023-04-06 at 16:48 +0100, Peter Maydell wrote:
> > On Thu, 2 Mar 2023 at 12:37, Paolo Bonzini wrote:
> > >
> > > From: David Woodhouse
> > >
> > > The way that Xen handles MSI PIRQs is kind of awful.
> >
> > > Now that this is wor
Hello Anushree,
On 6/23/23 13:09, Anushree Mathur wrote:
Hi everyone,
I was trying to boot rhel9.3 image with upstream qemu-system-ppc64 -smp 2
option and observed a segfault (qemu crash).
qemu command line used:
qemu-system-ppc64 -name Rhel9.3.ppc64le -smp 2 -m 16G -vga none -nographic
-ma
On Fri, Jun 23, 2023 at 8:45 AM Michael S. Tsirkin wrote:
> On Wed, May 24, 2023 at 11:13:32AM +0200, Albert Esteve wrote:
> > Add new vhost-user protocol message
> > `VHOST_USER_BACKEND_SHARED_OBJECT`. This new
> > message is sent from vhost-user back-ends
> > to interact with the virtio-dmabuf
On 6/23/23 06:38, Andrew Jones wrote:
On Thu, Jun 22, 2023 at 10:56:53AM -0300, Daniel Henrique Barboza wrote:
...
+#define KVM_MISA_CFG(_bit, _reg_id) \
+{.offset = _bit, .kvm_reg_id = _reg_id}
+
+/* KVM ISA extensions */
+static KVMCPUConfig kvm_misa_ext_cfgs[] = {
+KVM_MISA_CFG(RVA
On 6/23/23 06:58, Andrew Jones wrote:
On Thu, Jun 22, 2023 at 10:56:57AM -0300, Daniel Henrique Barboza wrote:
KVM-specific properties are being created inside target/riscv/kvm.c. But
at this moment we're gathering all the remaining properties from TCG and
adding them as is when running KVM.
From: Lakshmi Bai Raja Subramanian
fdt_load_addr is declared as uint32_t which is not matching with the
return data type of riscv_compute_fdt_addr. Modified fdt_load_addr data type
to uint64_t to match the riscv_compute_fdt_addr() return data type. This fix
also helps in calculating the right fd
On Fri, Jun 23, 2023 at 08:17:46AM +0100, Daniel P. Berrangé wrote:
> On Thu, Jun 22, 2023 at 03:20:01PM -0400, Peter Xu wrote:
> > On Thu, Jun 22, 2023 at 05:33:29PM +0100, Daniel P. Berrangé wrote:
> > > On Thu, Jun 22, 2023 at 11:54:43AM -0400, Peter Xu wrote:
> > > > I can try to move the todo
On Fri, 23 Jun 2023 06:05:28 -0400
"Michael S. Tsirkin" wrote:
> On Wed, Jun 07, 2023 at 03:57:16PM -0500, Suravee Suthikulpanit wrote:
> > Currently, pc-q35 and pc-i44fx machine models are default to use SMBIOS 2.8
> > (32-bit entry point). Since SMBIOS 3.0 (64-bit entry point) is now fully
> >
In the code for TARGET_NR_clock_adjtime, we set the pointer phtx to
the address of the local variable htx. This means it can never be
NULL, but later in the code we check it for NULL anyway. Coverity
complains about this (CID 1507683) because the NULL check comes after
a call to clock_adjtime() t
On Thu, 2 Mar 2023 at 12:50, Paolo Bonzini wrote:
>
> From: David Woodhouse
>
> If I advertise XENFEAT_hvm_pirqs then a guest now boots successfully as
> long as I tell it 'pci=nomsi'.
>
> [root@localhost ~]# cat /proc/interrupts
>CPU0
> 0: 52 IO-APIC 2-edge timer
>
Dear Daniel,
Thanks for your comments. Incorporated the same and updated the patch set as
v3.
https://lists.gnu.org/archive/html/qemu-riscv/2023-06/msg00570.html
Regards,
Lakshmi
-Original Message-
From: Daniel Henrique Barboza
Sent: Friday, June 23, 2023 12:16 AM
To: Lakshmi Bai Ra
On Fri, Jun 23, 2023 at 09:23:18AM +0100, Daniel P. Berrangé wrote:
> On Thu, Jun 22, 2023 at 11:54:43AM -0400, Peter Xu wrote:
> > On Thu, Jun 22, 2023 at 10:59:58AM +0100, Daniel P. Berrangé wrote:
> > > I've mentioned several times before that the user should never need to
> > > set this multifd
On Thu, Jun 22, 2023 at 7:48 PM Michael S. Tsirkin wrote:
>
> On Thu, Jun 22, 2023 at 05:46:40PM +0200, Julia Suvorova wrote:
> > On Thu, Jun 22, 2023 at 12:34 PM Ani Sinha wrote:
> > >
> > > PCI Express ports only have one slot, so PCI Express devices can only be
> > > plugged into slot 0 on a P
On 23/6/23 14:20, Alex Bennée wrote:
This is yet another make target you usually run in the top level of
the source directory.
Signed-off-by: Alex Bennée
---
Makefile | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
Reviewed-by: Philippe Mathieu-Daudé
On Fri, Jun 23, 2023 at 10:51:53AM -0400, Peter Xu wrote:
> On Fri, Jun 23, 2023 at 09:23:18AM +0100, Daniel P. Berrangé wrote:
> > On Thu, Jun 22, 2023 at 11:54:43AM -0400, Peter Xu wrote:
> > > On Thu, Jun 22, 2023 at 10:59:58AM +0100, Daniel P. Berrangé wrote:
> > > > I've mentioned several time
On 23/6/23 14:20, Alex Bennée wrote:
From: Marcin Juszkiewicz
Update prebuilt firmware images to have TF-A with FEAT_FGT support
enabled. This allowed us to enable test for "max" cpu in sbsa-ref
machine.
Signed-off-by: Marcin Juszkiewicz
Message-Id: <20230530152240.79160-1-marcin.juszkiew...@
On 23/6/23 16:44, Peter Maydell wrote:
In the code for TARGET_NR_clock_adjtime, we set the pointer phtx to
the address of the local variable htx. This means it can never be
NULL, but later in the code we check it for NULL anyway. Coverity
complains about this (CID 1507683) because the NULL chec
Peter Maydell writes:
> The xkb official name for the Arabic keyboard layout is 'ara'.
> However xkb has for at least the past 15 years also permitted it to
> be named via the legacy synonym 'ar'. In xkeyboard-config 2.39 this
> synoynm was removed, which breaks compilation of QEMU:
Queued to
Cédric Le Goater writes:
> Hello Anushree,
>
> On 6/23/23 13:09, Anushree Mathur wrote:
>> Hi everyone,
>> I was trying to boot rhel9.3 image with upstream qemu-system-ppc64
>> -smp 2 option and observed a segfault (qemu crash).
>> qemu command line used:
>> qemu-system-ppc64 -name Rhel9.3.ppc6
On 6/23/23 03:26, Michael S. Tsirkin wrote:
On Mon, May 22, 2023 at 11:31:57PM +0700, Bui Quang Minh wrote:
This commit adds XTSup configuration to let user choose to whether enable
this feature or not. When XTSup is enabled, additional bytes in IRTE with
enabled guest virtual VAPIC are used to
On Fri, 23 Jun 2023 at 16:21, Alex Bennée wrote:
>
>
> Peter Maydell writes:
>
> > The xkb official name for the Arabic keyboard layout is 'ara'.
> > However xkb has for at least the past 15 years also permitted it to
> > be named via the legacy synonym 'ar'. In xkeyboard-config 2.39 this
> > sy
On 23/5/23 20:59, David Hildenbrand wrote:
Let's fixup the documentation (e.g., removing traces of the ram_addr
parameter that no longer exists) and move it to the header file while at
it.
Suggested-by: Igor Mammedov
Acked-by: Igor Mammedov
Reviewed-by: Peter Xu
Signed-off-by: David Hildenbra
On 23/6/23 14:21, Nicholas Piggin wrote:
VOF is the new lightweight fast pseries bios. Add a Linux boot test
using VOF.
More tests could be moved to use VOF becasue it's much faster, but
Typo "because".
just dip one toe in the water first here. SLOF should continue to be
tested too.
Signed-
In handle_interrupt() we use level as an index into the interrupt_vector[]
array. This is safe because we have checked it against env->config->nlevel,
but Coverity can't see that (and it is only true because each CPU config
sets its XCHAL_NUM_INTLEVELS to something less than MAX_NLEVELS), so it
com
Richard Henderson writes:
> This is a perfectly natural occurrence for x86 "rep movb",
> where the "rep" prefix forms a counted loop of the one insn.
>
> During the tests/tcg/multiarch/memory test, this logging is
> triggered over 35 times. Within the context of cross-i386-tci
> build, whi
Richard Henderson writes:
> Test for invalid, integer overflow, and inexact.
> Test for proper result, modulo 2**64.
>
> Signed-off-by: Richard Henderson
Acked-by: Alex Bennée
--
Alex Bennée
Virtualisation Tech Lead @ Linaro
Peter Maydell writes:
> On Fri, 23 Jun 2023 at 16:21, Alex Bennée wrote:
>>
>>
>> Peter Maydell writes:
>>
>> > The xkb official name for the Arabic keyboard layout is 'ara'.
>> > However xkb has for at least the past 15 years also permitted it to
>> > be named via the legacy synonym 'ar'. I
On Fri, 23 Jun 2023, Fabiano Rosas wrote:
Nicholas Piggin writes:
From: BALATON Zoltan
All powerpc exception handlers share some code when handling machine
check exceptions. Move this to a common function.
Maybe Machine Check is simple enough, but this kind of sharing of code
has historic
Hi Peter,
On 2/28/23 10:36, Eric Auger wrote:
> Some registers whose 'cooked' writefns induce TLB maintenance do
> not have raw_writefn ops defined. If only the writefn ops is set
> (ie. no raw_writefn is provided), it is assumed the cooked also
> work as the raw one. For those registers it is not
When we generate code for guest loads and stores, at the moment they
end up being requests for a host-endian access. So for target-system-nios2
(little endian) a load like
ldwr3,0(r4)
results on an x86 host in the TCG IR
qemu_ld_a32_i32 r3,loc2,al+leul,0
but on s390 it is
qemu_ld_a
On Sun, Jun 18, 2023 at 08:40:28AM +0800, qianfan wrote:
>
> 在 2023/6/18 0:29, Guenter Roeck 写道:
> > Hi,
> >
> > On Tue, May 23, 2023 at 06:04:58PM +0800, qianfangui...@163.com wrote:
> > > From: qianfan Zhao
> > >
> > > Allwinner R40 (sun8i) SoC features a Quad-Core Cortex-A7 ARM CPU,
> > > an
On Sat, 17 Jun 2023 at 17:29, Guenter Roeck wrote:
>
> Hi,
>
> On Tue, May 23, 2023 at 06:04:58PM +0800, qianfangui...@163.com wrote:
> > From: qianfan Zhao
> >
> > Allwinner R40 (sun8i) SoC features a Quad-Core Cortex-A7 ARM CPU,
> > and a Mali400 MP2 GPU from ARM. It's also known as the Allwinn
On 22.06.2023 20:45, Maciej S. Szmigiero wrote:
On 22.06.2023 14:52, David Hildenbrand wrote:
On 22.06.23 14:14, Maciej S. Szmigiero wrote:
On 22.06.2023 14:06, David Hildenbrand wrote:
On 22.06.23 13:17, Maciej S. Szmigiero wrote:
On 22.06.2023 13:15, David Hildenbrand wrote:
On 22.06.23 13
On 6/21/2023 4:28 PM, Peter Xu wrote:
> On Wed, Jun 21, 2023 at 03:15:42PM -0400, Steven Sistare wrote:
>> On 6/20/2023 5:46 PM, Peter Xu wrote:
>>> On Thu, Jun 15, 2023 at 01:26:39PM -0700, Steve Sistare wrote:
Migration of a guest in the suspended state is broken. The incoming
migratio
SUN Type 4, 5 and 5c keyboards have dip switches to choose the language layout
of the keyboard. Solaris makes an ioctl to query the value of the dipswitches
and uses that value to select keyboard layout. Also the SUN bios like the one
in the file ss5.bin uses this value to support at least some
On 6/23/23 10:44, Peter Maydell wrote:
On Sat, 17 Jun 2023 at 17:29, Guenter Roeck wrote:
Hi,
On Tue, May 23, 2023 at 06:04:58PM +0800, qianfangui...@163.com wrote:
From: qianfan Zhao
Allwinner R40 (sun8i) SoC features a Quad-Core Cortex-A7 ARM CPU,
and a Mali400 MP2 GPU from ARM. It's als
On 6/23/2023 2:25 PM, Steven Sistare wrote:
> On 6/21/2023 4:28 PM, Peter Xu wrote:
>> On Wed, Jun 21, 2023 at 03:15:42PM -0400, Steven Sistare wrote:
>>> On 6/20/2023 5:46 PM, Peter Xu wrote:
On Thu, Jun 15, 2023 at 01:26:39PM -0700, Steve Sistare wrote:
> Migration of a guest in the susp
On Intel CPUs there are certain bits in MSR_ARCH_CAPABILITIES that
indicates if the CPU is not affected by a vulnerability. Without these
bits guests may try to deploy the mitigation even if the CPU is not
affected.
Export the bits to guests that indicate immunity to hardware
vulnerabilities.
Sig
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1725
This fix is implemented by having the vCont handler set the value of
`gdbserver_state.c_cpu` if any threads are to be resumed. The specific CPU
is picked arbitrarily from the ones to be resumed, but it should be okay, as all
GDB cares ab
On 23/6/23 19:25, Peter Maydell wrote:
When we generate code for guest loads and stores, at the moment they
end up being requests for a host-endian access. So for target-system-nios2
(little endian) a load like
ldwr3,0(r4)
results on an x86 host in the TCG IR
qemu_ld_a32_i32 r3,lo
On 2/10/20 13:36, Alex Bennée wrote:
From: Thomas Huth
We do not support Debian 9 in QEMU anymore, and the Debian 9 containers
are now no longer used in the gitlab-CI. Time to remove them.
Signed-off-by: Thomas Huth
Signed-off-by: Alex Bennée
Reviewed-by: Daniel P. Berrangé
Reviewed-by: Phi
HAX is deprecated since commits 73741fda6c ("MAINTAINERS: Abort
HAXM maintenance") and 90c167a1da ("docs/about/deprecated: Mark
HAXM in QEMU as deprecated"), released in v8.0.0.
Per the QEMU deprecation policy, we shouldn't remove it before
QEMU release v8.2.0. However per the latest HAXM release
On 24/6/23 01:08, Philippe Mathieu-Daudé wrote:
HAX is deprecated since commits 73741fda6c ("MAINTAINERS: Abort
HAXM maintenance") and 90c167a1da ("docs/about/deprecated: Mark
HAXM in QEMU as deprecated"), released in v8.0.0.
Per the QEMU deprecation policy, we shouldn't remove it before
QEMU re
On 23/6/23 14:37, Cédric Le Goater wrote:
On 6/23/23 11:10, Peter Maydell wrote:
On Fri, 23 Jun 2023 at 09:21, Nicholas Piggin wrote:
ppc has always silently ignored access to real (physical) addresses
with nothing behind it, which can make debugging difficult at times.
It looks like the way
On Fri, Jun 23, 2023 at 8:41 AM Peter Maydell wrote:
>
> In handle_interrupt() we use level as an index into the interrupt_vector[]
> array. This is safe because we have checked it against env->config->nlevel,
> but Coverity can't see that (and it is only true because each CPU config
> sets its XC
This change:
commit f00506aeca2f6d92318967693f8da8c713c163f3
Merge: d37158bb242 87e303de70f
Author: Peter Maydell
Date: Wed Mar 29 11:19:19 2023 +0100
Merge tag 'pull-tcg-20230328' of https://gitlab.com/rth7680/qemu into
staging
Use a local version of GTree [#285]
Fix page_set_fla
On Fri, May 26, 2023 at 06:00:06PM +0100, Jonathan Cameron wrote:
> v8: Formatting fixes for QMP docs from Markus Armbruster (thanks!)
This and other patches add a bunch of over-80 chars lines. I'm not
going to intervene here as cxl has lots of them but maybe scan over cxl
codebase and shorten wh
22.06.2023 23:33, Michael S. Tsirkin wrote:
On Thu, Jun 08, 2023 at 09:41:58PM +0300, Michael Tokarev wrote:
Applied to my trivial-patches branch (Maybe it's time to resurrect it).
pci things:
Reviewed-by: Michael S. Tsirkin
It's been merged to master on Jun-11 already. But thank you fo
On 23.06.23 07:58, Michael S. Tsirkin wrote:
On Tue, Jun 13, 2023 at 05:02:05PM +0200, David Hildenbrand wrote:
One limitation of virtio-mem is that we cannot currently unplug virtio-mem
devices that have all memory unplugged from the VM.
Let's properly handle forced unplug (as can be triggered
On Fri, Jun 23, 2023 at 09:04:37AM +0200, David Hildenbrand wrote:
> On 23.06.23 07:58, Michael S. Tsirkin wrote:
> > On Tue, Jun 13, 2023 at 05:02:05PM +0200, David Hildenbrand wrote:
> > > One limitation of virtio-mem is that we cannot currently unplug virtio-mem
> > > devices that have all memor
On Thu, Jun 22, 2023 at 03:20:01PM -0400, Peter Xu wrote:
> On Thu, Jun 22, 2023 at 05:33:29PM +0100, Daniel P. Berrangé wrote:
> > On Thu, Jun 22, 2023 at 11:54:43AM -0400, Peter Xu wrote:
> > > I can try to move the todo even higher. Trying to list the initial goals
> > > here:
> > >
> > > - On
On Fri, Jun 23, 2023 at 8:45 AM Michael S. Tsirkin wrote:
> On Wed, May 24, 2023 at 11:13:32AM +0200, Albert Esteve wrote:
> > Add new vhost-user protocol message
> > `VHOST_USER_BACKEND_SHARED_OBJECT`. This new
> > message is sent from vhost-user back-ends
> > to interact with the virtio-dmabuf
Currently on PPC64 qemu always dumps the guest memory in
Big Endian (BE) format even though the guest running in Little Endian
(LE) mode. So crash tool fails to load the dump as illustrated below:
Log :
$ virsh dump DOMAIN --memory-only dump.file
Domain 'DOMAIN' dumped to dump.file
$ crash vmlin
On 5/23/23 15:45, Greg Kurz wrote:
On Tue, 23 May 2023 12:20:17 +0530
Narayana Murty N wrote:
On 5/22/23 23:50, Greg Kurz wrote:
On Mon, 22 May 2023 12:02:42 -0400
Narayana Murty N wrote:
Currently on PPC64 qemu always dumps the guest memory in
Big Endian (BE) format even though the gues
On Fri, Jun 23, 2023 at 09:19:29AM +0200, Albert Esteve wrote:
>
>
> On Fri, Jun 23, 2023 at 8:45 AM Michael S. Tsirkin wrote:
>
> On Wed, May 24, 2023 at 11:13:32AM +0200, Albert Esteve wrote:
> > Add new vhost-user protocol message
> > `VHOST_USER_BACKEND_SHARED_OBJECT`. This new
On 6/22/23 18:16, Max Chou wrote:
--- a/target/riscv/vcrypto_helper.c
+++ b/target/riscv/vcrypto_helper.c
@@ -22,6 +22,7 @@
#include "qemu/bitops.h"
#include "qemu/bswap.h"
#include "cpu.h"
+#include "crypto/aes.h"
#include "exec/memop.h"
#include "exec/exec-all.h"
#include "exec/help
Richard Henderson wrote:
> On 6/22/23 18:54, Juan Quintela wrote:
>> The following changes since commit b455ce4c2f300c8ba47cba7232dd03261368a4cb:
>>Merge tag 'q800-for-8.1-pull-request'
>> ofhttps://github.com/vivier/qemu-m68k into staging (2023-06-22
>> 10:18:32 +0200)
>> are available in th
On Thu, Jun 22, 2023 at 10:19 PM Marc-André Lureau <
marcandre.lur...@gmail.com> wrote:
> Hi
>
> On Wed, May 24, 2023 at 11:13 AM Albert Esteve wrote:
>
>> Add new vhost-user protocol message
>> `VHOST_USER_BACKEND_SHARED_OBJECT`. This new
>> message is sent from vhost-user back-ends
>> to intera
On Wed, May 24, 2023 at 11:13:32AM +0200, Albert Esteve wrote:
> Add new vhost-user protocol message
> `VHOST_USER_BACKEND_SHARED_OBJECT`. This new
> message is sent from vhost-user back-ends
> to interact with the virtio-dmabuf table
> in order to add, remove, or lookup for
> virtio dma-buf shared
ppc currently silently accepts invalid real address access. Catch
these and turn them into machine checks. POWER9/10 machine check
codes for invalid real address access are implemented.
Signed-off-by: Nicholas Piggin
---
target/ppc/cpu_init.c| 1 +
target/ppc/excp_helper.c | 35
checkstop state does not halt the system, interrupts continue to be
serviced, and other CPUs run.
Stop the machine with vm_stop(), and print a register dump too.
Signed-off-by: Nicholas Piggin
---
target/ppc/excp_helper.c | 35 +--
1 file changed, 21 insertions(+
ppc has always silently ignored access to real (physical) addresses
with nothing behind it, which can make debugging difficult at times.
It looks like the way to handle this is implement the transaction
failed call, which most target architectures do. Notably not x86
though, I wonder why?
Other q
From: BALATON Zoltan
All powerpc exception handlers share some code when handling machine
check exceptions. Move this to a common function.
Reviewed-by: Nicholas Piggin
Signed-off-by: BALATON Zoltan
[np: tweak subject, rename function to powerpc_mcheck_test_and_checkstop]
Signed-off-by-by: Nic
Implement the correct register settings for the invalid-real access
machine check for POWER9/10 processors.
Signed-off-by: Nicholas Piggin
---
target/ppc/excp_helper.c | 26 --
1 file changed, 24 insertions(+), 2 deletions(-)
diff --git a/target/ppc/excp_helper.c b/targ
On Thu, Jun 22, 2023 at 11:54:43AM -0400, Peter Xu wrote:
> On Thu, Jun 22, 2023 at 10:59:58AM +0100, Daniel P. Berrangé wrote:
> > I've mentioned several times before that the user should never need to
> > set this multifd-channels parameter (nor many other parameters) on the
> > destination in th
On Fri, 23 Jun 2023 at 09:21, Nicholas Piggin wrote:
>
> ppc has always silently ignored access to real (physical) addresses
> with nothing behind it, which can make debugging difficult at times.
>
> It looks like the way to handle this is implement the transaction
> failed call, which most target
On 5/31/23 03:23, Nicholas Piggin wrote:
Make sure each CPU gets its state set up for gdb, not just the ones
before PowerPCCPUClass has had its gdb state set up.
Signed-off-by: Nicholas Piggin
Applied to ppc-next.
Thanks,
C.
---
target/ppc/gdbstub.c | 30 +++---
On 6/20/23 01:36, Joel Stanley wrote:
The phb error macros add a newline for you, so remove the second one to
avoid double whitespace.
Signed-off-by: Joel Stanley
Applied to ppc-next.
Thanks,
C.
---
hw/pci-host/pnv_phb4.c | 14 +++---
1 file changed, 7 insertions(+), 7 delet
On 6/20/23 07:59, Cédric Le Goater wrote:
Hello,
Please welcome new reviewers on baremetal POWER systems !
Follow cleanups to report an error when KVM is used on non-KVM
machines.
Thanks,
C.
Cédric Le Goater (9):
MAINTAINERS: Add reviewers for PowerNV baremetal emulation
MAINTAINERS: A
On 6/20/23 12:57, Nicholas Piggin wrote:
To prepare for some later changes to nested-HV I would like to get
these cleanups done and move nested to its own file. This is
rebased and patch 4 has some nested function definitions and
structs in spapr_nested.h that Harsh suggested.
Thanks,
Nick
Nich
On Thu, Jun 22, 2023 at 10:56:52AM -0300, Daniel Henrique Barboza wrote:
> Next patch will add KVM specific user properties for both MISA and
> multi-letter extensions. For MISA extensions we want to make use of what
> is already available in misa_ext_cfgs[] to avoid code repetition.
>
> misa_ext_
On 6/20/23 15:10, Nicholas Piggin wrote:
Because they got more complexities than I first thought, these patches
are broken out from the bigger series here:
https://lists.gnu.org/archive/html/qemu-ppc/2023-05/msg00425.html
Since then I fixed the --disable-tcg compile bug reported by Anushree
hop
On 6/20/23 15:13, Nicholas Piggin wrote:
System call interrupts in ISA v3.1 CPUs add a LEV indication in SRR1
that corresponds with the LEV field of the instruction that caused the
interrupt.
Signed-off-by: Nicholas Piggin
Applied to ppc-next.
Thanks,
C.
---
This is unchanged, just tak
On 6/20/23 15:15, Nicholas Piggin wrote:
The CTRL register is able to write the bit in the RUN field, which gets
reflected into the TS field which is read-only and contains the state of
the RUN field for all threads in the core.
TCG does not implement SMT, so the correct implementation just requ
On 6/21/23 13:09, Nicholas Piggin wrote:
The top bits of the LEV field of the sc instruction are to be treated as
as a reserved field rather than a reserved value, meaning LEV is
effectively the bottom bit. LEV=0xF should be treated as LEV=1 and be
a hypercall, for example.
This changes the inst
On 6/22/23 11:33, Nicholas Piggin wrote:
This series is based on some previously posted TCG fixes, in particular
the CTRL register fix is required.
Also added the Philippe's patch in the series to prevent conflict.
Since v1, main changes are just some tidying of comments and changelogs,
and add
On 6/22/23 18:25, Frederic Barrat wrote:
Fix the TIMA special ops detection regression, as spotted by Coverity.
Tested by running a pseries guest on top of a powernv9 and powernv10 host.
Changelog:
v2: define get_config for spapr
Frederic Barrat (2):
pnv/xive2: Add a get_config() method on
On Thu, Jun 22, 2023 at 10:56:53AM -0300, Daniel Henrique Barboza wrote:
...
> +#define KVM_MISA_CFG(_bit, _reg_id) \
> +{.offset = _bit, .kvm_reg_id = _reg_id}
> +
> +/* KVM ISA extensions */
> +static KVMCPUConfig kvm_misa_ext_cfgs[] = {
> +KVM_MISA_CFG(RVA, KVM_RISCV_ISA_EXT_A),
> +K
The keyboard mapping name 'ar' was a legacy name only available from
xkeyboard-config via a (15 year old) backcompat mapping. This mapping
was finally removed in the latest upstream release 2.39:
https://gitlab.freedesktop.org/xkeyboard-config/xkeyboard-config/-/commit/470ad2cd8fea84d7210377161
On Thu, Jun 22, 2023 at 10:56:56AM -0300, Daniel Henrique Barboza wrote:
> riscv_isa_string_ext() is being used by riscv_isa_string(), which is
> then used by boards to retrieve the 'riscv,isa' string to be written in
> the FDT. All this happens after riscv_cpu_realize(), meaning that we're
> alrea
Hi Michael,
On Fri, Jun 23, 2023 at 09:54:54AM +0300, Michael Tokarev wrote:
> 22.06.2023 17:51, Bastian Koppelmann wrote:
> ..
> > > Is it a -stable material?
> >
> > Yes. If you pick this up, make sure you also pick up
> > https://lore.kernel.org/qemu-devel/20230621161422.1652151-1-kbast...@ma
On Thu, Jun 22, 2023 at 10:56:57AM -0300, Daniel Henrique Barboza wrote:
> KVM-specific properties are being created inside target/riscv/kvm.c. But
> at this moment we're gathering all the remaining properties from TCG and
> adding them as is when running KVM. This creates a situation where
> non-K
On Wed, Jun 07, 2023 at 03:57:16PM -0500, Suravee Suthikulpanit wrote:
> Currently, pc-q35 and pc-i44fx machine models are default to use SMBIOS 2.8
> (32-bit entry point). Since SMBIOS 3.0 (64-bit entry point) is now fully
> supported since QEMU 7.0, default to use SMBIOS 3.0 for newer machine
> m
On Fri, 23 Jun 2023 at 10:40, Daniel P. Berrangé wrote:
>
> The keyboard mapping name 'ar' was a legacy name only available from
> xkeyboard-config via a (15 year old) backcompat mapping. This mapping
> was finally removed in the latest upstream release 2.39:
>
>
> https://gitlab.freedesktop.or
On Thu, 22 Jun 2023 at 15:30, Richard Henderson
wrote:
>
> Signed-off-by: Richard Henderson
> ---
> docs/system/arm/cpu-features.rst | 23 +++
> docs/system/arm/emulation.rst| 1 +
> 2 files changed, 24 insertions(+)
>
> diff --git a/docs/system/arm/cpu-features.rst
> b
On Mon, 19 Jun 2023 at 15:02, Richard Henderson
wrote:
>
> One cannot test for feature aa32_simd_r32 without first
> testing if AArch32 mode is supported at all. This leads to
>
> qemu-system-aarch64: ARM CPUs must have both VFP-D32 and Neon or neither
>
> for Apple M1 cpus.
>
> We already have a
On Fri, Jun 23, 2023 at 11:12:13AM +0100, Peter Maydell wrote:
> On Fri, 23 Jun 2023 at 10:40, Daniel P. Berrangé wrote:
> >
> > The keyboard mapping name 'ar' was a legacy name only available from
> > xkeyboard-config via a (15 year old) backcompat mapping. This mapping
> > was finally removed in
On Tue, Jun 20, 2023 at 05:20:24PM +0100, Peter Maydell wrote:
> The xkb official name for the Arabic keyboard layout is 'ara'.
> However xkb has for at least the past 15 years also permitted it to
> be named via the legacy synonym 'ar'. In xkeyboard-config 2.39 this
> synoynm was removed, which b
23.06.2023 12:51, Bastian Koppelmann wrote:
Is there anything else in this series worth picking up for stable, eg:
Fix helper_ret() not correctly restoring PSW
Fix RR_JLI clobbering reg A[11]
These are rare cases where the guest does something wrong. It will not lead to a
crash of QEMU.
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