>-Original Message-
>From: Peter Xu
>Sent: Thursday, June 8, 2023 11:41 PM
>To: Jason Gunthorpe ; Liu, Yi L ; Duan,
>Zhenzhong
>Cc: Duan, Zhenzhong ; qemu-
>de...@nongnu.org; m...@redhat.com; jasow...@redhat.com;
>pbonz...@redhat.com; richard.hender...@linaro.org; edua...@habkost.net;
>
On Wed, 07 Jun 2023 19:47, Yeqi Fu wrote:
+have_user_native_call = get_option('user_native_call') \
+.require(have_user, error_message: 'user_native_call requires user') \
+.require(targetos == 'linux', error_message: 'user_native_call requires
Linux') \
+.allowed()
Is there a ch
On Wed, 07 Jun 2023 19:47, Yeqi Fu wrote:
--- a/linux-user/main.c
+++ b/linux-user/main.c
+/* Set the library for native bypass */
+if (native_lib != NULL) {
+char *token = malloc(strlen(native_lib) + 12);
malloc() can fail (in rare circumstances). Check for the return value
>-Original Message-
>From: Peter Xu
>Sent: Friday, June 9, 2023 3:53 AM
>To: Jason Gunthorpe
>Cc: Liu, Yi L ; Duan, Zhenzhong
>; qemu-devel@nongnu.org; m...@redhat.com;
>jasow...@redhat.com; pbonz...@redhat.com;
>richard.hender...@linaro.org; edua...@habkost.net;
>marcel.apfelb...@gmail
According to the `The RISC-V Advanced Interrupt Architecture`
document, if register `mmsiaddrcfgh` of the domain has bit L set
to one, then `smsiaddrcfg` and `smsiaddrcfgh` are locked as
read-only alongside `mmsiaddrcfg` and `mmsiaddrcfgh`.
Signed-off-by: Tommy Wu
Reviewed-by: Frank Chang
---
h
On Thu, Jun 08, 2023 at 01:49:27PM -0700, Mike Kravetz wrote:
> This effectively reverts commit 16c243e99d33 ("udmabuf: Add support
> for mapping hugepages (v4)"). Recently, Junxiao Chang found a BUG
> with page map counting as described here [1]. This issue pointed out
> that the udmabuf driver
Hi all,
Modifications on kernel end is:
https://lore.kernel.org/lkml/20230608063857.1677973-2-jiqian.c...@amd.com/T/#u
On 2023/6/8 10:56, Jiqian Chen wrote:
> Hi all,
>
> I am working to implement virtgpu S3 function on Xen.
>
> Currently on Xen, if we start a guest who enables virtgpu, and th
On 6/7/2023 9:51 PM, Eugenio Perez Martin wrote:
On Wed, Jun 7, 2023 at 11:09 AM Zhu Lingshan wrote:
When read the state of a virtqueue, vhost_vdpa need
to check whether the device is suspended.
This commit verifies whether VHOST_BACKEND_F_SUSPEND is
negotiated when checking vhost_vdpa->sus
Hi Daniel,
Thanks for all the suggestions ! I'll send patch v4 and fix all the issues.
On Thu, May 25, 2023 at 8:29 PM Daniel Henrique Barboza <
dbarb...@ventanamicro.com> wrote:
>
>
> On 5/22/23 10:11, Tommy Wu wrote:
> > Signed-off-by: Frank Chang
> > Signed-off-by: Tommy Wu
> > ---
> > hw
This patchset added support for Smrnmi Extension in RISC-V.
There are four new CSRs and one new instruction added to allow NMI to be
resumable in RISC-V, which are:
=
* mnscratch (0x740)
* mnepc (0x741)
* mncause (0x742)
*
Signed-off-by: Frank Chang
Signed-off-by: Tommy Wu
---
target/riscv/helper.h | 1 +
target/riscv/insn32.decode| 3 ++
.../riscv/insn_trans/trans_privileged.c.inc | 12 +
target/riscv/op_helper.c | 49 +++
4
Signed-off-by: Frank Chang
Signed-off-by: Tommy Wu
---
hw/riscv/riscv_hart.c | 21 +
include/hw/riscv/riscv_hart.h | 4
target/riscv/cpu.c| 13 +
target/riscv/cpu.h| 7 +++
target/riscv/cpu_bits.h | 12
Signed-off-by: Frank Chang
Signed-off-by: Tommy Wu
---
target/riscv/cpu.c | 5 +++
target/riscv/cpu.h | 4 ++
target/riscv/cpu_bits.h | 11 ++
target/riscv/csr.c | 82 +
4 files changed, 102 insertions(+)
diff --git a/target/riscv/cpu
Signed-off-by: Frank Chang
Signed-off-by: Tommy Wu
---
target/riscv/cpu_helper.c | 57 +++
1 file changed, 52 insertions(+), 5 deletions(-)
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index da477b6c99..1a926bb661 100644
--- a/target/ris
On 6/7/23 00:02, BALATON Zoltan wrote:
Count exceptions which can be queried with info irq monitor command.
I don't think the TYPE_INTERRUPT_STATS_PROVIDER interface was designed
for CPUs. It is more suitable for interrupt controllers.
C.
Signed-off-by: BALATON Zoltan
---
target/ppc/cpu.
On 6/7/2023 8:49 PM, Wu, Fei wrote:
> On 6/1/2023 10:40 AM, Richard Henderson wrote:
>>> +static int
>>> +__attribute__((format(printf, 2, 3)))
>>> +fprintf_log(FILE *a, const char *b, ...)
>>> +{
>>> + va_list ap;
>>> + va_start(ap, b);
>>> +
>>> + if (!to_string) {
>>> + vfprintf(
On Wed, Jun 07, 2023 at 03:57:17PM -0500, Suravee Suthikulpanit wrote:
> Since KVM_MAX_VCPUS is currently defined to 1024 for x86 as shown in
> arch/x86/include/asm/kvm_host.h, update QEMU limits to the same number.
>
> In case KVM could not support the specified number of vcpus, QEMU would
> retu
On Wed, Jun 07, 2023 at 03:57:16PM -0500, Suravee Suthikulpanit wrote:
> Currently, pc-q35 and pc-i44fx machine models are default to use SMBIOS 2.8
> (32-bit entry point). Since SMBIOS 3.0 (64-bit entry point) is now fully
> supported since QEMU 7.0, default to use SMBIOS 3.0 for newer machine
> m
This patch adds the new syscall for the
"RISC-V Hardware Probing Interface"
(https://docs.kernel.org/riscv/hwprobe.html).
Signed-off-by: Robbin Ehn
---
v1->v2: Moved to syscall.c
v2->v3: Separate function, get/put user
---
linux-user/riscv/syscall32_nr.h | 1 +
linux-user/riscv/syscall64_nr.h
On Thu, 8 Jun 2023 10:51:05 +0800
Zhao Liu wrote:
> On Wed, Jun 07, 2023 at 04:49:34PM +0200, Igor Mammedov wrote:
> > Date: Wed, 7 Jun 2023 16:49:34 +0200
> > From: Igor Mammedov
> > Subject: Re: [PATCH v2 2/3] hw/smbios: Fix thread count in type4
> > X-Mailer: Claws Mail 4.1.1 (GTK 3.24.38; x8
On Wed, 7 Jun 2023 22:01:25 +0200 (CEST)
BALATON Zoltan wrote:
> On pegasos2 which has ACPI as part of VT8231 south bridge the board
> firmware writes PM control register by accessing the second byte so
> addr will be 1. This wasn't handled correctly and the write went to
> addr 0 instead. Remov
On Wed, 7 Jun 2023 15:57:16 -0500
Suravee Suthikulpanit wrote:
> Currently, pc-q35 and pc-i44fx machine models are default to use SMBIOS 2.8
> (32-bit entry point). Since SMBIOS 3.0 (64-bit entry point) is now fully
> supported since QEMU 7.0, default to use SMBIOS 3.0 for newer machine
> models.
On Thu, Jun 8, 2023 at 9:07 AM Zhu, Lingshan wrote:
>
>
>
> On 6/7/2023 9:51 PM, Eugenio Perez Martin wrote:
> > On Wed, Jun 7, 2023 at 11:09 AM Zhu Lingshan wrote:
> >> When read the state of a virtqueue, vhost_vdpa need
> >> to check whether the device is suspended.
> >>
> >> This commit verifi
Fix missing env->ca restore when going from L2 back to the host.
Fixes: 120f738a467 ("spapr: implement nested-hv capability for the virtual
hypervisor")
Reviewed-by: Harsh Prateek Bora
Signed-off-by: Nicholas Piggin
---
hw/ppc/spapr_hcall.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/h
To prepare for some later changes to nested-HV I would like to get
these cleanups done and move nested to its own file. These were
posted earlier, not much changed except rebased on the CR helper
accessor functions.
Thanks,
Nick
Nicholas Piggin (4):
ppc/spapr: H_ENTER_NESTED should restore host
Create spapr_nested.c for most of the nested HV implementation.
Signed-off-by: Nicholas Piggin
---
hw/ppc/meson.build | 1 +
hw/ppc/spapr_hcall.c | 415 +-
hw/ppc/spapr_nested.c | 496 +
include/hw/ppc/spapr.h | 61
Arguably this is just shuffling around register accesses, but one nice
thing it does is allow the exit to save away the L2 state then switch
the environment to the L1 before copying L2 data back to the L1, which
logically flows more naturally and simplifies the error paths.
Signed-off-by: Nicholas
Rather than use a copy of CPUPPCState to store the host state while
the environment has been switched to the L2, use a new struct for
this purpose.
Have helper functions to save and load this host state.
Signed-off-by: Nicholas Piggin
---
hw/ppc/spapr_hcall.c| 150 ++
On Thu, 8 Jun 2023 at 08:44, Wu, Fei wrote:
>
> On 6/7/2023 8:49 PM, Wu, Fei wrote:
> > On 6/1/2023 10:40 AM, Richard Henderson wrote:
> >> Did you really need something different than monitor_disas? You almost
> >> certainly want to read physical memory and not virtual anyway.
> >>
> > Yes, it's
On 6/8/2023 4:49 PM, Eugenio Perez Martin wrote:
On Thu, Jun 8, 2023 at 9:07 AM Zhu, Lingshan wrote:
On 6/7/2023 9:51 PM, Eugenio Perez Martin wrote:
On Wed, Jun 7, 2023 at 11:09 AM Zhu Lingshan wrote:
When read the state of a virtqueue, vhost_vdpa need
to check whether the device is su
On Thu, 8 Jun 2023, Cédric Le Goater wrote:
On 6/7/23 00:02, BALATON Zoltan wrote:
Count exceptions which can be queried with info irq monitor command.
I don't think the TYPE_INTERRUPT_STATS_PROVIDER interface was designed
for CPUs. It is more suitable for interrupt controllers.
True but:
-
On Tue, 30 May 2023 at 22:23, Vikram Garhwal wrote:
>
> The QTests perform three tests on the Xilinx VERSAL CANFD controller:
> Tests the CANFD controllers in loopback.
> Tests the CANFD controllers in normal mode with CAN frame.
> Tests the CANFD controllers in normal mode with CANFD
On Thu, Jun 08, 2023 at 12:23:10AM -0700, Tommy Wu wrote:
> This patchset added support for Smrnmi Extension in RISC-V.
>
> There are four new CSRs and one new instruction added to allow NMI to be
> resumable in RISC-V, which are:
>
> =
On Wed, 7 Jun 2023 18:52:14 +
Shesha Bhushan Sreenivasamurthy wrote:
> From: Fan Ni
> Sent: Wednesday, June 7, 2023 11:31 AM
> To: Shesha Bhushan Sreenivasamurthy
> Cc: Jonathan Cameron ; qemu-devel@nongnu.org
> ; linux-...@vger.kernel.org
> ; gregory.pr...@memverge.com
> ; hch...@avery-
Please add a commit message to all patches of the series.
Another comment below.
On Thu, Jun 08, 2023 at 12:23:11AM -0700, Tommy Wu wrote:
> Signed-off-by: Frank Chang
> Signed-off-by: Tommy Wu
> ---
> hw/riscv/riscv_hart.c | 21 +
> include/hw/riscv/riscv_hart.h
On Mon, 5 Jun 2023 at 16:48, Hanna Czenczek wrote:
>
> When processing vectored guest requests that are not aligned to the
> storage request alignment, we pad them by adding head and/or tail
> buffers for a read-modify-write cycle.
Hi; Coverity complains (CID 1512819) that the assert added
in thi
This function is a variant of iova_tree_foreach and support tranversing
a range to trigger callback with a private data.
Reviewed-by: Peter Xu
Signed-off-by: Zhenzhong Duan
---
include/qemu/iova-tree.h | 17 +++--
util/iova-tree.c | 31 +++
2 file
Commit 63b88968f1 ("intel-iommu: rework the page walk logic") adds logic
to record mapped IOVA ranges so we only need to send MAP or UNMAP when
necessary. But there is still a corner case of unnecessary UNMAP.
During invalidation, either domain or device selective, we only need to
unmap when there
Hi All,
This patchset includes some fixes on VFIO dirty sync and vIOMMU.
PATCH1 isn't needed now as dependent changes in PATCH2 is removed,
but as Peter has given Reviewed-by, leave it to maintainer to
decide if pick or not.
Tested net card passthrough, ping/ssh pass
Tested DSA vdev passthrough,
Peter Xu found a potential issue:
"The other thing is when I am looking at the new code I found that we
actually extended the replay() to be used also in dirty tracking of vfio,
in vfio_sync_dirty_bitmap(). For that maybe it's already broken if
unmap_all() because afaiu log_sync() can be called i
During address space unmap, corresponding IOVA tree entries are
also removed. But DMAMap is set beyond notifier's scope by 1, so
in theory there is possibility to remove a continuous entry above
the notifier's scope but falling in adjacent notifier's scope.
There is no issue currently as no use ca
Replay doesn't notify registered notifiers but the one passed
to it. So it's meaningless to check the registered notifier's
synthetic flag.
There is no issue currently as all replay use cases have MAP
flag set, but let's be robust.
Signed-off-by: Zhenzhong Duan
---
hw/i386/intel_iommu.c | 2 +-
On Wed, 7 Jun 2023 at 09:56, Antonio Caggiano wrote:
>
> On MacOS 11 and subsequent versions, in case the resulting binary is not
> signed with the proper entitlement, handle and report the HV_DENIED
> error.
>
> Signed-off-by: Antonio Caggiano
> ---
> v2: Use architecture specific defines from A
On Wed, 7 Jun 2023 at 05:40, Cédric Le Goater wrote:
>
> Cortex A7 CPUs with an FPU implementing VFPv4 without NEON support
> have 16 64-bit FPU registers and not 32 registers. Let users set the
> number of VFP registers with a CPU property.
>
> The primary use case of this property is for the Cor
On Wed, 7 Jun 2023 23:01:11 +
Shesha Bhushan Sreenivasamurthy wrote:
> Hi,
> For DCD sideband there needs to be LD-ID. Is the following approach
> acceptable?
QEMU question so +CC qemu-devel
>
> -device
> cxl-type3,bus=swport0,volatile-memdev=vmem0,dc-memdev=vmem1,id=cxl-vmem0,num-dc-re
Shesha,
You've sent an email with the 'In-reply-to' set to one of Terry's patches.
Please check why that happened and make sure you don't do that in future as
it hides your unrelated thread in email clients and the archives!
See
https://lore.kernel.org/linux-cxl/20230607221651.2454764-1-terry.b
On Thu, Jun 8, 2023 at 11:34 AM Zhu, Lingshan wrote:
>
>
>
> On 6/8/2023 4:49 PM, Eugenio Perez Martin wrote:
> > On Thu, Jun 8, 2023 at 9:07 AM Zhu, Lingshan wrote:
> >>
> >>
> >> On 6/7/2023 9:51 PM, Eugenio Perez Martin wrote:
> >>> On Wed, Jun 7, 2023 at 11:09 AM Zhu Lingshan
> >>> wrote:
>
Hi Marc-André,
On 07/06/2023 12:21, Marc-André Lureau wrote:
Hi Antonio
On Wed, Jun 7, 2023 at 1:05 PM Antonio Caggiano
wrote:
Add the SDL_WINDOW_ALLOW_HIGHDPI flag when creating a window and get the
drawable size instead of the window size when setting up the framebuffer
and the viewport.
On 07/06/2023 21:01, BALATON Zoltan wrote:
On pegasos2 which has ACPI as part of VT8231 south bridge the board
firmware writes PM control register by accessing the second byte so
addr will be 1. This wasn't handled correctly and the write went to
addr 0 instead. Remove the acpi_pm1_cnt_write() f
On Fri, May 26, 2023 at 09:04:34AM -0700, Richard Henderson wrote:
> On 5/26/23 03:19, Daniel P. Berrangé wrote:
> > +# Upstream pipeline jobs start automatically unless told not to
> > +# by setting QEMU_CI=1
> > +- if: '$QEMU_CI == "1" && $CI_PROJECT_NAMESPACE == $QEMU_CI_UPSTREAM
>
On 06/06/23 3:45 pm, Het Gala wrote:
MigrateChannelList allows to connect accross multiple interfaces. Added
MigrateChannelList struct as argument to migration QAPIs.
Future patchset series plans to include multiple MigrateChannels
for multiple interfaces to be connected. That is the reason,
'
* Peter Maydell (peter.mayd...@linaro.org) wrote:
> On Thu, 8 Jun 2023 at 08:44, Wu, Fei wrote:
> >
> > On 6/7/2023 8:49 PM, Wu, Fei wrote:
> > > On 6/1/2023 10:40 AM, Richard Henderson wrote:
> > >> Did you really need something different than monitor_disas? You almost
> > >> certainly want to r
On Thu, 8 Jun 2023 at 13:06, Dr. David Alan Gilbert wrote:
>
> * Peter Maydell (peter.mayd...@linaro.org) wrote:
> > On Thu, 8 Jun 2023 at 08:44, Wu, Fei wrote:
> > >
> > > On 6/7/2023 8:49 PM, Wu, Fei wrote:
> > > > On 6/1/2023 10:40 AM, Richard Henderson wrote:
> > > >> Did you really need some
Queued, thanks.
Paolo
On MacOS 11 and subsequent versions, in case the resulting binary is not
signed with the proper entitlement, handle and report the HV_DENIED
error.
Signed-off-by: Antonio Caggiano
---
v2: Use architecture specific defines from AvailabilityMacros.h to enable the
HV_DENIED case only on MacOS 11
From: Mads Ynddal
The arguments extracted from `sys.argv` named and unpacked to make it
clear what the arguments are and what they're used for.
The two input files were opened, but never explicitly closed. File usage
changed to use `with` statement to take care of this. At the same time,
ownersh
From: Mads Ynddal
I wanted to use simpletrace.py for an internal project, so I tried to update
and polish the code. Some of the commits resolve specific issues, while some
are more subjective.
I've tried to divide it into commits so we can discuss the
individual changes, and I'm ready to pull th
From: Mads Ynddal
In my work to refactor simpletrace.py, I noticed that there's no
maintainer of it, and has the status of "odd fixes". I'm using it from
time to time, so I'd like to maintain the script.
I've added myself as reviewer under "Tracing" to be informed of changes
that might affect si
From: Mads Ynddal
Moved event_mapping and event_id_to_name down one level in the function
call-stack to keep variable instantiation and usage closer (`process`
and `run` has no use of the variables; `read_trace_records` does).
Instead of passing event_mapping and event_id_to_name to the bottom o
From: Mads Ynddal
It was unclear what was the supported public interface. I.e. when
refactoring the code, what functions/classes are important to retain.
Signed-off-by: Mads Ynddal
---
scripts/simpletrace.py | 2 ++
1 file changed, 2 insertions(+)
diff --git a/scripts/simpletrace.py b/scripts
From: Mads Ynddal
It wasn't clear where the constants and structs came from, so I added
comments to help.
Signed-off-by: Mads Ynddal
---
scripts/simpletrace.py | 5 +
1 file changed, 5 insertions(+)
diff --git a/scripts/simpletrace.py b/scripts/simpletrace.py
index b221d9a241..5c230a1b74
From: Mads Ynddal
Readability is subjective, but I've expanded the naming of the variables
and arguments, to help with understanding for new eyes on the code.
Signed-off-by: Mads Ynddal
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Stefan Hajnoczi
---
scripts/simpletrace.py | 34 +
From: Mads Ynddal
To avoid duplicate code depending on input types and to better handle
open/close of log with a context-manager, we move the logic of process into
_process.
Signed-off-by: Mads Ynddal
---
scripts/simpletrace.py | 26 ++
1 file changed, 18 insertions(+),
From: Mads Ynddal
A failed call to `read_header` wouldn't be handled the same for the two
different code paths (one path would try to use `None` as a list).
Changed to raise exception to be handled centrally. This also allows for
easier unpacking, as errors has been filtered out.
Signed-off-by:
From: Mads Ynddal
Python 3 removed `dict.iteritems()` in favor of `dict.items()`. This
means the script curerntly doesn't work on Python 3.
Signed-off-by: Mads Ynddal
---
scripts/analyse-locks-simpletrace.py | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/scripts/analyse-lo
From: Mads Ynddal
Instead of explicitly calling `begin` and `end`, we can change the class
to use the context-manager paradigm. This is mostly a styling choice,
used in modern Python code. But it also allows for more advanced analyzers
to handle exceptions gracefully in the `__exit__` method (not
From: Mads Ynddal
The call to `getargspec` was deprecated and in Python 3.11 it has been
removed in favor of `getfullargspec`. `getfullargspec` is compatible
with QEMU's requirement of at least Python version 3.6.
Signed-off-by: Mads Ynddal
Reviewed-by: Stefan Hajnoczi
---
scripts/simpletrace
From: Mads Ynddal
Moved event processing to the Analyzer class to separate specific analyzer
logic (like caching and function signatures) from the _process function.
This allows for new types of Analyzer-based subclasses without changing
the core code.
Note, that the fn_cache is important for pe
From: Mads Ynddal
Define `SimpleException` to differentiate our exceptions from generic
exceptions (IOError, etc.). Adapted simpletrace to support this and
output to stderr.
Signed-off-by: Mads Ynddal
Reviewed-by: Philippe Mathieu-Daudé
---
scripts/simpletrace.py | 22 ++
From: Mads Ynddal
By moving the dynamic argument construction to keyword-arguments,
we can remove all of the specialized handling, and streamline it.
If a tracing method wants to access these, they can define the
kwargs, or ignore it be placing `**kwargs` at the end of the
function's arguments li
Hi Marc-André and Akihiko,
On 07/06/2023 13:24, Akihiko Odaki wrote:
On 2023/06/07 19:29, Marc-André Lureau wrote:
Hi Antonio
On Wed, Jun 7, 2023 at 1:13 PM Antonio Caggiano
mailto:quic_acagg...@quicinc.com>> wrote:
Multiple graphics devices can be defined with an associated OpenGL
On 2023/5/30 21:18, Christoph Muellner wrote:
From: Christoph Müllner
A previous patch provides a pointer to the RISCVCPUConfig data.
Let's use this to add the necessary code for vendor extensions.
This patch does not change the current behaviour, but clearly
defines how vendor extension supp
On Wed, 17 May 2023 at 09:13, Mohamed ElSayed wrote:
>
> Signed-off-by: Mohamed ElSayed
> ---
> hw/arm/tivac.c| 56 ++
> hw/arm/tm4c123gh6pm_soc.c | 275 ++
> include/hw/arm/tm4c123gh6pm_soc.h | 71
> 3 files changed, 402 ins
These instructions are part of pool2, see the grand tree above
in the file.
Signed-off-by: Siarhei Volkau
---
target/mips/tcg/mxu_translate.c | 296 +++-
1 file changed, 293 insertions(+), 3 deletions(-)
diff --git a/target/mips/tcg/mxu_translate.c b/target/mips/tcg/
The instruction is used to parallel multiply and accumulate
four 8-bit data.
Signed-off-by: Siarhei Volkau
---
target/mips/tcg/mxu_translate.c | 75 +
1 file changed, 75 insertions(+)
diff --git a/target/mips/tcg/mxu_translate.c b/target/mips/tcg/mxu_translate.c
These instructions were designed that they overwrite source
register during partial storing of result.
Signed-off-by: Siarhei Volkau
---
target/mips/tcg/mxu_translate.c | 30 ++
1 file changed, 18 insertions(+), 12 deletions(-)
diff --git a/target/mips/tcg/mxu_transl
The instruction adds/subtracts four 16-bit packed in XRb and XRc.
Placing packed 16-bit results in XRa and XRd.
Signed-off-by: Siarhei Volkau
---
target/mips/tcg/mxu_translate.c | 89 +
1 file changed, 89 insertions(+)
diff --git a/target/mips/tcg/mxu_translate.c
These instructions are same data shift in various directions, thus one
generation function is implemented for all three.
Signed-off-by: Siarhei Volkau
---
target/mips/tcg/mxu_translate.c | 55 +
1 file changed, 55 insertions(+)
diff --git a/target/mips/tcg/mxu_tr
These instructions are part of pool16, see the grand opcode organization
tree on top of the file.
Signed-off-by: Siarhei Volkau
---
target/mips/tcg/mxu_translate.c | 122 +++-
1 file changed, 121 insertions(+), 1 deletion(-)
diff --git a/target/mips/tcg/mxu_translate
The instruction shuffles 8 bytes in two registers by
one of 4 predefined patterns.
Signed-off-by: Siarhei Volkau
---
target/mips/tcg/mxu_translate.c | 81 +
1 file changed, 81 insertions(+)
diff --git a/target/mips/tcg/mxu_translate.c b/target/mips/tcg/mxu_transl
These instructions are dual 32-bit arithmetic shift right and
pack LSBs to 2x 16-bit into a MXU register.
The difference is the shift amount source: immediate or GP reg.
Signed-off-by: Siarhei Volkau
---
target/mips/tcg/mxu_translate.c | 59 +
1 file changed, 59 i
These instructions are part of pool15, see the grand opcode organization
tree on top of the file.
Signed-off-by: Siarhei Volkau
---
target/mips/tcg/mxu_translate.c | 200 +++-
1 file changed, 196 insertions(+), 4 deletions(-)
diff --git a/target/mips/tcg/mxu_translat
The instruction adds two 32-bit values with respect
to corresponding carry flags in MXU_CR.
XRa += XRb + LeftCarry flag;
XRd += XRc + RightCarry flag;
Suddenly, it doesn't modify carry flags as a result of addition.
Signed-off-by: Siarhei Volkau
---
target/mips/tcg/mxu_translate.c | 39 +
This patch series is aimed to add complete support of the
Ingenic MXU extensions of version 1 revision 2.
The serie doesn't split revision 1 and revision 2 of the
MXU ASE as it ought to be, because I have no hardware which
supports revision 1 only. The MXU version 2 is not the subject
of the patch
These instructions are close to D16MAC so common generation function
provided.
Signed-off-by: Siarhei Volkau
---
target/mips/tcg/mxu_translate.c | 74 ++---
1 file changed, 68 insertions(+), 6 deletions(-)
diff --git a/target/mips/tcg/mxu_translate.c b/target/mips/tc
These instructions are part of pool1, see the grand tree above
in the file. Q8ADD is part of pool1 too but belong to another
category of instructions, thus will be made in later patches.
Signed-off-by: Siarhei Volkau
---
target/mips/tcg/mxu_translate.c | 244 +++-
1 f
These instructions are all dual 8-bit addition/subtraction in
various combinations. Most instructions are grouped in pool14,
see the opcode organization in the file.
Signed-off-by: Siarhei Volkau
---
target/mips/tcg/mxu_translate.c | 200
1 file changed, 200 inse
The instruction adds/subtracts two 32-bit values in XRb and XRc.
Placing results in XRa and XRd and updates carry bits for each
path in the MXU control register.
Signed-off-by: Siarhei Volkau
---
target/mips/tcg/mxu_translate.c | 64 +
1 file changed, 64 insertion
These instructions are:
- single 32-bit
- dual 16-bit packed
- quad 8-bit packed
conditional moves.
They are grouped in pool20 in the source code.
Signed-off-by: Siarhei Volkau
---
target/mips/tcg/mxu_translate.c | 188
1 file changed, 188 insertions(+)
diff --g
These instructions are same data shift in various directions, thus one
generation function is implemented for all three.
Signed-off-by: Siarhei Volkau
---
target/mips/tcg/mxu_translate.c | 78 +
1 file changed, 78 insertions(+)
diff --git a/target/mips/tcg/mxu_tr
These instructions do parallel quad 8-bit multiply and accumulate.
They are close to existing Q8MUL Q8MULSU so the generation
function modified to support all of them.
Also the patch fixes decoding of Q8MULSU according to tests on
hardware.
Signed-off-by: Siarhei Volkau
---
target/mips/tcg/mxu_t
Add support for emulating:
- S32LDDV and S32LDDVR
- S32STD and S32STDR
- S32STDV and S32STDVR
MXU instructions.
Add support for emulating MXU instructions with address register
post-modify counterparts:
- S32LDI and S32LDIR
- S32LDIV and S32LDIVR
- S32SDI and S32SDIR
- S32SDIV and S32SDIVR
Refact
These instructions used to multiply 2x32-bit GPR sources & accumulate
result into 64-bit pair of XRF registers.
These instructions stain HI/LO registers with the final result.
Their opcode is close to the MIPS32R1 MADD[U]/MSUB[U], so it have to
call decode_opc_special2_legacy when failing to find
The instruction is used to determine sign of four 16-bit
packed data in parallel.
Signed-off-by: Siarhei Volkau
---
target/mips/tcg/mxu_translate.c | 85 +
1 file changed, 85 insertions(+)
diff --git a/target/mips/tcg/mxu_translate.c b/target/mips/tcg/mxu_transla
The instruction is similar to multiply and accumulate
but works with MXU registers set.
Signed-off-by: Siarhei Volkau
---
target/mips/tcg/mxu_translate.c | 65 +
1 file changed, 65 insertions(+)
diff --git a/target/mips/tcg/mxu_translate.c b/target/mips/tcg/mxu_t
The instruction implements SAD (sum-absolute-difference) operation which
is used in motion estimation algorithms. The instruction handles four
8-bit data in parallel.
Signed-off-by: Siarhei Volkau
---
target/mips/tcg/mxu_translate.c | 45 +
1 file changed, 45 inse
The instruction is similar to multiply and accumulate
but works with MXU registers set.
Signed-off-by: Siarhei Volkau
---
target/mips/tcg/mxu_translate.c | 82 +
1 file changed, 82 insertions(+)
diff --git a/target/mips/tcg/mxu_translate.c b/target/mips/tcg/mxu_t
These instructions are part of pool3, see the grand tree above
in the file.
The instructions are close to D16MUL so common generation function
provided.
Signed-off-by: Siarhei Volkau
---
target/mips/tcg/mxu_translate.c | 95 +++--
1 file changed, 90 insertions(+), 5 d
These instructions are counterparts for D32/Q16-SLL/SLR/SAR with
difference that the shift amount placed into GPR.
Signed-off-by: Siarhei Volkau
---
target/mips/tcg/mxu_translate.c | 166 +++-
1 file changed, 162 insertions(+), 4 deletions(-)
diff --git a/target/mips
These instructions are all dual 16-bit addition/subtraction in
various combinations. The instructions are grouped in pool13,
see the opcode organization in the file.
Signed-off-by: Siarhei Volkau
---
target/mips/tcg/mxu_translate.c | 228 +++-
1 file changed, 227 inse
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