Currently, pc-q35 and pc-i44fx machine models are default to use SMBIOS 2.8
(32-bit entry point). Since SMBIOS 3.0 (64-bit entry point) is now fully
supported since QEMU 7.0, default to use SMBIOS 3.0 for newer machine
models. This is necessary to avoid the following message when launching
a VM wit
Hi,
> -Original Message-
> From: Daniel Henrique Barboza
> Sent: Tuesday, June 6, 2023 6:31 PM
> To: Wang, Xiao W ; qemu-devel@nongnu.org
> Cc: Palmer Dabbelt ; Alistair Francis
> ; Meng, Bin ; Weiwei
> Li ; Liu Zhiwei ; open
> list:RISC-V TCG CPUs
> Subject: Re: [PATCH] target/riscv/vec
>-Original Message-
>From: Peter Xu
>Sent: Tuesday, June 6, 2023 11:42 PM
>Subject: Re: [PATCH v2 2/4] intel_iommu: Fix a potential issue in VFIO dirty
>page sync
>
...
>> >> a/include/exec/memory.h b/include/exec/memory.h index
>> >> c3661b2276c7..eecc3eec6702 100644
>> >> --- a/include
On Wed, 7 Jun 2023 10:33:13 +0800, Yuquan Wang wrote:
>
> Please review the change.
> - sbsa-ref: Replace EHCI with XHCI on sysbus.
> This version updates relevant Kconfig and sbsa.rst file.
>
> Yuquan Wang (1):
> hw/arm/sbsa-ref: use XHCI to replace EHCI
>
> docs/sys
On Tue, 6 Jun 2023 at 19:28, Thomas Huth wrote:
>
> The ppc64 tuxrun tests are currently failing if "slirp" has been
> disabled in the binary since they are using "-netdev user" now.
> We have to skip the test if this network backend is missing.
Do the boot tests require networking? I doubt they
Most of the Aspeed machines use the UART5 device for the boot console,
and QEMU connects the first serial Chardev to this SoC device for this
purpose. See routine connect_serial_hds_to_uarts().
Nevertheless, some machines use another boot console, such as the fuji,
and commit 5d63d0c76c ("hw/arm/a
Boards will use this new property to identify the device CS line and
wire the SPI controllers accordingly.
Cc: Alistair Francis
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Cédric Le Goater
---
include/hw/ssi/ssi.h | 3 +++
hw/ssi/ssi.c | 7 +++
2 files changed, 10 insertions
This change completes commits 5aa281d757 ("aspeed: Introduce a
spi_boot region under the SoC") and 8b744a6a47 ("aspeed: Add a
boot_rom overlap region in the SoC spi_boot container") which
introduced a spi_boot container at the SoC level to map the boot rom
region as an overlap.
It also fixes a Cov
Hello,
This series fixes issues spotted by Coverity and adds a couple of
improvements for the machine definition.
The first is to offer the capability to define all CS of all SPI
controllers without introducing new machine types, using a blockdev on
the command line :
-blockdev node-name=fmc
When the -nodefaults option is set, flash devices should be created
with :
-blockdev node-name=fmc0,driver=file,filename=./flash.img \
-device mx66u51235f,addr=0x0,bus=ssi.0,drive=fmc0 \
To be noted that in this case, the ROM will not be installed and the
initial boot sequence (U-Boot loa
Currently, a set of default flash devices is created at machine init
and drives defined on the QEMU command line are associated to the FMC
and SPI controllers in sequence :
-drive file,format=raw,if=mtd
-drive file,format=raw,if=mtd
The CS lines are wired in the same creation loop. This mak
This should also avoid Coverity to report a memory leak warning when
the QEMU process exits. See CID 1508061.
Reviewed-by: Francisco Iglesias
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Cédric Le Goater
---
hw/arm/aspeed.c | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(
Cortex A7 CPUs with an FPU implementing VFPv4 without NEON support
have 16 64-bit FPU registers and not 32 registers. Let users set the
number of VFP registers with a CPU property.
The primary use case of this property is for the Cortex A7 of the
Aspeed AST2600 SoC.
Signed-off-by: Cédric Le Goate
As mentioned in docs/devel/style.rst "Automatic memory deallocation":
* Variables declared with g_auto* MUST always be initialized,
otherwise the cleanup function will use uninitialized stack memory
This avoids QEMU to coredump when running the "hash test" command
under Zephyr.
Cc: Steven Lee
This to avoid address conflicts on the same SSI bus. Adapt machines
using multiple devices on the same bus to avoid breakage.
Cc: "Edgar E. Iglesias"
Cc: Alistair Francis
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Cédric Le Goater
---
hw/arm/stellaris.c | 4 +++-
hw/
Simple routine to retrieve a DeviceState object on a SPI bus using its
address/cs. It will be useful for the board to wire the CS lines.
Cc: Alistair Francis
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Cédric Le Goater
---
include/hw/ssi/ssi.h | 2 ++
hw/ssi/ssi.c | 15
It will help in getting rid of some drive_get(IF_MTD) calls by
retrieving the BlockBackend directly from the m25p80 device.
Cc: Alistair Francis
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Cédric Le Goater
---
include/hw/block/flash.h | 4
hw/block/m25p80.c| 6 ++
2 fil
and get rid of an unnecessary drive_get(IF_MTD) call.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Cédric Le Goater
---
hw/arm/aspeed.c | 8 +---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
index efc112ca37b0..8beed0c2a66e 100644
---
Hello Nick,
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -443,7 +443,7 @@ void spr_write_generic32(DisasContext *ctx, int sprn, int
gprn)
#endif
}
-void spr_write_CTRL(DisasContext *ctx, int sprn, int gprn)
+static void spr_write_CTRL_ST(DisasContext *ctx, int sprn, int
Since adding MO_ATOM_MASK, the maximum MemOpIdx requires 15 bits,
which overflows the 12 bit field allocated for TCI memory ops.
Expand the field to 16 bits for 2-operand memory ops, and place
the value in TCG_REG_TMP for 3-operand memory ops (same as we
already do for 4-operand memory ops).
Cures
Two recent regressions, both related to recent tcg changes.
Our CI does not test TCI with --enable-debug-tcg, which given timeout
constraints is probably correct, but in this case resulted in an
infinite loop on aarch64 multiarch/memory.c with FEAT_LSE2 enabled.
r~
Richard Henderson (2):
tcg/t
We require either 2 or 4 registers to hold int128_t.
Failure to do so results in a register allocation assert.
Signed-off-by: Richard Henderson
---
tcg/tci/tcg-target.c.inc | 9 +
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.
On 6/6/23 22:46, Richard Henderson wrote:
Two recent regressions, both related to recent tcg changes.
Our CI does not test TCI with --enable-debug-tcg, which given timeout
constraints is probably correct, but in this case resulted in an
infinite loop on aarch64 multiarch/memory.c with FEAT_LSE2
Fabiano Rosas wrote:
> The code in threadinfo.c is only used for the QMP command
> query-migrationthreads. Make it explicit that this is something
> related to QMP.
>
> The current names are also too generic for a piece of code that
> doesn't affect the migration directly in any way.
>
> Signed-of
On 11/2/2022 8:49 AM, Xiaoyao Li wrote:
On 7/12/2022 10:12 AM, Xiaoyao Li wrote:
The issue that fixed by Patch 1 looks fatal though it doesn't appear on
KVM because KVM always searches with assending order and hit with the
correct cpuid leaf 0.
Patch 2 removes the wrong constraint on CPUID leaf
05.06.2023 18:45, Hanna Czenczek wrote:
From: Alexander Ivanov
data_end field in BDRVParallelsState is set to the biggest offset present
in BAT. If this offset is outside of the image, any further write will
create the cluster at this offset and/or the image will be truncated to
this offset on
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