On 6/1/2023 8:12 PM, Wu, Fei wrote:
> On 6/1/2023 10:40 AM, Richard Henderson wrote:
>> On 5/30/23 01:35, Fei Wu wrote:
>>> +static void do_dump_tbs_info(int total, int sort_by)
>>> +{
>>> + id = 1;
>>> + GList *i;
>>> + int count = total;
>>> +
>>> + g_list_free(last_search);
>>> +
On Mon, 5 Jun 2023 16:39:05 -0500
Suravee Suthikulpanit wrote:
> Currently, pc-q35 and pc-i44fx machine models are default to use SMBIOS 2.8
> (32-bit entry point). Since SMBIOS 3.0 (64-bit entry point) is now fully
> supported since QEMU 7.0, default to use SMBIOS 3.0 for newer machine
> models.
On Mon, 5 Jun 2023 16:39:04 -0500
Suravee Suthikulpanit wrote:
> In preparation for subsequent code to upgrade default SMBIOS
> entry point type. There is no functional change.
>
> Signed-off-by: Suravee Suthikulpanit
> ---
> hw/i386/pc.c | 12
> hw/i386/pc_piix.c | 9 --
On Mon, 5 Jun 2023 16:39:06 -0500
Suravee Suthikulpanit wrote:
> Since KVM_MAX_VCPUS is currently defined to 1024 for x86 as shown in
> arch/x86/include/asm/kvm_host.h, update QEMU limits to the same number.
>
> In case KVM could not support the specified number of vcpus, QEMU would
> return the
05.06.2023 18:45, Hanna Czenczek wrote:
When processing vectored guest requests that are not aligned to the
storage request alignment, we pad them by adding head and/or tail
buffers for a read-modify-write cycle.
The guest can submit I/O vectors up to IOV_MAX (1024) in length, but
with this padd
On Tue, 6 Jun 2023 09:35:41 +0200
Igor Mammedov wrote:
> On Mon, 5 Jun 2023 16:39:05 -0500
> Suravee Suthikulpanit wrote:
[...]
> > +/* For pc-i44fx-8.0 and older, use SMBIOS 2.8 by default */
> > +pcmc->default_smbios_ep_type = SMBIOS_ENTRY_POINT_TYPE_32;
> > }
[...]
> > static void p
Let pip decide whether a new version should be installed or the current
one is okay. This ensures that the virtual environment is updated
(either upgraded or downgraded) whenever a new version of a package is
requested.
The hardest part here is figuring out if a package is installed in
the venv (
Commit 752614cab8e6 ("target/riscv: rvv: Add tail agnostic for vector
load / store instructions") added an extra check for LMUL fragmentation,
intended for setting the "rest tail elements" in the last register for a
segment load insn.
Actually, the max_elements derived in vext_ld*() won't be a fra
On 06.06.23 10:00, Michael Tokarev wrote:
05.06.2023 18:45, Hanna Czenczek wrote:
When processing vectored guest requests that are not aligned to the
storage request alignment, we pad them by adding head and/or tail
buffers for a read-modify-write cycle.
The guest can submit I/O vectors up to I
On Mon, 5 Jun 2023 at 18:57, Philippe Mathieu-Daudé wrote:
>
> Follow QEMU CODING_STYLE, use the type definition.
>
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> include/qemu/uri.h | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/include/qemu/uri.h b/include/qemu/uri.h
On Mon, 5 Jun 2023 at 18:58, Philippe Mathieu-Daudé wrote:
>
> By default, C function prototypes declared in headers are visible,
> so there is no need to declare them as 'extern' functions.
> Remove this redundancy in a single bulk commit; do not modify:
>
> - meson.build (used to check functio
W dniu 5.06.2023 o 11:55, Yuquan Wang pisze:
The current sbsa-ref cannot use EHCI controller which is only
able to do 32-bit DMA, since sbsa-ref doesn't have RAM below 4GB.
Hence, this uses XHCI to provide a usb controller with 64-bit
DMA capablity instead of EHCI.
Signed-off-by: Yuquan Wang
R
From: qianfan Zhao
Allwinner R40 (sun8i) SoC features a Quad-Core Cortex-A7 ARM CPU,
and a Mali400 MP2 GPU from ARM. It's also known as the Allwinner T3
for In-Car Entertainment usage, A40i and A40pro are variants that
differ in applicable temperatures range (industrial and military).
Signed-off
From: qianfan Zhao
Types of memory that the SDRAM controller supports are DDR2/DDR3
and capacities of up to 2GiB. This commit adds emulation support
of the Allwinner R40 SDRAM controller.
This driver only support 256M, 512M and 1024M memory now.
Signed-off-by: qianfan Zhao
Signed-off-by: Peter
From: Richard Henderson
This fixes a bug in that these two insns should have been using atomic
16-byte stores, since MTE is ARMv8.5 and LSE2 is mandatory from ARMv8.4.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
Message-id: 20230530191438.411344-7-richard.hender...@linaro.org
S
From: Vikram Garhwal
Connect CANFD0 and CANFD1 on the Versal-virt machine and update xlnx-versal-virt
document with CANFD command line examples.
Signed-off-by: Vikram Garhwal
Reviewed-by: Peter Maydell
Reviewed-by: Francisco Iglesias
Signed-off-by: Peter Maydell
---
docs/system/arm/xlnx-ver
From: Richard Henderson
Pass the completed memop to gen_mte_check1_mmuidx.
For the moment, do nothing more than extract the size.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
Message-id: 20230530191438.411344-13-richard.hender...@linaro.org
Signed-off-by: Peter Maydell
---
tar
From: qianfan Zhao
A64's sd register was similar to H3, and it introduced a new register
named SAMP_DL_REG location at 0x144. The dma descriptor buffer size of
mmc2 is only 8K and the other mmc controllers has 64K.
Also fix allwinner-r40's mmc controller type.
Signed-off-by: qianfan Zhao
Signe
From: Richard Henderson
While we don't require 16-byte atomicity here, using a single larger
operation simplifies the code. Introduce finalize_memop_asimd for this.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
Message-id: 20230530191438.411344-6-richard.hender...@linaro.org
Sig
From: Francesco Cagnin
Required for guest debugging. The code has been structured like the KVM
counterpart.
Signed-off-by: Francesco Cagnin
Message-id: 20230601153107.81955-4-fcag...@quarkslab.com
Reviewed-by: Peter Maydell
Signed-off-by: Peter Maydell
---
include/sysemu/hvf.h | 22 +++
From: qianfan Zhao
Only a few important registers are added, especially the SRAM_VER
register.
Signed-off-by: qianfan Zhao
Reviewed-by: Niek Linnenbank
Signed-off-by: Peter Maydell
---
include/hw/arm/allwinner-r40.h| 3 +
include/hw/misc/allwinner-sramc.h | 69 +++
hw/arm/allw
From: Francesco Cagnin
Required for guest debugging.
Signed-off-by: Francesco Cagnin
Message-id: 20230601153107.81955-3-fcag...@quarkslab.com
Reviewed-by: Peter Maydell
Signed-off-by: Peter Maydell
---
target/arm/hvf/hvf.c | 213 +++
1 file changed, 21
From: Richard Henderson
We are going to need the complete memop beforehand,
so let's not compute it twice.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
Message-id: 20230530191438.411344-11-richard.hender...@linaro.org
Signed-off-by: Peter Maydell
---
target/arm/tcg/translate-a
5 13:16:56 -0700)
are available in the Git repository at:
https://git.linaro.org/people/pmaydell/qemu-arm.git
tags/pull-target-arm-20230606
for you to fetch changes up to f9ac778898cb28307e0f91421aba34d43c34b679:
target/arm: trap DCC access in user mode emulation (2023-06-06 10:1
From: Richard Henderson
We are going to need the complete memop beforehand,
so let's not compute it twice.
Reviewed-by: Peter Maydell
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
Message-id: 20230530191438.411344-12-richard.hender...@linaro.org
Signed-off-by: Peter May
From: Richard Henderson
No need to duplicate this check across multiple call sites.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
Message-id: 20230530191438.411344-9-richard.hender...@linaro.org
Signed-off-by: Peter Maydell
---
target/arm/tcg/translate-a64.c | 44 ++
From: qianfan Zhao
R40 has two ethernet controllers named as emac and gmac. The emac is
compatibled with A10, and the GMAC is compatibled with H3.
Signed-off-by: qianfan Zhao
Signed-off-by: Peter Maydell
---
include/hw/arm/allwinner-r40.h | 6
hw/arm/allwinner-r40.c | 50 +++
From: qianfan Zhao
R40 has eight UARTs, support both 16450 and 16550 compatible modes.
Signed-off-by: qianfan Zhao
Signed-off-by: Peter Maydell
---
include/hw/arm/allwinner-r40.h | 8
hw/arm/allwinner-r40.c | 34 +++---
2 files changed, 39 inserti
From: Zhuojia Shen
Accessing EL0-accessible Debug Communication Channel (DCC) registers in
user mode emulation is currently enabled. However, it does not match
Linux behavior as Linux sets MDSCR_EL1.TDCC on startup to disable EL0
access to DCC (see __cpu_setup() in arch/arm64/mm/proc.S).
This p
From: Zhuojia Shen
Test execution of DC CVAP and DC CVADP instructions under user mode
emulation.
Signed-off-by: Zhuojia Shen
Reviewed-by: Peter Maydell
Reviewed-by: Richard Henderson
Signed-off-by: Peter Maydell
---
tests/tcg/aarch64/dcpodp.c| 63 +++
te
From: Richard Henderson
While we don't require 16-byte atomicity here, using a single larger
load simplifies the code, and makes it a closer match to STXP.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
Message-id: 20230530191438.411344-5-richard.hender...@linaro.org
Signed-off-by
From: qianfan Zhao
This patch adds minimal support for AXP-221 PMU and connect it to
bananapi M2U board.
Signed-off-by: qianfan Zhao
Signed-off-by: Peter Maydell
---
hw/arm/bananapi_m2u.c | 6 +
hw/misc/axp209.c | 238 ---
hw/misc/axp2xx.c | 283 +++
From: qianfan Zhao
The CCU provides the registers to program the PLLs and the controls
most of the clock generation, division, distribution, synchronization
and gating.
This commit adds support for the Clock Control Unit which emulates
a simple read/write register interface.
Signed-off-by: qian
From: Richard Henderson
Let finalize_memop_atom be the new basic function, with
finalize_memop and finalize_memop_pair testing FEAT_LSE2
to apply the appropriate atomicity.
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
Message-id: 202305301914
From: Richard Henderson
We have many other instances of stg in the testsuite;
change these to provide an instance of stz2g.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
Message-id: 20230530191438.411344-19-richard.hender...@linaro.org
Signed-off-by: Peter Maydell
---
tests/tcg
From: Richard Henderson
Push the mte check behind the exclusive_addr check.
Document the several ways that we are still out of spec
with this implementation.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
Message-id: 20230530191438.411344-18-richard.hender...@linaro.org
Signed-off
From: Vikram Garhwal
The Xilinx Versal CANFD controller is developed based on SocketCAN, QEMU CAN bus
implementation. Bus connection and socketCAN connection for each CAN module
can be set through command lines.
Signed-off-by: Vikram Garhwal
Reviewed-by: Francisco Iglesias
Signed-off-by: Peter
From: Francesco Cagnin
Guests can now be debugged through the gdbstub. Support is added for
single-stepping, software breakpoints, hardware breakpoints and
watchpoints. The code has been structured like the KVM counterpart.
While guest debugging is enabled, the guest can still read and write the
From: Richard Henderson
Round len_align to 16 instead of 8, handling an odd 8-byte as part
of the tail. Use MO_ATOM_NONE to indicate that all of these memory
ops have only byte atomicity.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
Message-id: 20230530191438.411344-8-richard.h
From: Francesco Cagnin
These helpers will be also used for HVF. Aside from reformatting a
couple of comments for 'checkpatch.pl' and updating meson to compile
'hyp_gdbstub.c', this is just code motion.
Signed-off-by: Francesco Cagnin
Reviewed-by: Alex Bennée
Reviewed-by: Peter Maydell
Message
From: Richard Henderson
With -cpu max and FEAT_LSE2, the __aarch64__ section will only raise
an alignment exception when the load crosses a 16-byte boundary.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
Message-id: 20230530191438.411344-20-richard.hender...@linaro.org
Signed-off
From: Richard Henderson
FEAT_LSE2 only requires that atomic operations not cross a
16-byte boundary. Ordered operations may be completely
unaligned if SCTLR.nAA is set.
Because this alignment check is so special, do it by hand.
Make sure not to keep TCG temps live across the branch.
Signed-off
From: qianfan Zhao
TWI(i2c) is designed to be used as an interface between CPU host and the
serial 2-Wire bus. It can support all standard 2-Wire transfer, can be
operated in standard mode(100kbit/s) or fast-mode, supporting data rate
up to 400kbit/s.
Signed-off-by: qianfan Zhao
Reviewed-by: Ni
From: Vikram Garhwal
Signed-off-by: Vikram Garhwal
Reviewed-by: Peter Maydell
Reviewed-by: Francisco Iglesias
Signed-off-by: Peter Maydell
---
MAINTAINERS | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/MAINTAINERS b/MAINTAINERS
index 55668d63368..4b2639def6d 100644
--- a
From: Richard Henderson
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
Message-id: 20230530191438.411344-3-richard.hender...@linaro.org
Signed-off-by: Peter Maydell
---
target/arm/cpu.h | 5 +
1 file changed, 5 insertions(+)
diff --git a/
From: Richard Henderson
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
Message-id: 20230530191438.411344-21-richard.hender...@linaro.org
Signed-off-by: Peter Maydell
---
docs/system/arm/emulation.rst | 1 +
target/arm/tcg/cpu64.c| 1 +
2 files changed, 2 insertions(+)
di
From: Richard Henderson
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
Message-id: 20230530191438.411344-16-richard.hender...@linaro.org
Signed-off-by: Peter Maydell
---
target/arm/cpu.h | 3 ++-
target/arm/tcg/translate.h | 2 ++
target/arm/tcg/hflags.c
From: Richard Henderson
Fixes a bug in that with SCTLR.A set, we should raise any
alignment fault before raising any MTE check fault.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
Message-id: 20230530191438.411344-15-richard.hender...@linaro.org
Signed-off-by: Peter Maydell
---
From: Richard Henderson
This is required for LSE2, where the pair must be treated atomically if
it does not cross a 16-byte boundary. But it simplifies the code to do
this always.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
Message-id: 20230530191438.411344-10-richard.hender..
From: Zhuojia Shen
DC CVAP and DC CVADP instructions can be executed in EL0 on Linux,
either directly when SCTLR_EL1.UCI == 1 or emulated by the kernel (see
user_cache_maint_handler() in arch/arm64/kernel/traps.c).
This patch enables execution of the two instructions in user mode
emulation.
Sig
From: qianfan Zhao
Add documents for Banana Pi M2U
Signed-off-by: qianfan Zhao
Reviewed-by: Niek Linnenbank
[PMM: Minor format fixes to correct sphinx errors]
Signed-off-by: Peter Maydell
---
docs/system/arm/bananapi_m2u.rst | 139 +++
docs/system/target-arm.rst
From: qianfan Zhao
Add test case for booting from initrd and sd card.
Signed-off-by: qianfan Zhao
Reviewed-by: Niek Linnenbank
Tested-by: Niek Linnenbank
Signed-off-by: Peter Maydell
---
tests/avocado/boot_linux_console.py | 176
1 file changed, 176 insertions(+
From: Richard Henderson
Pass the individual memop to gen_mte_checkN.
For the moment, do nothing with it.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
Message-id: 20230530191438.411344-14-richard.hender...@linaro.org
Signed-off-by: Peter Maydell
---
target/arm/tcg/translate-a64
From: Vikram Garhwal
The QTests perform three tests on the Xilinx VERSAL CANFD controller:
Tests the CANFD controllers in loopback.
Tests the CANFD controllers in normal mode with CAN frame.
Tests the CANFD controllers in normal mode with CANFD frame.
Signed-off-by: Vikram Garhwal
A
From: Richard Henderson
Document the meaning of exclusive_high in a big-endian context,
and why we can't change it now.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
Message-id: 20230530191438.411344-2-richard.hender...@linaro.org
Signed-off-by: Peter Maydell
---
target/arm/cpu
On Mon, Jun 05, 2023 at 11:52:18AM +0200, Paolo Bonzini wrote:
> Compared to submodules, .wrap files have several advantages:
>
> * option parsing and downloading is delegated to meson
>
> * the commit is stored in a text file instead of a magic entry in the
> git tree object
>
> * we could st
On Tue, 6 Jun 2023, Mark Cave-Ayland wrote:
On 05/06/2023 07:58, Bernhard Beschow wrote:
Am 1. Juni 2023 12:45:47 UTC schrieb Mark Cave-Ayland
:
On 01/06/2023 13:07, Michael S. Tsirkin wrote:
On Thu, May 25, 2023 at 05:03:15PM +0100, Mark Cave-Ayland wrote:
On 23/05/2023 20:56, Bernhard Besc
On Mon, Jun 05, 2023 at 11:52:19AM +0200, Paolo Bonzini wrote:
> Move the handling of the roms/SLOF submodule out of the main Makefile,
> since we are going to remove submodules from the build process of QEMU.
>
> Signed-off-by: Paolo Bonzini
> ---
> .gitlab-ci.d/buildtest-template.yml | 2 +-
>
On Mon, Jun 05, 2023 at 11:52:20AM +0200, Paolo Bonzini wrote:
> In the beginning, the network bootloader was considered experimental and
> thus optional, but it is well established nowadays and configure always
> checks for roms/SLOF before compiling pc-bios/s390-ccw.
>
> Therefore, it makes sens
On Mon, Jun 05, 2023 at 11:52:21AM +0200, Paolo Bonzini wrote:
> Unlike other subprojects, these require an overlay directory to include
> meson rules to build the libraries. The rules are basically lifted
> from tests/fp/meson.build, with a few changes to create platform.h
> and publish a depende
On Mon, Jun 05, 2023 at 11:52:22AM +0200, Paolo Bonzini wrote:
> The only remaining user of submodules at build time is roms/SLOF,
> which is handled in pc-bios/s390-ccw/Makefile. Remove the relevant
> code from the main makefile.
>
> Signed-off-by: Paolo Bonzini
> ---
> .gitlab-ci.d/buildtest-
On Mon, Jun 05, 2023 at 11:52:23AM +0200, Paolo Bonzini wrote:
> Reuse --enable/--disable-download to control git submodules as well.
> Adjust the error messages of git-submodule.sh to refer to the new
> option.
>
> Signed-off-by: Paolo Bonzini
> ---
> configure
On Tue, 6 Jun 2023 at 10:47, Marcin Juszkiewicz
wrote:
>
> W dniu 5.06.2023 o 11:55, Yuquan Wang pisze:
> > The current sbsa-ref cannot use EHCI controller which is only
> > able to do 32-bit DMA, since sbsa-ref doesn't have RAM below 4GB.
> > Hence, this uses XHCI to provide a usb controller with
On 05/06/2023 11.52, Paolo Bonzini wrote:
Move the handling of the roms/SLOF submodule out of the main Makefile,
since we are going to remove submodules from the build process of QEMU.
Signed-off-by: Paolo Bonzini
---
.gitlab-ci.d/buildtest-template.yml | 2 +-
configure
On 05/06/2023 11.52, Paolo Bonzini wrote:
In the beginning, the network bootloader was considered experimental and
thus optional, but it is well established nowadays and configure always
checks for roms/SLOF before compiling pc-bios/s390-ccw.
Therefore, it makes sense to always build it together
Socket transport backend for 'migrate'/'migrate-incoming' QAPIs accept
new wire protocol of MigrateAddress struct.
It is achived by parsing 'uri' string and storing migration parameters
required for socket connection into well defined SocketAddress struct.
Suggested-by: Aravind Retnakaran
Signed
Integrated MigrateChannelList with all transport backends (socket, exec
and rdma) for both source and destination migration code flow.
Suggested-by: Aravind Retnakaran
Signed-off-by: Het Gala
---
migration/migration.c | 77 ---
migration/socket.c| 5
RDMA based transport backend for 'migrate'/'migrate-incoming' QAPIs
accept new wire protocol of MigrateAddress struct.
It is achived by parsing 'uri' string and storing migration parameters
required for RDMA connection into well defined InetSocketAddress struct.
Suggested-by: Aravind Retnakaran
This patch introduces well defined MigrateAddress struct and its related
child objects.
The existing argument of 'migrate' and 'migrate-incoming' QAPI - 'uri'
is of string type. The current migration flow follows double encoding
scheme for fetching migration parameters such as 'uri' and this is
n
Adding multifd tcp common test case for modified QAPI syntax defined.
Suggested-by: Aravind Retnakaran
Signed-off-by: Het Gala
---
tests/qtest/migration-test.c | 45
1 file changed, 45 insertions(+)
diff --git a/tests/qtest/migration-test.c b/tests/qtest/mi
migration_channels_and_uri_compatible() check for transport mechanism
suitable for multifd migration gets executed when the caller calls old
uri syntax. It needs it to be run when using the mordern MigrateCHannel
QAPI syntax too.
After URI -> 'MigrateChannel' object conversion,
migration_channels_
This patch parses 'migrate' and 'migrate-incoming' QAPI's 'uri' parameter
with all the migration connection related information and stores them
inside well defined 'MigrateAddress' struct.
Misc: limit line width in exec.c to 80 characters recommended by Qemu.
Suggested-by: Aravind Retnakaran
Sig
MigrateChannelList allows to connect accross multiple interfaces. Added
MigrateChannelList struct as argument to migration QAPIs.
Future patchset series plans to include multiple MigrateChannels
for multiple interfaces to be connected. That is the reason,
'MigrateChannelList'
is the preferred choi
This is v6 patchset of modified 'migrate' and 'migrate-incoming' QAPI design
for upstream review.
Would like to thank all the maintainers that actively participated in the v5
patchset discussion and gave insightful suggestions to improve the patches.
Link to previous upstream community patchset
Exec transport backend for 'migrate'/'migrate-incoming' QAPIs accept
new wire protocol of MigrateAddress struct.
It is achived by parsing 'uri' string and storing migration parameters
required for exec connection into strList struct.
Suggested-by: Aravind Retnakaran
Signed-off-by: Het Gala
---
qemu_start_incoming_migration needs to check the number of multifd
channels or postcopy ram channels to configure the backlog parameter (i.e.
the maximum length to which the queue of pending connections for sockfd
may grow) of listen(). So enforce the usage of postcopy-preempt and
multifd as below:
The Postcopy preempt capability is expected to be set before incoming
starts, so change the postcopy tests to start with deferred incoming and
call migrate-incoming after the cap has been set.
Why the existing tests (without this patch) didn't fail?
There could be two reasons:
1) "backlog" specifi
Setting the cap/params of multifd and postcopy preempt is expected
to be done before incoming starts, as the number of multifd channels or
postcopy ram channels is used by qemu_start_incoming_migration (to
listen on the number of pending connections).
Enfocre the cap/params of multifd and postcopy
W dniu 6.06.2023 o 12:04, Peter Maydell pisze:
On Tue, 6 Jun 2023 at 10:47, Marcin Juszkiewicz
wrote:
W dniu 5.06.2023 o 11:55, Yuquan Wang pisze:
The current sbsa-ref cannot use EHCI controller which is only
able to do 32-bit DMA, since sbsa-ref doesn't have RAM below 4GB.
Hence, this uses X
Hi,
On 6/6/23 05:34, Xiao Wang wrote:
Commit 752614cab8e6 ("target/riscv: rvv: Add tail agnostic for vector
load / store instructions") added an extra check for LMUL fragmentation,
intended for setting the "rest tail elements" in the last register for a
segment load insn.
Actually, the max_ele
On Mon, 5 Jun 2023 at 14:35, Guenter Roeck wrote:
>
> On 6/5/23 02:40, Peter Maydell wrote:
> > If you can provide a link to the zImage and the dtb to reproduce
> > as well, that would be helpful.
>
>
> Please see http://server.roeck-us.net/qemu/arm-v7/.
Thanks. I've identified the cause of the r
QEMU allows qemu_irq lines to transfer arbitrary integers. However
the convention is that for a simple IRQ line the values transferred
are always 0 and 1. The A10 SD controller device instead assumes a
0-vs-non-0 convention, which happens to work with the interrupt
controller it is wired up to.
In commit 2c5fa0778c3b430 we fixed an endianness bug in the Allwinner
A10 PIC model; however in the process we introduced a regression.
This is because the old code was robust against the incoming 'level'
argument being something other than 0 or 1, whereas the new code was
not.
In particular, the
In commit 2c5fa0778c3b430 we fixed an endianness bug in the Allwinner
A10 PIC model; however in the process we introduced a regression.
This is because the old code was robust against the incoming 'level'
argument being something other than 0 or 1, whereas the new code was
not.
In particular, the
06.06.2023 11:45, Hanna Czenczek wrote:
On 06.06.23 10:00, Michael Tokarev wrote:
..
This seems to be over-complicated, both of them, no?
I would have preferred to have this discussion while the patch was still on-list for review (this specific version was for two months, counting from
the f
On 05/06/2023 17:57, Peter Xu wrote:
> On Tue, May 30, 2023 at 06:59:25PM +0100, Joao Martins wrote:
>> Much like pci_device_iommu_address_space() fetches the IOMMU AS, add a
>> pci_device_iommu_memory_region() which lets it return an the IOMMU MR
>> associated with it. The IOMMU MR is returned cor
Smepmp is a ratified extension which qemu refers to as epmp.
Rename epmp to smepmp and add it to extension list so that
it is added to the isa string.
Signed-off-by: Himanshu Chauhan
---
target/riscv/cpu.c | 9 +
target/riscv/cpu_cfg.h | 2 +-
target/riscv/csr.c | 6 +++---
ta
From: Marc-André Lureau
It will be used from other units.
Signed-off-by: Marc-André Lureau
---
include/ui/egl-helpers.h | 2 ++
ui/egl-helpers.c | 12 +---
2 files changed, 7 insertions(+), 7 deletions(-)
diff --git a/include/ui/egl-helpers.h b/include/ui/egl-helpers.h
index
From: Marc-André Lureau
Hi,
The D-Bus display doesn't work on Windows, since it relies on FDs transfer over
Unix domain socket. This isn't (yet) supported on Windows. To make it work, the
interfaces are adapted to use 'ay' WSASocketW data instead of 'h' (in a similar
fashion as QMP 'get-win32-so
From: Marc-André Lureau
Signed-off-by: Marc-André Lureau
---
tests/qtest/dbus-display-test.c | 43 ++---
tests/qtest/meson.build | 2 +-
2 files changed, 41 insertions(+), 4 deletions(-)
diff --git a/tests/qtest/dbus-display-test.c b/tests/qtest/dbus-displa
From: Marc-André Lureau
Make GBM optional for EGL code, and enable the build for win32.
Signed-off-by: Marc-André Lureau
---
qapi/ui.json | 5 ++---
include/ui/egl-helpers.h | 7 ++-
ui/egl-headless.c| 20 +---
ui/egl-helpers.c | 38 +++
From: Marc-André Lureau
Used in the following test on win32, to share sockets with the QEMU
process.
Signed-off-by: Marc-André Lureau
---
tests/qtest/libqtest.h | 9 +
tests/qtest/libqtest.c | 5 +
2 files changed, 14 insertions(+)
diff --git a/tests/qtest/libqtest.h b/tests/qtest
From: Marc-André Lureau
Similar to egl_fb_read(), same limitations, but with extra arguments to
read a subset of the framebuffer. Used in following commits.
Signed-off-by: Marc-André Lureau
---
include/ui/egl-helpers.h | 1 +
ui/egl-helpers.c | 14 ++
2 files changed, 15 i
From: Marc-André Lureau
Signed-off-by: Marc-André Lureau
---
ui/dbus-listener.c | 6 ++
ui/trace-events| 3 +++
2 files changed, 9 insertions(+)
diff --git a/ui/dbus-listener.c b/ui/dbus-listener.c
index e92eff66e3..8605dffd8a 100644
--- a/ui/dbus-listener.c
+++ b/ui/dbus-listener.c
@@
On 05/06/2023 17:56, Alex Williamson wrote:
External email: Use caution opening links or attachments
On Sun, 4 Jun 2023 12:33:43 +0300
Avihai Horon wrote:
On 01/06/2023 23:22, Alex Williamson wrote:
External email: Use caution opening links or attachments
On Tue, 30 May 2023 17:48:20 +0
From: Marc-André Lureau
This property is similar to ``org.freedesktop.DBus.Interfaces`` property
on the bus interface: it's an array of strings listing the extra
interfaces and capabilities available, in a convenient way.
Most interfaces are implicit, as they are required. For
``org/qemu/Display
From: Marc-André Lureau
Allocate pixman bits for scanouts with qemu_win32_map_alloc() so we can
set a shareable handle on the associated display surface.
Note: when bits are provided to pixman_image_create_bits(), you must also give
the rowstride (the argument is ignored when bits is NULL)
Sign
From: Marc-André Lureau
D-Bus doesn't support fd-passing on Windows (AF_UNIX doesn't have
SCM_RIGHTS yet, but there are other means to share objects. I have
proposed various solutions upstream, but none seem fitting enough atm).
To make the "-display dbus" work on Windows, implement an alternati
From: Marc-André Lureau
Windows GL drivers are notoriously not very good. Otoh, ANGLE provides
rock solid GLES implementation on top of direct3d. We should recommend
it and default to ES when using EGL (users can easily override this if
necessary)
Signed-off-by: Marc-André Lureau
---
ui/egl-he
From: Marc-André Lureau
virgl offers a few features that require to have access to the
underlying EGLDisplay. This is the case for the D3D texture sharing support.
The API callback is merged for virgl 1.0:
https://gitlab.freedesktop.org/virgl/virglrenderer/-/merge_requests/1113
Signed-off-by: M
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