[PULL 05/23] tcg/mips: Split out tcg_out_movi_one

Emit all constants that can be loaded in exactly one insn. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- tcg/mips/tcg-target.c.inc | 26 -- 1 file changed, 20 insertions(+), 6 deletions(-) diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-

[PULL 06/23] tcg/mips: Split out tcg_out_movi_two

Emit all 32-bit signed constants, which can be loaded in two insns. Signed-off-by: Richard Henderson --- tcg/mips/tcg-target.c.inc | 35 --- 1 file changed, 24 insertions(+), 11 deletions(-) diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc index

[PULL 02/23] tcg/mips: Move TCG_GUEST_BASE_REG to S7

No functional change; just moving the saved reserved regs to the end. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- tcg/mips/tcg-target.c.inc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc

[PULL 12/23] tcg/mips: Replace MIPS_BE with HOST_BIG_ENDIAN

Since e03b56863d2b, which replaced HOST_WORDS_BIGENDIAN with HOST_BIG_ENDIAN, there is no need to define a second symbol which is [0,1]. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- tcg/mips/tcg-target.c.inc | 46 +-- 1 file change

[PULL 09/23] tcg/mips: Try tb-relative addresses in tcg_out_movi

These addresses are often loaded by the qemu_ld/st slow path, for loading the retaddr value. Signed-off-by: Richard Henderson --- tcg/mips/tcg-target.c.inc | 13 + 1 file changed, 13 insertions(+) diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc index 068deab8c9..9

[PULL 03/23] tcg/mips: Unify TCG_GUEST_BASE_REG tests

In tcg_out_qemu_ld/st, we already check for guest_base matching int16_t. Mirror that when setting up TCG_GUEST_BASE_REG in the prologue. Signed-off-by: Richard Henderson --- tcg/mips/tcg-target.c.inc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tcg/mips/tcg-target.c.inc b/

[PULL 01/23] tcg/mips: Move TCG_AREG0 to S8

No functional change; just moving the saved reserved regs to the end. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- tcg/mips/tcg-target.h | 2 +- tcg/mips/tcg-target.c.inc | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/tcg/mips/tcg-target

[PULL 10/23] tcg/mips: Try three insns with shift and add in tcg_out_movi

These sequences are inexpensive to test. Maxing out at three insns results in the same space as a load plus the constant pool entry. Signed-off-by: Richard Henderson --- tcg/mips/tcg-target.c.inc | 44 +++ 1 file changed, 44 insertions(+) diff --git a/tcg/mi

[PULL 04/23] tcg/mips: Create and use TCG_REG_TB

This vastly reduces the size of code generated for 64-bit addresses. The code for exit_tb, for instance, where we load a (tagged) pointer to the current TB, goes from 0x400aa9725c: li v0,64 0x400aa97260: dsll v0,v0,0x10 0x400aa97264: ori v0,v0,0xaa9 0x400aa97268: dsll v0,v0,

[PULL 16/23] tcg/riscv: Support ADD.UW, SEXT.B, SEXT.H, ZEXT.H from Zba+Zbb

Acked-by: Alistair Francis Reviewed-by: Daniel Henrique Barboza Signed-off-by: Richard Henderson --- tcg/riscv/tcg-target.c.inc | 32 1 file changed, 24 insertions(+), 8 deletions(-) diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc index edf

[PULL 23/23] tcg/riscv: Support CTZ, CLZ from Zbb

Acked-by: Alistair Francis Reviewed-by: Daniel Henrique Barboza Signed-off-by: Richard Henderson --- tcg/riscv/tcg-target-con-set.h | 1 + tcg/riscv/tcg-target.h | 8 tcg/riscv/tcg-target.c.inc | 35 ++ 3 files changed, 40 insertions(+), 4

[PULL 00/23] tcg patch queue

The following changes since commit b300c134465465385045ab705b68a42699688332: Merge tag 'pull-vfio-20230524' of https://github.com/legoater/qemu into staging (2023-05-24 14:23:41 -0700) are available in the Git repository at: https://gitlab.com/rth7680/qemu.git tags/pull-tcg-202

[PULL 18/23] tcg/riscv: Support rotates from Zbb

Acked-by: Alistair Francis Reviewed-by: Daniel Henrique Barboza Signed-off-by: Richard Henderson --- tcg/riscv/tcg-target.h | 4 ++-- tcg/riscv/tcg-target.c.inc | 34 ++ 2 files changed, 36 insertions(+), 2 deletions(-) diff --git a/tcg/riscv/tcg-target.h b

[PULL 11/23] tcg/mips: Use qemu_build_not_reached for LO/HI_OFF

The new(ish) macro produces a compile-time error instead of a link-time error. Signed-off-by: Richard Henderson --- tcg/mips/tcg-target.c.inc | 8 +++- 1 file changed, 3 insertions(+), 5 deletions(-) diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc index b86a0679af..fd92cc

[PULL 07/23] tcg/mips: Use the constant pool for 64-bit constants

During normal processing, the constant pool is accessible via TCG_REG_TB. During the prologue, it is accessible via TCG_REG_T9. Signed-off-by: Richard Henderson --- tcg/mips/tcg-target.h | 1 + tcg/mips/tcg-target.c.inc | 65 +-- 2 files changed, 49 inse

[PULL 08/23] tcg/mips: Aggressively use the constant pool for n64 calls

Repeated calls to a single helper are common -- especially the ones for softmmu memory access. Prefer the constant pool to longer sequences to increase sharing. Signed-off-by: Richard Henderson --- tcg/mips/tcg-target.c.inc | 16 +--- 1 file changed, 13 insertions(+), 3 deletions(-)

[PULL 21/23] tcg/riscv: Improve setcond expansion

Split out a helper function, tcg_out_setcond_int, which does not always produce the complete boolean result, but returns a set of flags to do so. Based on 21af16198425, the same improvement for loongarch64. Acked-by: Alistair Francis Reviewed-by: Daniel Henrique Barboza Signed-off-by: Richard H

[PULL 14/23] tcg/riscv: Probe for Zba, Zbb, Zicond extensions

Define a useful subset of the extensions. Probe for them via compiler pre-processor feature macros and SIGILL. Acked-by: Alistair Francis Reviewed-by: Daniel Henrique Barboza Signed-off-by: Richard Henderson --- tcg/riscv/tcg-target.h | 6 +++ tcg/riscv/tcg-target.c.inc | 96

[PULL 22/23] tcg/riscv: Implement movcond

Implement with and without Zicond. Without Zicond, we were letting the middle-end expand to a 5 insn sequence; better to use a branch over a single insn. Acked-by: Alistair Francis Reviewed-by: Daniel Henrique Barboza Signed-off-by: Richard Henderson --- tcg/riscv/tcg-target-con-set.h | 1 +

[PULL 17/23] tcg/riscv: Use ADD.UW for guest address generation

The instruction is a combined zero-extend and add. Use it for exactly that. Acked-by: Alistair Francis Reviewed-by: Daniel Henrique Barboza Signed-off-by: Richard Henderson --- tcg/riscv/tcg-target.c.inc | 33 ++--- 1 file changed, 22 insertions(+), 11 deletions(-)

[PULL 15/23] tcg/riscv: Support ANDN, ORN, XNOR from Zbb

Acked-by: Alistair Francis Reviewed-by: Daniel Henrique Barboza Signed-off-by: Richard Henderson --- tcg/riscv/tcg-target-con-set.h | 1 + tcg/riscv/tcg-target-con-str.h | 1 + tcg/riscv/tcg-target.h | 12 +- tcg/riscv/tcg-target.c.inc | 41

Re: [PATCH 0/4] monitor/hmp: cleanup monitor_event() and suspend_cnt

Markus Armbruster writes: > Copying the HMP maintainer for another pair of eyes. Crossed Paolo's PR, so nevermind.

[PULL 13/23] disas/riscv: Decode czero.{eqz,nez}

Acked-by: Alistair Francis Reviewed-by: Daniel Henrique Barboza Signed-off-by: Richard Henderson --- disas/riscv.c | 6 ++ 1 file changed, 6 insertions(+) diff --git a/disas/riscv.c b/disas/riscv.c index e61bda5674..d597161d46 100644 --- a/disas/riscv.c +++ b/disas/riscv.c @@ -962,6 +962,8

[PULL 19/23] tcg/riscv: Support REV8 from Zbb

Acked-by: Alistair Francis Reviewed-by: Daniel Henrique Barboza Signed-off-by: Richard Henderson --- tcg/riscv/tcg-target.h | 10 +- tcg/riscv/tcg-target.c.inc | 29 + 2 files changed, 34 insertions(+), 5 deletions(-) diff --git a/tcg/riscv/tcg-target.h

[PULL 20/23] tcg/riscv: Support CPOP from Zbb

Acked-by: Alistair Francis Reviewed-by: Daniel Henrique Barboza Signed-off-by: Richard Henderson --- tcg/riscv/tcg-target.h | 4 ++-- tcg/riscv/tcg-target.c.inc | 9 + 2 files changed, 11 insertions(+), 2 deletions(-) diff --git a/tcg/riscv/tcg-target.h b/tcg/riscv/tcg-target.h ind

Re: [PATCH v1 1/2] vfio-user: update comments

On Thu, May 25, 2023 at 05:02:03PM +0200, Markus Armbruster wrote: > Jagannathan Raman writes: > > > Clarify the behavior of TYPE_VFU_OBJECT when TYPE_REMOTE_MACHINE enables > > the auto-shutdown property. Also, add notes to VFU_OBJECT_ERROR. > > > > Signed-off-by: Jagannathan Raman > > --- > >

Re: [PATCH v1 0/2] Fix the documentation for vfio-user and multi-process QEMU

On Wed, May 17, 2023 at 04:43:55PM +, Jagannathan Raman wrote: > This series addresses recent comments from Markus Armbruster in the > "Machine x-remote property auto-shutdown" email thread. > > Jagannathan Raman (2): > vfio-user: update comments > docs: fix multi-process QEMU documentatio

Re: [PATCH 01/12] block-coroutine-wrapper: Take AioContext lock in no_co_wrappers

On Thu, May 25, 2023 at 02:47:02PM +0200, Kevin Wolf wrote: > All of the functions that currently take a BlockDriverState, BdrvChild > or BlockBackend as their first parameter expect the associated > AioContext to be locked when they are called. In the case of > no_co_wrappers, they are called from

Re: [PATCH 02/12] block: Clarify locking rules for bdrv_open(_inherit)()

On Thu, May 25, 2023 at 02:47:03PM +0200, Kevin Wolf wrote: > These functions specify that the caller must hold the "@filename > AioContext lock". This doesn't make sense, file names don't have an > AioContext. New BlockDriverStates always start in the main AioContext, > so this is what we really n

Re: [PATCH 03/12] block: Take main AioContext lock when calling bdrv_open()

On Thu, May 25, 2023 at 02:47:04PM +0200, Kevin Wolf wrote: > The function documentation already says that all callers must hold the > main AioContext lock, but not all of them do. This can cause assertion > failures when functions called by bdrv_open() try to drop the lock. Fix > a few more caller

Re: io-qcow2 failures on zfs

Ping. On 5/19/23 15:44, Richard Henderson wrote: I'm doing some testing on one of the Linaro build machines and I reliably see Summary of Failures: 712/790 qemu:block / io-qcow2-150 ERROR    5.24s   exit status 1 777/790 qemu:block / io-qco

Re: [PATCH v3 1/1] block/blkio: use qemu_open() to support fd passing for virtio-blk

Stefan Hajnoczi writes: > On Wed, May 17, 2023 at 09:19:26AM +0200, Stefano Garzarella wrote: >> CCing Markus for some advice. >> >> On Tue, May 16, 2023 at 11:04:21AM -0500, Jonathon Jongsma wrote: [...] >> > I need some way to determine that the particular qemu binary can accept >> > a /dev/

Re: [RFC PATCH v1 0/9] Hypervisor-Enforced Kernel Integrity

On 5/25/2023 6:25 AM, Mickaël Salaün wrote: On 24/05/2023 23:04, Trilok Soni wrote: On 5/5/2023 8:20 AM, Mickaël Salaün wrote: Hi, This patch series is a proof-of-concept that implements new KVM features (extended page tracking, MBEC support, CR pinning) and defines a new API to protect gue

Re: [PATCH 04/12] block-backend: Fix blk_new_open() for iothreads

On Thu, May 25, 2023 at 02:47:05PM +0200, Kevin Wolf wrote: > This fixes blk_new_open() to not assume that bs is in the main context. > > In particular, the BlockBackend must be created with the right > AioContext because it will refuse to move to a different context > afterwards. (blk->allow_aio_

Re: [PATCH 05/12] mirror: Hold main AioContext lock for calling bdrv_open_backing_file()

On Thu, May 25, 2023 at 02:47:06PM +0200, Kevin Wolf wrote: > bdrv_open_backing_file() calls bdrv_open_inherit(), so all callers must > hold the main AioContext lock. > > Signed-off-by: Kevin Wolf > --- > block.c| 2 ++ > block/mirror.c | 6 ++ > 2 files changed, 8 insertions(+) Rev

Re: [PATCH 06/12] qcow2: Fix open with 'file' in iothread

On Thu, May 25, 2023 at 02:47:07PM +0200, Kevin Wolf wrote: > qcow2_open() doesn't work correctly when opening the 'file' child moves > bs to an iothread, for several reasons: > > - It uses BDRV_POLL_WHILE() to wait for the qcow2_open_entry() > coroutine, which involves dropping the AioContext l

Re: [PATCH] configure: unset harmful environment variables

Paolo Bonzini wrote: > Apart from CLICOLOR_FORCE and GREP_OPTIONS, there are other variables > that are listed in the Autoconf manual. While Autoconf neutralizes them > very early, and assumes it does not (yet) run in a shell that has "unset", > QEMU assumes that the user invoked configure under

Re: [PATCH 07/12] raw-format: Fix open with 'file' in iothread

On Thu, May 25, 2023 at 02:47:08PM +0200, Kevin Wolf wrote: > When opening the 'file' child moves bs to an iothread, we need to hold > the AioContext lock of it before we can call raw_apply_options() (and > more specifically, bdrv_getlength() inside of it). > > Signed-off-by: Kevin Wolf > --- >

Re: [PATCH 08/12] copy-before-write: Fix open with child in iothread

On Thu, May 25, 2023 at 02:47:09PM +0200, Kevin Wolf wrote: > The AioContext lock must not be held for bdrv_open_child(), but it is > necessary for the followig operations, in particular those using nested > event loops in coroutine wrappers. > > Temporarily dropping the main AioContext lock is no

Re: [PATCH 09/12] block: Take AioContext lock in bdrv_open_driver()

On Thu, May 25, 2023 at 02:47:10PM +0200, Kevin Wolf wrote: > bdrv_refresh_total_sectors() and bdrv_refresh_limits() expect to be > called under the AioContext lock of the node. Take the lock. > > Signed-off-by: Kevin Wolf > --- > block.c | 7 +++ > 1 file changed, 7 insertions(+) Reviewed-

Re: [PATCH 10/12] block: Fix AioContext locking in bdrv_insert_node()

On Thu, May 25, 2023 at 02:47:11PM +0200, Kevin Wolf wrote: > While calling bdrv_new_open_driver_opts(), the main AioContext lock must > be held, not the lock of the AioContext of the block subtree it will be > added to afterwards. > > Signed-off-by: Kevin Wolf > --- > block.c | 11 +++ >

Re: [PATCH 11/12] iotests: Make verify_virtio_scsi_pci_or_ccw() public

On Thu, May 25, 2023 at 02:47:12PM +0200, Kevin Wolf wrote: > It has no internal callers, so its only use is being called from > individual test cases. If the name starts with an underscore, it is > considered private and linters warn against calling it. 256 only gets > away with it currently becau

Re: [PATCH v3 1/1] block/blkio: use qemu_open() to support fd passing for virtio-blk

On 5/25/23 1:30 PM, Markus Armbruster wrote: Stefan Hajnoczi writes: On Wed, May 17, 2023 at 09:19:26AM +0200, Stefano Garzarella wrote: CCing Markus for some advice. On Tue, May 16, 2023 at 11:04:21AM -0500, Jonathon Jongsma wrote: [...] I need some way to determine that the particular

Re: [PATCH 12/12] iotests: Test blockdev-create in iothread

On Thu, May 25, 2023 at 02:47:13PM +0200, Kevin Wolf wrote: > If blockdev-create references an existing node in an iothread (e.g. as > it's 'file' child), then suddenly all of the image creation code must > run in that AioContext, too. Test that this actually works. > > Signed-off-by: Kevin Wolf

Re: [RFC PATCH v1 0/9] Hypervisor-Enforced Kernel Integrity

On Thu, 2023-05-25 at 09:07 -0700, Sean Christopherson wrote: > On Thu, May 25, 2023, Rick P Edgecombe wrote: > > I wonder if it might be a good idea to POC the guest side before > > settling on the KVM interface. Then you can also look at the whole > > thing and judge how much usage it would get f

Re: [PATCH v5 04/10] scripts/qapi: document the tool that generated the file

On Wed, May 24, 2023 at 02:39:46PM +0100, Alex Bennée wrote: > This makes it a little easier for developers to find where things > where being generated. > > Reviewed-by: Richard Henderson > Signed-off-by: Alex Bennée > Message-Id: <20230523125000.3674739-5-alex.ben...@linaro.org> > --- > scrip

Re: [PULL 00/23] tcg patch queue

gitlab.com/rth7680/qemu.git tags/pull-tcg-20230525 for you to fetch changes up to a30498fcea5a8b9c544324ccfb0186090104b229: tcg/riscv: Support CTZ, CLZ from Zbb (2023-05-25 15:29:36 +) tcg/mips: - Constant formation im

Re: [PATCH v3 1/1] hw/arm/aspeed:Add vpd data for Rainier machine

Hello Cedric, On 5/25/23 1:37 AM, Cédric Le Goater wrote: [ ... ] However, regarding Cédric's log above, a reboot is expected on the first boot of a fresh image when there's valid VPD available. For the first boot of a fresh image we configure the kernel with a minimal devicetree that allows

Re: [PATCH v2 06/27] mkvenv: add ensure subcommand

On Tue, May 16, 2023 at 6:59 AM Paolo Bonzini wrote: > > From: John Snow > > This command is to be used to add various packages (or ensure they're > already present) into the configure-provided venv in a modular fashion. > > Examples: > > mkvenv ensure --online --dir "${source_dir}/python/wheels/

Re: [PATCH] mkvenv: pass first missing package to diagnose()

On Fri, May 19, 2023 at 4:25 AM Paolo Bonzini wrote: > > If sphinx is present but the theme is not, mkvenv will print an > inaccurate diagnostic: > > ERROR: Could not find a version that satisfies the requirement > sphinx-rtd-theme>=0.5.0 (from versions: none) > ERROR: No matching distribution fo

Re: [PATCH 3/3] Makefile: remove $(TESTS_PYTHON)

On Thu, May 25, 2023 at 6:28 AM Paolo Bonzini wrote: > > It is now the same as $(PYTHON), since the latter always points at > pyvenv/bin/python3. Good point! > > Signed-off-by: Paolo Bonzini Reviewed-by: John Snow > --- > tests/Makefile.include| 8 +++- > tests/vm/Makefile.include

[PATCH 0/2] meson: Fix initrd-stress.img build

Just a small fix to the build of the initrd used by the migration guestperf.py script. $ cd build $ make tests/migration/initrd-stress.img <-- BROKEN $ ./tests/migration/guestperf.py --binary /path/to/qemu-system-x86_64 \ --initrd ./tests/migration/initrd-stress.img --debug Fabiano Rosas (2):

[PATCH 2/2] meson: Add static glib dependency for initrd-stress.img

We recently moved glib detection code to meson but the static libs were left out. Add a specific dependency for stress.c which is linked statically. $ make V=1 tests/migration/initrd-stress.img before: cc -m64 -mcx16 -o tests/migration/stress ... -static -Wl,--start-group /usr/lib64/libglib-2.0

[PATCH 1/2] meson: Remove leftover comment

Commit d2e6f9272d ("fuzz: remove fork-fuzzing scaffolding") removed the linker script and forgot to remove the comment. Signed-off-by: Fabiano Rosas --- meson.build | 2 -- 1 file changed, 2 deletions(-) diff --git a/meson.build b/meson.build index ef181ff2df..ba1b7012cd 100644 --- a/meson.buil

[RFC PATCH v2 2/5] virtio-balloon: device has Working Set Reporting

- working_set_vq to receive Working Set reports from guest - notification_vq to send config or request to guest - add working set as object property on device Signed-off-by: T.J. Alumbaugh --- hw/virtio/virtio-balloon.c | 164 - include/hw/virtio/virtio-bal

[RFC PATCH v2 5/5] virtio-balloon: Migration of working set config

Migrate working_set_num_bins through VMStateDescription. Signed-off-by: T.J. Alumbaugh --- hw/virtio/virtio-balloon.c | 12 1 file changed, 12 insertions(+) diff --git a/hw/virtio/virtio-balloon.c b/hw/virtio/virtio-balloon.c index a124d95534..6e1646abfd 100644 --- a/hw/virtio/virt

[RFC PATCH v2 1/5] virtio-balloon: Add Working Set Reporting feature

Balloon header includes: - feature bit for Working Set Reporting - number of Working Set bins member in balloon config - types for communicating Working Set information Signed-off-by: T.J. Alumbaugh --- .../standard-headers/linux/virtio_balloon.h | 20 +++ 1 file changed, 20

[RFC PATCH v2 3/5] virtio-balloon: Add QMP functions for Working Set

- Adds QMP function 'working-set-config' - Adds QMP function 'working-set-request' - Retrieve working set via 'guest-working-set' property on balloon >> cat script.py NAME = "name" SOCKET = 'vm.sock' BALLOON = "/machine/peripheral/balloon0" import json import asyncio from qemu.qmp import

[RFC PATCH v2 4/5] virtio-balloon: Add HMP functions for Working Set

- Adds 'working_set_request', 'working_set_config' HMP functions Start qemu with '-monitor telnet:127.0.0.1:,server=on,wait=off' >> telnet localhost (qemu) working_set_config 200 800 3000 750 1000 (qemu) working_set_request (qemu) qom-get /machine/peripheral/balloon0 guest-working-set {

[RFC PATCH v2 0/5] virtio-balloon: Working Set Reporting

This is the device implementation for the proposed expanded balloon feature described here: https://lore.kernel.org/linux-mm/20230509185419.1088297-1-yuan...@google.com/ This series has a fixed number of "bins" for the working set report, but this is not a constraint of the system. The bin number

Re: [RFC PATCH] softfloat: use QEMU_FLATTEN to avoid mistaken isra inlining

On Thu, 25 May 2023, Paolo Bonzini wrote: On 5/23/23 16:33, Richard Henderson wrote: The tests are poorly ordered, testing many unlikely things before the most likely thing (normal).  A better ordering would be     if (likely(tp##_is_normal(arg))) {     } else if (tp##_is_zero(arg)) {     }

Re: [RFC PATCH] softfloat: use QEMU_FLATTEN to avoid mistaken isra inlining

On Thu, 25 May 2023, Paolo Bonzini wrote: On 5/23/23 16:33, Richard Henderson wrote: The tests are poorly ordered, testing many unlikely things before the most likely thing (normal).  A better ordering would be     if (likely(tp##_is_normal(arg))) {     } else if (tp##_is_zero(arg)) {    

[PATCH v2 11/20] target/arm: Hoist finalize_memop out of do_fp_{ld, st}

We are going to need the complete memop beforehand, so let's not compute it twice. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/tcg/translate-a64.c | 43 ++ 1 file changed, 23 insertions(+), 20 deletions(-) diff --git a/target/arm/t

[PATCH v2 17/20] target/arm: Move mte check for store-exclusive

Push the mte check behind the exclusive_addr check. Document the several ways that we are still out of spec with this implementation. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/tcg/translate-a64.c | 42 +- 1 file changed, 36 insert

[PATCH v2 05/20] target/arm: Use tcg_gen_qemu_{st, ld}_i128 for do_fp_{st, ld}

While we don't require 16-byte atomicity here, using a single larger operation simplifies the code. Introduce finalize_memop_asimd for this. Signed-off-by: Richard Henderson --- target/arm/tcg/translate.h | 24 +++ target/arm/tcg/translate-a64.c | 35 +++-

[PATCH v2 12/20] target/arm: Pass memop to gen_mte_check1*

Pass the completed memop to gen_mte_check1_mmuidx. For the moment, do nothing more than extract the size. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/tcg/translate-a64.h | 2 +- target/arm/tcg/translate-a64.c | 82 ++ target/arm/tc

[PATCH v2 07/20] target/arm: Use tcg_gen_qemu_{ld, st}_i128 in gen_sve_{ld, st}r

Round len_align to 16 instead of 8, handling an odd 8-byte as part of the tail. Use MO_ATOM_NONE to indicate that all of these memory ops have only byte atomicity. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/tcg/translate-sve.c | 95 +-

[PATCH v2 01/20] target/arm: Add commentary for CPUARMState.exclusive_high

Document the meaning of exclusive_high in a big-endian context, and why we can't change it now. Signed-off-by: Richard Henderson --- target/arm/cpu.h | 7 +++ 1 file changed, 7 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index d469a2637b..4e16eab82e 100644 --- a/target/ar

[PATCH v2 02/20] target/arm: Add feature test for FEAT_LSE2

Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/cpu.h | 5 + 1 file changed, 5 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 4e16eab82e..36ab66d0c3 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3850,6 +3850,11 @@ static inline boo

[PATCH v2 00/20] target/arm: Implement FEAT_LSE2

v1: https://patchew.org/QEMU/20230216030854.1212208-1-richard.hender...@linaro.org/ All prerequisites are upstream. There are still outstanding patches to improve the atomic16 support, but those are all optimizations. Patches needing r-b: 01-target-arm-Add-commentary-for-CPUARMState.exclusi.p

[PATCH v2 13/20] target/arm: Pass single_memop to gen_mte_checkN

Pass the individual memop to gen_mte_checkN. For the moment, do nothing with it. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/tcg/translate-a64.h | 2 +- target/arm/tcg/translate-a64.c | 31 +++ target/arm/tcg/translate-sve.c | 4 ++--

[PATCH v2 08/20] target/arm: Sink gen_mte_check1 into load/store_exclusive

No need to duplicate this check across multiple call sites. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/tcg/translate-a64.c | 44 -- 1 file changed, 21 insertions(+), 23 deletions(-) diff --git a/target/arm/tcg/translate-a64.c b/ta

[PATCH v2 10/20] target/arm: Hoist finalize_memop out of do_gpr_{ld, st}

We are going to need the complete memop beforehand, so let's not compute it twice. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/tcg/translate-a64.c | 61 +++--- 1 file changed, 35 insertions(+), 26 deletions(-) diff --git a/target/arm/t

[PATCH v2 19/20] tests/tcg/multiarch: Adjust sigbus.c

With -cpu max and FEAT_LSE2, the __aarch64__ section will only raise an alignment exception when the load crosses a 16-byte boundary. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- tests/tcg/multiarch/sigbus.c | 13 + 1 file changed, 9 insertions(+), 4 deletions(-)

[PATCH v2 03/20] target/arm: Introduce finalize_memop_{atom,pair}

Let finalize_memop_atom be the new basic function, with finalize_memop and finalize_memop_pair testing FEAT_LSE2 to apply the appropriate atomicity. Signed-off-by: Richard Henderson --- target/arm/tcg/translate.h | 39 +- target/arm/tcg/translate-a64.c | 2 ++

[PATCH v2 16/20] target/arm: Relax ordered/atomic alignment checks for LSE2

FEAT_LSE2 only requires that atomic operations not cross a 16-byte boundary. Ordered operations may be completely unaligned if SCTLR.nAA is set. Because this alignment check is so special, do it by hand. Make sure not to keep TCG temps live across the branch. Signed-off-by: Richard Henderson --

[PATCH v2 06/20] target/arm: Use tcg_gen_qemu_st_i128 for STZG, STZ2G

This fixes a bug in that these two insns should have been using atomic 16-byte stores, since MTE is ARMv8.5 and LSE2 is mandatory from ARMv8.4. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/tcg/translate-a64.c | 17 ++--- 1 file changed, 10 insertions(+)

[PATCH v2 18/20] tests/tcg/aarch64: Use stz2g in mte-7.c

We have many other instances of stg in the testsuite; change these to provide an instance of stz2g. Signed-off-by: Richard Henderson --- tests/tcg/aarch64/mte-7.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/tests/tcg/aarch64/mte-7.c b/tests/tcg/aarch64/mte-7.c index a98

[PATCH v2 20/20] target/arm: Enable FEAT_LSE2 for -cpu max

Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- docs/system/arm/emulation.rst | 1 + target/arm/tcg/cpu64.c| 1 + 2 files changed, 2 insertions(+) diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst index 7338987875..ecbbd63adf 100644 --- a/docs/sy

[PATCH v2 15/20] target/arm: Add SCTLR.nAA to TBFLAG_A64

Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/cpu.h | 3 ++- target/arm/tcg/translate.h | 2 ++ target/arm/tcg/hflags.c| 6 ++ target/arm/tcg/translate-a64.c | 1 + 4 files changed, 11 insertions(+), 1 deletion(-) diff --git a/target/ar

[PATCH v2 04/20] target/arm: Use tcg_gen_qemu_ld_i128 for LDXP

While we don't require 16-byte atomicity here, using a single larger load simplifies the code, and makes it a closer match to STXP. Signed-off-by: Richard Henderson --- target/arm/tcg/translate-a64.c | 31 --- 1 file changed, 20 insertions(+), 11 deletions(-) diff --

[PATCH v2 09/20] target/arm: Load/store integer pair with one tcg operation

This is required for LSE2, where the pair must be treated atomically if it does not cross a 16-byte boundary. But it simplifies the code to do this always. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/tcg/translate-a64.c | 70 ++ 1

[PATCH v2 14/20] target/arm: Check alignment in helper_mte_check

Fixes a bug in that with SCTLR.A set, we should raise any alignment fault before raising any MTE check fault. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/internals.h | 3 ++- target/arm/tcg/mte_helper.c| 18 ++ target/arm/tcg/translate

[PATCH] accel/tcg: Fix check for page writeability in load_atomic16_or_exit

PAGE_WRITE is current writability, as modified by TB protection; PAGE_WRITE_ORG is the original page writability. Fixes: cdfac37be0d ("accel/tcg: Honor atomicity of loads") Signed-off-by: Richard Henderson --- accel/tcg/ldst_atomicity.c.inc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)

[PATCH v4 02/16] accel/tcg: Fix check for page writeability in load_atomic16_or_exit

PAGE_WRITE is current writability, as modified by TB protection; PAGE_WRITE_ORG is the original page writability. Fixes: cdfac37be0d ("accel/tcg: Honor atomicity of loads") Signed-off-by: Richard Henderson --- accel/tcg/ldst_atomicity.c.inc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)

[PATCH v4 06/16] tcg/aarch64: Rename temporaries

We will need to allocate a second general-purpose temporary. Rename the existing temps to add a distinguishing number. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target.c.inc | 50 ++-- 1 file changed, 25 insertions(+), 25 del

[PATCH v4 13/16] accel/tcg: Extract store_atom_insert_al16 to host header

Signed-off-by: Richard Henderson --- host/include/generic/host/store-insert-al16.h | 50 +++ accel/tcg/ldst_atomicity.c.inc| 40 +-- 2 files changed, 51 insertions(+), 39 deletions(-) create mode 100644 host/include/generic/host/store-insert-al16.h di

[PATCH v4 05/16] tcg/i386: Support 128-bit load/store

Signed-off-by: Richard Henderson --- tcg/i386/tcg-target.h | 4 +- tcg/i386/tcg-target.c.inc | 191 +- 2 files changed, 190 insertions(+), 5 deletions(-) diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h index 0106946996..b167f1e8d6 100644 --- a

[PATCH v4 14/16] accel/tcg: Add x86_64 load_atom_extract_al16_or_al8

Signed-off-by: Richard Henderson --- .../x86_64/host/load-extract-al16-al8.h | 50 +++ 1 file changed, 50 insertions(+) create mode 100644 host/include/x86_64/host/load-extract-al16-al8.h diff --git a/host/include/x86_64/host/load-extract-al16-al8.h b/host/include/x86_64/

Re: [PATCH v3 0/2] accel/tcg: Improvements to atomic128.h

On 5/24/23 11:32, Richard Henderson wrote: Changes for v3: * Most of the v2 patch set merged, except x86_64 atomic128-ldst.h, which failed testing with clang-11 with debian 11. * New patch to change __int128_t detection. * This in turn enabled CONFIG_ATOMIC128, which was not ideal

[PATCH v4 01/16] tcg: Fix register move type in tcg_out_ld_helper_ret

The first move was incorrectly using TCG_TYPE_I32 while the second move was correctly using TCG_TYPE_REG. This prevents a 64-bit host from moving all 128-bits of the return value. Fixes: ebebea53ef8 ("tcg: Support TCG_TYPE_I128 in tcg_out_{ld,st}_helper_{args,ret}") Signed-off-by: Richard Hender

[PATCH v4 03/16] meson: Split test for __int128_t type from __int128_t arithmetic

Older versions of clang have missing runtime functions for arithmetic with -fsanitize=undefined (see 464e3671f9d5c), so we cannot use __int128_t for implementing Int128. But __int128_t is present, data movement works, and can be use for atomic128. Probe for both CONFIG_INT128_TYPE and CONFIG_INT1

[PATCH v4 00/16] tcg: Improvements to atomic128

This is a merge of a couple of singleton fixes, CONFIG_ATOMIC128 detection, and tcg backend code generation patch sets, just to keep everything in one place. Tested with the Arm FEAT_LSE2 patch set, which greatly increases the number of 16-byte atomic operations. Patches needing review: 01-tcg-

[PATCH v4 04/16] qemu/atomic128: Add x86_64 atomic128-ldst.h

With CPUINFO_ATOMIC_VMOVDQA, we can perform proper atomic load/store without cmpxchg16b. Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- host/include/x86_64/host/atomic128-ldst.h | 68 +++ 1 file changed, 68 insertions(+) create mode 100644 host/include/x86_64

[PATCH v4 16/16] accel/tcg: Add aarch64 store_atom_insert_al16

Signed-off-by: Richard Henderson --- host/include/aarch64/host/store-insert-al16.h | 47 +++ 1 file changed, 47 insertions(+) create mode 100644 host/include/aarch64/host/store-insert-al16.h diff --git a/host/include/aarch64/host/store-insert-al16.h b/host/include/aarch64/host/

[PATCH v4 12/16] accel/tcg: Extract load_atom_extract_al16_or_al8 to host header

Signed-off-by: Richard Henderson --- .../generic/host/load-extract-al16-al8.h | 45 +++ accel/tcg/ldst_atomicity.c.inc| 36 +-- 2 files changed, 47 insertions(+), 34 deletions(-) create mode 100644 host/include/generic/host/load-extract-al16-al8.h

[PATCH v4 11/16] tcg/s390x: Support 128-bit load/store

Use LPQ/STPQ when 16-byte atomicity is required. Note that these instructions require 16-byte alignment. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- tcg/s390x/tcg-target-con-set.h | 2 + tcg/s390x/tcg-target.h | 2 +- tcg/s390x/tcg-target.c.inc | 103

Re: [PATCH] tcg: Fix register move type in tcg_out_ld_helper_ret

On 5/24/23 13:02, Richard Henderson wrote: The first move was incorrectly using TCG_TYPE_I32 while the second move was correctly using TCG_TYPE_REG. This prevents a 64-bit host from moving all 128-bits of the return value. Fixes: ebebea53ef8 ("tcg: Support TCG_TYPE_I128 in tcg_out_{ld,st}_help

Re: [PATCH] accel/tcg: Fix check for page writeability in load_atomic16_or_exit

On 5/25/23 16:51, Richard Henderson wrote: PAGE_WRITE is current writability, as modified by TB protection; PAGE_WRITE_ORG is the original page writability. Fixes: cdfac37be0d ("accel/tcg: Honor atomicity of loads") Signed-off-by: Richard Henderson --- accel/tcg/ldst_atomicity.c.inc | 2 +-

[PATCH v4 08/16] tcg/aarch64: Simplify constraints on qemu_ld/st

Adjust the softmmu tlb to use TMP[0-2], not any of the normally available registers. Since we handle overlap betwen inputs and helper arguments, we can allow any allocatable reg. Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target-con-set.h | 2 -- tcg/aarch64/tcg-target-con-str.h | 1

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