ble in the Git repository at:
https://gitlab.com/gaosong/qemu.git tags/pull-loongarch-20230505
for you to fetch changes up to 9dd207d409cc2eb08fe52965b9d1fd4a12a82bd5:
hw/intc: don't use target_ulong for LoongArch ipi (2023-05-05
Hi,
在 2023/5/5 下午9:24, WANG Xuerui 写道:
Hi,
On 2023/5/3 15:06, Richard Henderson wrote:
This should be true of all server class loongarch64.
And desktop-class (i.e. all Loongson-3 series).
Signed-off-by: Richard Henderson
---
tcg/loongarch64/tcg-target.c.inc | 6 ++
1 file changed, 6
Implement kvm_arch_init_vcpu interface for loongarch,
in this function, we register VM change state handler.
And when VM state changes to running, the counter value
should be put into kvm to keep consistent with kvm,
and when state change to stop, counter value should be
refreshed from kvm.
Signed
Define some functions in target/loongarch/kvm.c, such as
kvm_arch_put_registers, kvm_arch_get_registers and
kvm_arch_handle_exit, etc. which are needed by kvm/kvm-all.c.
Now the most functions has no content and they will be
implemented in the next patches.
Signed-off-by: Tianrui Zhao
Reviewed-by
Implement the kvm_arch_init of loongarch, in the function, the
KVM_CAP_MP_STATE cap is checked by kvm ioctl.
Signed-off-by: Tianrui Zhao
Reviewed-by: Richard Henderson
---
target/loongarch/kvm.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/loongarch/kvm.c b/target/loongarch/kvm.c
Supplement vcpu env initial when vcpu reset, including
init vcpu CSR_CPUID,CSR_TID to cpu->cpu_index. The two
regs will be used in kvm_get/set_csr_ioctl.
Signed-off-by: Tianrui Zhao
---
target/loongarch/cpu.c | 2 ++
target/loongarch/cpu.h | 1 +
2 files changed, 3 insertions(+)
diff --git a/ta
This series add loongarch kvm support, mainly implement
some interfaces used by kvm such as kvm_arch_get/set_regs,
kvm_arch_handle_exit, kvm_loongarch_set_interrupt, etc.
Currently, we are able to boot LoongArch KVM Linux Guests.
In loongarch VM, mmio devices and iocsr devices are emulated
in user
Implement kvm_arch_handle_exit for loongarch. In this
function, the KVM_EXIT_LOONGARCH_IOCSR is handled,
we read or write the iocsr address space by the addr,
length and is_write argument in kvm_run.
Signed-off-by: Tianrui Zhao
Reviewed-by: Richard Henderson
---
target/loongarch/kvm.c|
On Thu, 4 May 2023 12:14:47 +0200, =?utf-8?q?Eugenio_P=C3=A9rez?=
wrote:
> The commit 93a97dc5200a ("virtio-net: enable vq reset feature") enables
> unconditionally vq reset feature as long as the device is emulated.
> This makes impossible to actually disable the feature, and it causes
> migrat
Add kvm.c and kvm-stub.c into meson.build to compile
it when kvm is configed. Meanwhile in meson.build,
we set the kvm_targets to loongarch64-softmmu when
the cpu is loongarch.
Signed-off-by: Tianrui Zhao
Reviewed-by: Richard Henderson
---
meson.build | 2 ++
target/loongarch/m
Implement loongarch kvm set vcpu interrupt interface,
when a irq is set in vcpu, we use the KVM_INTERRUPT
ioctl to set intr into kvm.
Signed-off-by: Tianrui Zhao
---
target/loongarch/cpu.c | 18 +-
target/loongarch/kvm-stub.c | 11 +++
target/loongarch/kvm.
Implement kvm_arch_get/set_registers interfaces, many regs
can be get/set in the function, such as core regs, csr regs,
fpu regs, mp state, etc.
Signed-off-by: Tianrui Zhao
Reviewed-by: Richard Henderson
---
meson.build | 1 +
target/loongarch/cpu.c| 3 +
target/lo
This patch is only a placeholder now, which is used to
show some kvm structures and macros for reviewers.
And it will be replaced by using update-linux-headers.sh
when the linux loongarch kvm patches are accepted.
Signed-off-by: Tianrui Zhao
---
linux-headers/asm-loongarch/kvm.h | 99 +++
This patch includes:
- VADDA.{B/H/W/D}.
Reviewed-by: Richard Henderson
Signed-off-by: Song Gao
Message-Id: <20230504122810.4094787-13-gaos...@loongson.cn>
---
target/loongarch/disas.c| 5 ++
target/loongarch/helper.h | 5 ++
target/loongarch/insn_trans/tr
This patch includes:
- VSSRLRN.{B.H/H.W/W.D};
- VSSRARN.{B.H/H.W/W.D};
- VSSRLRN.{BU.H/HU.W/WU.D};
- VSSRARN.{BU.H/HU.W/WU.D};
- VSSRLRNI.{B.H/H.W/W.D/D.Q};
- VSSRARNI.{B.H/H.W/W.D/D.Q};
- VSSRLRNI.{BU.H/HU.W/WU.D/DU.Q};
- VSSRARNI.{BU.H/HU.W/WU.D/DU.Q}.
Reviewed-by: Richard Henderson
Signed-off-
This patch includes;
- VNEG.{B/H/W/D}.
Reviewed-by: Richard Henderson
Signed-off-by: Song Gao
Message-Id: <20230504122810.4094787-7-gaos...@loongson.cn>
---
target/loongarch/disas.c| 10 ++
target/loongarch/insn_trans/trans_lsx.c.inc | 20
target
The following changes since commit eb5c3932a383ba1ef3a911232c644f2e053ef66c:
Merge tag 'pw-pull-request' of https://gitlab.com/marcandre.lureau/qemu into
staging (2023-05-05 19:18:05 +0100)
are available in the Git repository at:
https://gitlab.com/gaosong/qemu.git tags/pull-loongarch-20230
This patch includes:
- VSRLRN.{B.H/H.W/W.D};
- VSRARN.{B.H/H.W/W.D};
- VSRLRNI.{B.H/H.W/W.D/D.Q};
- VSRARNI.{B.H/H.W/W.D/D.Q}.
Reviewed-by: Richard Henderson
Signed-off-by: Song Gao
Message-Id: <20230504122810.4094787-27-gaos...@loongson.cn>
---
target/loongarch/disas.c| 16
This patch includes:
- VADD.{B/H/W/D/Q};
- VSUB.{B/H/W/D/Q}.
Reviewed-by: Richard Henderson
Signed-off-by: Song Gao
Message-Id: <20230504122810.4094787-5-gaos...@loongson.cn>
---
target/loongarch/disas.c| 23 +++
target/loongarch/insn_trans/trans_lsx.c.inc | 69 +
This patch includes:
- VSEQ[I].{B/H/W/D};
- VSLE[I].{B/H/W/D}[U];
- VSLT[I].{B/H/W/D/}[U].
Reviewed-by: Richard Henderson
Signed-off-by: Song Gao
Message-Id: <20230504122810.4094787-36-gaos...@loongson.cn>
---
target/loongarch/disas.c| 43 +
target/loongarch/helper.h
This patch includes:
- VADDI.{B/H/W/D}U;
- VSUBI.{B/H/W/D}U.
Reviewed-by: Richard Henderson
Signed-off-by: Song Gao
Message-Id: <20230504122810.4094787-6-gaos...@loongson.cn>
---
target/loongarch/disas.c| 14
target/loongarch/insn_trans/trans_lsx.c.inc | 37
This patch includes:
- VFRSTP[I].{B/H}.
Acked-by: Richard Henderson
Signed-off-by: Song Gao
Message-Id: <20230504122810.4094787-33-gaos...@loongson.cn>
---
target/loongarch/disas.c| 5 +++
target/loongarch/helper.h | 5 +++
target/loongarch/insn_trans/tra
This patch includes:
- VSRLR[I].{B/H/W/D};
- VSRAR[I].{B/H/W/D}.
Reviewed-by: Richard Henderson
Signed-off-by: Song Gao
Message-Id: <20230504122810.4094787-25-gaos...@loongson.cn>
---
target/loongarch/disas.c| 18
target/loongarch/helper.h | 18
This patch includes:
- VLDI.
Reviewed-by: Richard Henderson
Signed-off-by: Song Gao
Message-Id: <20230504122810.4094787-43-gaos...@loongson.cn>
---
target/loongarch/disas.c| 7 +
target/loongarch/insn_trans/trans_lsx.c.inc | 137
target/loongarch/insns
This patch includes:
- VDIV.{B/H/W/D}[U];
- VMOD.{B/H/W/D}[U].
Reviewed-by: Richard Henderson
Signed-off-by: Song Gao
Message-Id: <20230504122810.4094787-17-gaos...@loongson.cn>
---
target/loongarch/disas.c| 17 ++
target/loongarch/helper.h | 17 +++
This patch includes:
- VSIGNCOV.{B/H/W/D}.
Reviewed-by: Richard Henderson
Signed-off-by: Song Gao
Message-Id: <20230504122810.4094787-20-gaos...@loongson.cn>
---
target/loongarch/disas.c| 5 ++
target/loongarch/helper.h | 5 ++
target/loongarch/insn_trans
This patch includes:
- VF{ADD/SUB/MUL/DIV}.{S/D};
- VF{MADD/MSUB/NMADD/NMSUB}.{S/D};
- VF{MAX/MIN}.{S/D};
- VF{MAXA/MINA}.{S/D};
- VFLOGB.{S/D};
- VFCLASS.{S/D};
- VF{SQRT/RECIP/RSQRT}.{S/D}.
Reviewed-by: Richard Henderson
Signed-off-by: Song Gao
Message-Id: <20230504122810.4094787-34-gaos...@lo
Reviewed-by: Richard Henderson
Signed-off-by: Song Gao
Message-Id: <20230504122810.4094787-2-gaos...@loongson.cn>
---
linux-user/loongarch64/signal.c | 4 +-
target/loongarch/cpu.c | 2 +-
target/loongarch/cpu.h | 21 -
target/loongarch/gdbstub.c | 4 +-
target/
This patch includes:
- VSAT.{B/H/W/D}[U].
Reviewed-by: Richard Henderson
Signed-off-by: Song Gao
Message-Id: <20230504122810.4094787-18-gaos...@loongson.cn>
---
target/loongarch/disas.c| 9 ++
target/loongarch/helper.h | 9 ++
target/loongarch/insn_tran
This patch includes:
- VPCNT.{B/H/W/D}.
Reviewed-by: Richard Henderson
Signed-off-by: Song Gao
Message-Id: <20230504122810.4094787-31-gaos...@loongson.cn>
---
target/loongarch/disas.c| 5 +
target/loongarch/helper.h | 5 +
target/loongarch/insn_tr
This patch includes:
- VABSD.{B/H/W/D}[U].
Reviewed-by: Richard Henderson
Signed-off-by: Song Gao
Message-Id: <20230504122810.4094787-12-gaos...@loongson.cn>
---
target/loongarch/disas.c| 9 ++
target/loongarch/helper.h | 9 ++
target/loongarch/insn_trans
This patch includes:
- VREPLVE[I].{B/H/W/D};
- VBSLL.V, VBSRL.V;
- VPACK{EV/OD}.{B/H/W/D};
- VPICK{EV/OD}.{B/H/W/D}.
Reviewed-by: Richard Henderson
Signed-off-by: Song Gao
Message-Id: <20230504122810.4094787-40-gaos...@loongson.cn>
---
target/loongarch/disas.c| 35 +
ta
This patch includes:
- VSLLWIL.{H.B/W.H/D.W};
- VSLLWIL.{HU.BU/WU.HU/DU.WU};
- VEXTL.Q.D, VEXTL.QU.DU.
Reviewed-by: Richard Henderson
Signed-off-by: Song Gao
Message-Id: <20230504122810.4094787-24-gaos...@loongson.cn>
---
target/loongarch/disas.c| 9 +
target/loongarch/
Reviewed-by: Richard Henderson
Signed-off-by: Song Gao
Message-Id: <20230504122810.4094787-3-gaos...@loongson.cn>
---
target/loongarch/insn_trans/trans_lsx.c.inc | 5 +
target/loongarch/lsx_helper.c | 6 ++
target/loongarch/meson.build| 1 +
target/loongarch
This patch includes:
- VMADD.{B/H/W/D};
- VMSUB.{B/H/W/D};
- VMADDW{EV/OD}.{H.B/W.H/D.W/Q.D}[U];
- VMADDW{EV/OD}.{H.BU.B/W.HU.H/D.WU.W/Q.DU.D}.
Reviewed-by: Richard Henderson
Signed-off-by: Song Gao
Message-Id: <20230504122810.4094787-16-gaos...@loongson.cn>
---
target/loongarch/disas.c
This patch includes:
- VSADD.{B/H/W/D}[U];
- VSSUB.{B/H/W/D}[U].
Reviewed-by: Richard Henderson
Signed-off-by: Song Gao
Message-Id: <20230504122810.4094787-8-gaos...@loongson.cn>
---
target/loongarch/disas.c| 17 +
target/loongarch/insn_trans/trans_lsx.c.inc
This patch includes:
- VMAX[I].{B/H/W/D}[U];
- VMIN[I].{B/H/W/D}[U].
Reviewed-by: Richard Henderson
Signed-off-by: Song Gao
Message-Id: <20230504122810.4094787-14-gaos...@loongson.cn>
---
target/loongarch/disas.c| 33
target/loongarch/helper.h | 18 +
This patch includes:
- VBITSEL.V;
- VBITSELI.B;
- VSET{EQZ/NEZ}.V;
- VSETANYEQZ.{B/H/W/D};
- VSETALLNEZ.{B/H/W/D}.
Reviewed-by: Richard Henderson
Signed-off-by: Song Gao
Message-Id: <20230504122810.4094787-38-gaos...@loongson.cn>
---
target/loongarch/disas.c| 20 ++
targ
This patch includes:
- VSSRLN.{B.H/H.W/W.D};
- VSSRAN.{B.H/H.W/W.D};
- VSSRLN.{BU.H/HU.W/WU.D};
- VSSRAN.{BU.H/HU.W/WU.D};
- VSSRLNI.{B.H/H.W/W.D/D.Q};
- VSSRANI.{B.H/H.W/W.D/D.Q};
- VSSRLNI.{BU.H/HU.W/WU.D/DU.Q};
- VSSRANI.{BU.H/HU.W/WU.D/DU.Q}.
Reviewed-by: Richard Henderson
Signed-off-by: Song
This patch includes:
- VILV{L/H}.{B/H/W/D};
- VSHUF.{B/H/W/D};
- VSHUF4I.{B/H/W/D};
- VPERMI.W;
- VEXTRINS.{B/H/W/D}.
Reviewed-by: Richard Henderson
Signed-off-by: Song Gao
Message-Id: <20230504122810.4094787-41-gaos...@loongson.cn>
---
target/loongarch/disas.c| 25
ta
From: Alex Bennée
The calling function is already working with hwaddr and uint64_t so
lets avoid bringing target_ulong in if we don't need to.
Signed-off-by: Alex Bennée
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Song Gao
Message-Id: <20230404132711.2563638-1-alex.ben...@linaro.org>
Sig
This patch includes:
- VEXTH.{H.B/W.H/D.W/Q.D};
- VEXTH.{HU.BU/WU.HU/DU.WU/QU.DU}.
Reviewed-by: Richard Henderson
Signed-off-by: Song Gao
Message-Id: <20230504122810.4094787-19-gaos...@loongson.cn>
---
target/loongarch/disas.c| 9 ++
target/loongarch/helper.h
This patch includes:
- VCLO.{B/H/W/D};
- VCLZ.{B/H/W/D}.
Reviewed-by: Richard Henderson
Signed-off-by: Song Gao
Message-Id: <20230504122810.4094787-30-gaos...@loongson.cn>
---
target/loongarch/disas.c| 9 ++
target/loongarch/helper.h | 9 ++
targe
Reviewed-by: Richard Henderson
Signed-off-by: Song Gao
Message-Id: <20230504122810.4094787-4-gaos...@loongson.cn>
---
target/loongarch/cpu.c | 2 ++
target/loongarch/cpu.h | 2 ++
target/loongarch/insn_trans/trans_lsx.c.inc | 11 +++
3 files ch
This patch includes:
- VINSGR2VR.{B/H/W/D};
- VPICKVE2GR.{B/H/W/D}[U];
- VREPLGR2VR.{B/H/W/D}.
Reviewed-by: Richard Henderson
Signed-off-by: Song Gao
Message-Id: <20230504122810.4094787-39-gaos...@loongson.cn>
---
target/loongarch/disas.c| 33 ++
target/loongarch/insn_t
This patch includes:
- VSLL[I].{B/H/W/D};
- VSRL[I].{B/H/W/D};
- VSRA[I].{B/H/W/D};
- VROTR[I].{B/H/W/D}.
Reviewed-by: Richard Henderson
Signed-off-by: Song Gao
Message-Id: <20230504122810.4094787-23-gaos...@loongson.cn>
---
target/loongarch/disas.c| 36 +
This patch includes:
- VLD[X], VST[X];
- VLDREPL.{B/H/W/D};
- VSTELM.{B/H/W/D}.
Reviewed-by: Richard Henderson
Signed-off-by: Song Gao
Message-Id: <20230504122810.4094787-42-gaos...@loongson.cn>
---
target/loongarch/disas.c| 34 +
target/loongarch/insn_trans/trans_lsx.c
Reviewed-by: Richard Henderson
Signed-off-by: Song Gao
Message-Id: <20230504122810.4094787-45-gaos...@loongson.cn>
---
target/loongarch/cpu.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c
index 55d7f9255e..c0afc21b2f 100644
--- a/target/loong
This patch includes:
- VBITCLR[I].{B/H/W/D};
- VBITSET[I].{B/H/W/D};
- VBITREV[I].{B/H/W/D}.
Reviewed-by: Richard Henderson
Signed-off-by: Song Gao
Message-Id: <20230504122810.4094787-32-gaos...@loongson.cn>
---
target/loongarch/disas.c| 25 ++
target/loongarch/helper.h
This patch includes:
- VSRLN.{B.H/H.W/W.D};
- VSRAN.{B.H/H.W/W.D};
- VSRLNI.{B.H/H.W/W.D/D.Q};
- VSRANI.{B.H/H.W/W.D/D.Q}.
Reviewed-by: Richard Henderson
Signed-off-by: Song Gao
Message-Id: <20230504122810.4094787-26-gaos...@loongson.cn>
---
target/loongarch/disas.c| 16 +++
This patch includes:
- VFCVT{L/H}.{S.H/D.S};
- VFCVT.{H.S/S.D};
- VFRINT[{RNE/RZ/RP/RM}].{S/D};
- VFTINT[{RNE/RZ/RP/RM}].{W.S/L.D};
- VFTINT[RZ].{WU.S/LU.D};
- VFTINT[{RNE/RZ/RP/RM}].W.D;
- VFTINT[{RNE/RZ/RP/RM}]{L/H}.L.S;
- VFFINT.{S.W/D.L}[U];
- VFFINT.S.L, VFFINT{L/H}.D.W.
Reviewed-by: Richard
This patch includes:
- VAVG.{B/H/W/D}[U];
- VAVGR.{B/H/W/D}[U].
Reviewed-by: Richard Henderson
Signed-off-by: Song Gao
Message-Id: <20230504122810.4094787-11-gaos...@loongson.cn>
---
target/loongarch/disas.c| 17 ++
target/loongarch/helper.h | 18 ++
targ
This patch includes:
- VFCMP.cond.{S/D}.
Reviewed-by: Richard Henderson
Signed-off-by: Song Gao
Message-Id: <20230504122810.4094787-37-gaos...@loongson.cn>
---
target/loongarch/disas.c| 94 +
target/loongarch/helper.h | 5 ++
target/loo
This patch includes:
- VMUL.{B/H/W/D};
- VMUH.{B/H/W/D}[U];
- VMULW{EV/OD}.{H.B/W.H/D.W/Q.D}[U];
- VMULW{EV/OD}.{H.BU.B/W.HU.H/D.WU.W/Q.DU.D}.
Reviewed-by: Richard Henderson
Signed-off-by: Song Gao
Message-Id: <20230504122810.4094787-15-gaos...@loongson.cn>
---
target/loongarch/disas.c
This patch includes:
- V{AND/OR/XOR/NOR/ANDN/ORN}.V;
- V{AND/OR/XOR/NOR}I.B.
Reviewed-by: Richard Henderson
Signed-off-by: Song Gao
Message-Id: <20230504122810.4094787-22-gaos...@loongson.cn>
---
target/loongarch/disas.c| 12 +
target/loongarch/helper.h
This patch includes:
- VADDW{EV/OD}.{H.B/W.H/D.W/Q.D}[U];
- VSUBW{EV/OD}.{H.B/W.H/D.W/Q.D}[U];
- VADDW{EV/OD}.{H.BU.B/W.HU.H/D.WU.W/Q.DU.D}.
Reviewed-by: Richard Henderson
Signed-off-by: Song Gao
Message-Id: <20230504122810.4094787-10-gaos...@loongson.cn>
---
target/loongarch/disas.c
Introduce set_fpr() and get_fpr() and remove cpu_fpr.
Reviewed-by: Richard Henderson
Signed-off-by: Song Gao
Message-Id: <20230504122810.4094787-44-gaos...@loongson.cn>
---
.../loongarch/insn_trans/trans_farith.c.inc | 72 +++
target/loongarch/insn_trans/trans_fcmp.c.inc | 12
This patch includes:
- VHADDW.{H.B/W.H/D.W/Q.D/HU.BU/WU.HU/DU.WU/QU.DU};
- VHSUBW.{H.B/W.H/D.W/Q.D/HU.BU/WU.HU/DU.WU/QU.DU}.
Reviewed-by: Richard Henderson
Signed-off-by: Song Gao
Message-Id: <20230504122810.4094787-9-gaos...@loongson.cn>
---
target/loongarch/disas.c| 17 +++
This patch includes:
- VMSKLTZ.{B/H/W/D};
- VMSKGEZ.B;
- VMSKNZ.B.
Reviewed-by: Richard Henderson
Signed-off-by: Song Gao
Message-Id: <20230504122810.4094787-21-gaos...@loongson.cn>
---
target/loongarch/disas.c| 7 ++
target/loongarch/helper.h | 7 ++
t
The following commits changed the code such that the fallback to MFSS for
MFFSCRN,
MFFSCRNI, MFFSCE and MFFSL on pre 3.0 ISAs was removed and became an illegal
instruction:
bf8adfd88b547680aa857c46098f3a1e94373160 - target/ppc: Move mffscrn[i] to
decodetree
394c2e2fda70da722f20fb60412d6c0ca
When the size of the physical address space is known (PhysBits is not
zero) move the 64bit pci io window to the end of the address space.
Signed-off-by: Gerd Hoffmann
---
src/fw/pciinit.c | 8
1 file changed, 8 insertions(+)
diff --git a/src/fw/pciinit.c b/src/fw/pciinit.c
index badf13
v3 changes:
- rename variables, use u8 for CPULongMode.
v2 changes:
- e820 conflict fix
Gerd Hoffmann (6):
better kvm detection
detect physical address space size
move 64bit pci window to end of address space
be less conservative with the 64bit pci io window
qemu: log reservations in f
In case kvm emulates features of another hypervisor (for example hyperv)
two VMM CPUID blocks will be present, one for the emulated hypervisor
and one for kvm itself.
This patch makes seabios loop over the VMM CPUID blocks to make sure it
will properly detect kvm when multiple blocks are present.
With loglevel 1 (same we use for RAM entries),
so it is included in the firmware log by default.
Signed-off-by: Gerd Hoffmann
---
src/fw/paravirt.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/fw/paravirt.c b/src/fw/paravirt.c
index fc308bf1ef1d..02351b24caea 100644
--
Add support to check for overlaps with e820 entries.
In case the 64bit pci io window has conflicts move it down.
The only known case where this happens is AMD processors
with 1TB address space which has some space just below
1TB reserved for HT.
Signed-off-by: Gerd Hoffmann
---
src/e820map.h
Check for pae and long mode using cpuid. If present also read the
physical address bits. Apply some qemu sanity checks (see below).
Record results in PhysBits and LongMode variables. In case we are not
sure what the address space size is leave the PhysBits variable unset.
On qemu we have the pr
Current seabios code will only enable and use the 64bit pci io window in
case it runs out of space in the 32bit pci mmio window below 4G.
This patch will also enable the 64bit pci io window when
(a) RAM above 4G is present, and
(b) the physical address space size is known, and
(c) seabios is
On Thu, May 04, 2023 at 07:22:25PM +0200, Juan Quintela wrote:
> Daniel P. Berrangé wrote:
> > On Thu, May 04, 2023 at 01:38:41PM +0200, Juan Quintela wrote:
> >> That is the moment we know we have transferred something.
> >>
> >> Signed-off-by: Juan Quintela
> >> ---
> >> migration/qemu-file.c
Simply fix the #vcpus_count to @vcpus_count in CPUArchId comments. Since
we are at here, resort the parameters in comments to match the sequence
of parameters which defined in the CPUArchId.
Signed-off-by: Shaoqin Huang
---
include/hw/boards.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletio
> -Original Message-
> From: Lukas Straub
> Sent: Friday, May 5, 2023 6:46 AM
> To: Vladimir Sementsov-Ogievskiy
> Cc: qemu-devel@nongnu.org; quint...@redhat.com; Zhang, Chen
> ; Peter Xu ; Leonardo Bras
>
> Subject: Re: [PATCH v4 10/10] migration: block incoming colo when capability
> -Original Message-
> From: Vladimir Sementsov-Ogievskiy
> Sent: Saturday, April 29, 2023 3:49 AM
> To: qemu-devel@nongnu.org
> Cc: lukasstra...@web.de; quint...@redhat.com; Zhang, Chen
> ; vsement...@yandex-team.ru
> Subject: [PATCH v4 00/10] COLO: improve build options
>
> v4:
> 01:
On 04/05/2023 23.19, Daniel Henrique Barboza wrote:
On 5/4/23 15:05, Thomas Huth wrote:
When building QEMU with "--without-default-devices", the pseries
machine fails to start even when running with the --nodefaults option:
$ ./qemu-system-ppc64 --nodefaults -M pseries
Type 'spapr-nvdimm'
On 5/4/23 15:01, Fabiano Rosas wrote:
...
# This config exists just so we can make SEMIHOSTING default when TCG
# is selected without also changing it for other architectures.
config ARM_SEMIHOSTING
bool
default y if TCG && ARM
select ARM_COMPATIBLE_SEMIHOSTING
This can be replac
On 5/4/23 10:56, Konstantin Kostiuk wrote:
From: Kostiantyn Kostiuk
The following changes since commit 044f8cf70a2fdf3b9e4c4d849c66e7855d2c446a:
Merge tag 'migration-20230428-pull-request' of
https://gitlab.com/juan.quintela/qemu into staging (2023-05-03 10:29:30 +0100)
are available in
On 05.05.23 10:56, Zhang, Chen wrote:
-Original Message-
From: Vladimir Sementsov-Ogievskiy
Sent: Saturday, April 29, 2023 3:49 AM
To:qemu-devel@nongnu.org
Cc:lukasstra...@web.de;quint...@redhat.com; Zhang, Chen
;vsement...@yandex-team.ru
Subject: [PATCH v4 00/10] COLO: improve build op
On 5/4/23 15:45, Peter Maydell wrote:
We have two target architectures which don't have Coverity components
defined for them: xtensa and openrisc. Add them.
Signed-off-by: Peter Maydell
---
As usual with coverity components, these will need to be added
manually via the scanner UI, since it has
On 5/4/23 10:13, Thomas Huth wrote:
Commit cf60ccc330 ("cutils: Introduce bundle mechanism") abandoned
compatibility with Windows older than 8 - we should reflect this
in our _WIN32_WINNT and set it to the value that corresponds to
Windows 8.
Signed-off-by: Thomas Huth
---
include/qemu/osdep.
On 5/4/23 22:42, Alex Williamson wrote:
The PCI Resizable BAR (ReBAR) capability is currently hidden from the
VM because the protocol for interacting with the capability does not
support a mechanism for the device to reject an advertised supported
BAR size. However, when assigned to a VM, the ac
On 5/4/23 22:53, Babu Moger wrote:
Add the following feature bits.
no-nested-data-bp : Processor ignores nested data breakpoints.
This bit is useless, unfortunately. Another similar bit include the one
about availability of FCS/FDS in the x87 save state.
They say that something is _
Queued, thanks.
Paolo
On 04.05.23 23:14, Stefan Hajnoczi wrote:
On Thu, 4 May 2023 at 13:39, Hanna Czenczek wrote:
On 11.04.23 17:05, Hanna Czenczek wrote:
[...]
Hanna Czenczek (4):
vhost: Re-enable vrings after setting features
vhost-user: Interface for migration state transfer
vhost: Add high-level
On Wed, 3 May 2023 at 08:11, Richard Henderson
wrote:
>
> This header is supposed to be private to tcg and in fact
> does not need to be included here at all.
>
> Reviewed-by: Song Gao
> Signed-off-by: Richard Henderson
Reviewed-by: Peter Maydell
thanks
-- PMM
On Wed, 3 May 2023 at 08:11, Richard Henderson
wrote:
>
> Signed-off-by: Richard Henderson
> ---
> accel/tcg/cputlb.c | 103 +++
> accel/tcg/user-exec.c | 12 +-
> accel/tcg/ldst_atomicity.c.inc | 491 +
> 3 files changed, 540 insertions(
Store the bytes in descending order on big-endian.
Invert the logic in the multi-byte signed tests on big-endian.
Make the checks in the multi-byte signed tests stricter.
Signed-off-by: Ilya Leoshkevich
---
tests/tcg/multiarch/system/memory.c | 64 +++--
1 file changed, 4
Multiarch tests are written in C and need support for printing
characters. Instead of implementing the runtime from scratch, just
reuse the pc-bios/s390-ccw one.
Run tests with -nographic in order to enable SCLP (enable this for
the existing tests as well, since it does not hurt).
Use the default
On 5/4/23 13:03, Nina Schoetterl-Glausch wrote:
On Tue, 2023-04-25 at 18:14 +0200, Pierre Morel wrote:
When the host supports the CPU topology facility, the PTF
instruction with function code 2 is interpreted by the SIE,
provided that the userland hypervisor activates the interpretation
by usi
v3: https://lists.gnu.org/archive/html/qemu-devel/2023-04/msg04756.html
v3 -> v4: Trivial rebase on top of Alex's series.
v2: https://lists.gnu.org/archive/html/qemu-devel/2023-04/msg04154.html
v2 -> v3: The idea with sharing the QEMU headers with the tests seems
to be controversial. Jus
Hi,
I noticed that the bdrv_graph_co_rd_lock() and bdrv_graph_co_rd_unlock()
functions use qemu_in_main_thread() as a conditional to return early.
What high-level requirements ensure that qemu_in_main_thread() will
evaluate to the same value during locking and unlocking?
This paragraph assumes no
On Wed, 3 May 2023 at 08:15, Richard Henderson
wrote:
>
> With the current structure of cputlb.c, there is no difference
> between the little-endian and big-endian entry points, aside
> from the assert. Unify the pairs of functions.
>
> Hoist the qemu_{ld,st}_helpers arrays to tcg.c.
>
> Reviewed
On Wed, 3 May 2023 at 08:23, Richard Henderson
wrote:
>
> TCG backends may need to defer to a helper to implement
> the atomicity required by a given operation. Mirror the
> interface used in system mode.
>
> Signed-off-by: Richard Henderson
> ---
> include/tcg/tcg-ldst.h | 6 +-
> accel/tcg/
On Wed, 3 May 2023 at 08:08, Richard Henderson
wrote:
>
> We can now fold these two pieces of code.
>
> Signed-off-by: Richard Henderson
Reviewed-by: Peter Maydell
thanks
-- PMM
(By the way, thanks for the explanations :))
On 05.05.23 11:03, Hanna Czenczek wrote:
On 04.05.23 23:14, Stefan Hajnoczi wrote:
[...]
I think it's better to change QEMU's vhost code
to leave stateful devices suspended (but not reset) across
vhost_dev_stop() -> vhost_dev_start(), maybe by int
On Fri, May 5, 2023 at 11:03 AM Hanna Czenczek wrote:
>
> On 04.05.23 23:14, Stefan Hajnoczi wrote:
> > On Thu, 4 May 2023 at 13:39, Hanna Czenczek wrote:
> >> On 11.04.23 17:05, Hanna Czenczek wrote:
> >>
> >> [...]
> >>
> >>> Hanna Czenczek (4):
> >>> vhost: Re-enable vrings after setting f
On Wed, 3 May 2023 at 08:17, Richard Henderson
wrote:
>
> Signed-off-by: Richard Henderson
> ---
> +/**
> + * load_atom_16:
> + * @p: host address
> + * @memop: the full memory op
> + *
> + * Load 16 bytes from @p, honoring the atomicity of @memop.
> + */
> +static Int128 load_atom_16(CPUArchS
Hi Jason,
as this is a Xen specific change, I would like Stefano or another Xen
developer to take a look at it, just few things from my side ...
On Tuesday, May 2, 2023 4:37:22 PM CEST Jason Andryuk wrote:
> xen_9pfs_free can't use gnttabdev since it is already closed and NULL-ed
Where exactly d
On 5/3/23 06:09, Nicholas Piggin wrote:
Fix missing env->ca restore when going from L2 back to the host.
Fixes: 120f738a467 ("spapr: implement nested-hv capability for the virtual
hypervisor")
Signed-off-by: Nicholas Piggin
---
hw/ppc/spapr_hcall.c | 1 +
1 file changed, 1 insertion(+)
d
On Wed, 3 May 2023 at 08:29, Richard Henderson
wrote:
>
> There is an edge condition prior to gcc13 for which optimization
> is required to generate 16-byte atomic sequences. Detect this.
>
> Signed-off-by: Richard Henderson
> ---
> accel/tcg/ldst_atomicity.c.inc | 38 ++---
On Wed, 3 May 2023 at 08:10, Richard Henderson
wrote:
>
> Notice when Intel or AMD have guaranteed that vmovdqa is atomic.
> The new variable will also be used in generated code.
>
> Signed-off-by: Richard Henderson
> ---
> include/qemu/cpuid.h | 18 ++
> tcg/i386/tcg-target
On 2023/5/3 15:06, Richard Henderson wrote:
The system is required to emulate unaligned accesses, even if the
hardware does not support it. The resulting trap may or may not
be more efficient than the qemu slow path. There are linux kernel
patches in flight to allow userspace to query hardwar
On Wed, 3 May 2023 at 08:08, Richard Henderson
wrote:
>
> Hosts using Intel and AMD AVX cpus are quite common.
> Add fast paths through ldst_atomicity using this.
>
> Only enable with CONFIG_INT128; some older clang versions do not
> support __int128_t, and the inline assembly won't work on struct
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