Re: [PATCH v3 3/4] target/riscv: check smstateen fcsr flag

On 2023/4/29 00:52, Mayuresh Chitale wrote: If misa.F and smstateen_fcsr_ok flag are clear then all the floating point instructions must generate an appropriate exception. Signed-off-by: Mayuresh Chitale --- target/riscv/insn_trans/trans_rvd.c.inc | 13 ++--- target/riscv/insn_trans/

Re: [PATCH v3 01/19] target/riscv: Refactor some of the generic vector functionality

On 2023/4/28 22:47, Lawrence Hunter wrote: From: Kiran Ostrolenk Take some functions/macros out of `vector_helper` and put them in a new module called `vector_internals`. This ensures they can be used by both vector and vector-crypto helpers (latter implemented in proceeding commits). Signed

Re: [PATCH v3 02/19] target/riscv: Refactor vector-vector translation macro

On 2023/4/28 22:47, Lawrence Hunter wrote: From: Kiran Ostrolenk Refactor the non SEW-specific stuff out of `GEN_OPIVV_TRANS` into function `opivv_trans` (similar to `opivi_trans`). `opivv_trans` will be used in proceeding vector-crypto commits. Signed-off-by: Kiran Ostrolenk Reviewed-by: R

Re: [PATCH v3 03/19] target/riscv: Remove redundant "cpu_vl == 0" checks

On 2023/4/28 22:47, Lawrence Hunter wrote: From: Nazar Kazakov Remove the redundant "vl == 0" check which is already included within the vstart >= vl check, when vl == 0. Signed-off-by: Nazar Kazakov --- Reviewed-by: Weiwei Li Weiwei Li target/riscv/insn_trans/trans_rvv.c.inc | 31 +

Re: [PATCH v3 04/19] target/riscv: Add Zvbc ISA extension support

On 2023/4/28 22:47, Lawrence Hunter wrote: This commit adds support for the Zvbc vector-crypto extension, which consists of the following instructions: * vclmulh.[vx,vv] * vclmul.[vx,vv] Translation functions are defined in `target/riscv/insn_trans/trans_rvvk.c.inc` and helpers are defined in

Re: [PATCH v3 05/19] target/riscv: Move vector translation checks

On 2023/4/28 22:47, Lawrence Hunter wrote: From: Nazar Kazakov Move the checks out of `do_opiv{v,x,i}_gvec{,_shift}` functions and into the corresponding macros. This enables the functions to be reused in proceeding commits without check duplication. Signed-off-by: Nazar Kazakov Reviewed-by

Re: [PATCH v3 06/19] target/riscv: Refactor translation of vector-widening instruction

On 2023/4/28 22:47, Lawrence Hunter wrote: From: Dickon Hood Zvbb (implemented in later commit) has a widening instruction, which requires an extra check on the enabled extensions. Refactor GEN_OPIVX_WIDEN_TRANS() to take a check function to avoid reimplementing it. Signed-off-by: Dickon Ho

Re: [PATCH v3 07/19] target/riscv: Refactor some of the generic vector functionality

On 2023/4/28 22:47, Lawrence Hunter wrote: From: Kiran Ostrolenk Move some macros out of `vector_helper` and into `vector_internals`. This ensures they can be used by both vector and vector-crypto helpers (latter implemented in proceeding commits). Signed-off-by: Kiran Ostrolenk --- Revie

Re: [PATCH v3 11/19] target/riscv: Add Zvbb ISA extension support

On 2023/4/28 22:47, Lawrence Hunter wrote: From: Dickon Hood This commit adds support for the Zvbb vector-crypto extension, which consists of the following instructions: * vrol.[vv,vx] * vror.[vv,vx,vi] * vbrev8.v * vrev8.v * vandn.[vv,vx] * vbrev.v * vclz.v * vctz.v * vcpop.v * vwsll.[vv,vx

Re: [PATCH v3 19/19] target/riscv: Expose Zvk* and Zvb[b, c] cpu properties

On 2023/4/28 22:47, Lawrence Hunter wrote: From: Nazar Kazakov Exposes earlier CPU flags allowing the use of the vector cryptography extensions. Signed-off-by: Nazar Kazakov --- Reviewed-by: Weiwei Li Weiwei Li target/riscv/cpu.c | 10 ++ 1 file changed, 10 insertions(+)

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