Re: [PATCH v4] acpi: pcihp: allow repeating hot-unplug requests

On Wed, Apr 26, 2023 at 07:20:08PM +0200, Kashyap Chamarthy wrote: > On Wed, Apr 26, 2023 at 07:40:02PM +0300, Michael Tokarev wrote: > > 18.04.2023 12:04, Igor Mammedov wrote: > > > with Q35 using ACPI PCI hotplug by default, user's request to unplug > > > device is ignored when it's issued before

Re: [PATCH v11 12/13] tests/qtest: Restrict tpm-tis-i2c-test to CONFIG_TCG

On 26/04/2023 20.00, Fabiano Rosas wrote: The test set -accel tcg, so restrict it to when TCG is present. Signed-off-by: Fabiano Rosas --- tests/qtest/meson.build | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build index cfc

Re: [PATCH v4] acpi: pcihp: allow repeating hot-unplug requests

27.04.2023 10:01, Michael S. Tsirkin пишет: .. You can CC stable then. Yes, please do in the future. I picked up this one already. Thanks! /mjt

Re: [PATCH v2 1/2] igb: RX descriptors handling cleanup

On 2023/04/27 1:09, Tomasz Dzieciol wrote: Format of Intel 82576 was changed in comparison to Intel 82574 extended descriptors. This change updates filling of advanced descriptors fields accordingly: * remove TCP ACK detection * add IPv6 with extensions traffic detection * fragment checksum and I

[PATCH RFC v2 5/9] target/loongarch: Implement kvm_arch_init function

Implement the kvm_arch_init of loongarch, in the function, the KVM_CAP_MP_STATE cap is checked by kvm ioctl. Signed-off-by: Tianrui Zhao --- target/loongarch/kvm.c | 1 + 1 file changed, 1 insertion(+) diff --git a/target/loongarch/kvm.c b/target/loongarch/kvm.c index 50662fd3fb..8dea294930 100

[PATCH RFC v2 1/9] linux-headers: Add KVM headers for loongarch

This patch is only a placeholder now, which is used to show some kvm structures and macros for reviewers. And it will be replaced by using update-linux-headers.sh when the linux loongarch kvm patches are accepted. Signed-off-by: Tianrui Zhao --- linux-headers/asm-loongarch/kvm.h | 99 +++

[PATCH RFC v2 9/9] target/loongarch: Add loongarch kvm into meson build

Add kvm.c and kvm-stub.c into meson.build to compile it when kvm is configed. Meanwhile in meson.build, we set the kvm_targets to loongarch64-softmmu when the cpu is loongarch. Signed-off-by: Tianrui Zhao --- meson.build | 2 ++ target/loongarch/meson.build | 1 + 2 files change

[PATCH RFC v2 0/9] Add loongarch kvm accel support

This series add loongarch kvm support, mainly implement some interfaces used by kvm such as kvm_arch_get/set_regs, kvm_arch_handle_exit, kvm_loongarch_set_interrupt, etc. Currently, we are able to boot LoongArch KVM Linux Guests. In loongarch VM, mmio devices and iocsr devices are emulated in user

[PATCH RFC v2 8/9] target/loongarch: Implement set vcpu intr for kvm

Implement loongarch kvm set vcpu interrupt interface, when a irq is set in vcpu, we use the KVM_INTERRUPT ioctl to set intr into kvm. Signed-off-by: Tianrui Zhao --- target/loongarch/cpu.c | 18 +- target/loongarch/kvm-stub.c | 11 +++ target/loongarch/kvm.

[PATCH RFC v2 7/9] target/loongarch: Implement kvm_arch_handle_exit

Implement kvm_arch_handle_exit for loongarch. In this function, the KVM_EXIT_LOONGARCH_IOCSR is handled, we read or write the iocsr address space by the addr, length and is_write argument in kvm_run. Signed-off-by: Tianrui Zhao --- target/loongarch/kvm.c| 24 +++- tar

[PATCH RFC v2 2/9] target/loongarch: Define some kvm_arch interfaces

Define some functions in target/loongarch/kvm.c, such as kvm_arch_put_registers, kvm_arch_get_registers and kvm_arch_handle_exit, etc. which are needed by kvm/kvm-all.c. Now the most functions has no content and they will be implemented in the next patches. Signed-off-by: Tianrui Zhao --- target

[PATCH RFC v2 3/9] target/loongarch: Supplement vcpu env initial when vcpu reset

Supplement vcpu env initial when vcpu reset, including init vcpu mp_state value to KVM_MP_STATE_RUNNABLE and init vcpu CSR_CPUID,CSR_TID to cpu->cpu_index. Signed-off-by: Tianrui Zhao --- target/loongarch/cpu.c | 3 +++ target/loongarch/cpu.h | 2 ++ 2 files changed, 5 insertions(+) diff --git

[PATCH RFC v2 6/9] target/loongarch: Implement kvm_arch_init_vcpu

Implement kvm_arch_init_vcpu interface for loongarch, in this function, we register VM change state handler. And when VM state changes to running, the counter value should be put into kvm to keep consistent with kvm, and when state change to stop, counter value should be refreshed from kvm. Signed

[PATCH RFC v2 4/9] target/loongarch: Implement kvm get/set registers

Implement kvm_arch_get/set_registers interfaces, many regs can be get/set in the function, such as core regs, csr regs, fpu regs, mp state, etc. Signed-off-by: Tianrui Zhao --- meson.build | 1 + target/loongarch/kvm.c| 356 +- target/l

[PATCH v3 1/2] cpu: expose qemu_cpu_list_lock for lock-guard use

Expose qemu_cpu_list_lock globally so that we can use WITH_QEMU_LOCK_GUARD and QEMU_LOCK_GUARD to simplify a few code paths now and in future. Signed-off-by: Jamie Iles --- cpus-common.c | 2 +- include/exec/cpu-common.h | 1 + linux-user/elfload.c | 12 ++-- migration

[PATCH v3 0/2] accel/tcg/tcg-accel-ops-rr: ensure fairness with icount

From: Jamie Iles The round-robin scheduler will iterate over the CPU list with an assigned budget until the next timer expiry and may exit early because of a TB exit. This is fine under normal operation but with icount enabled and SMP it is possible for a CPU to be starved of run time and the sy

[PATCH v3 2/2] accel/tcg/tcg-accel-ops-rr: ensure fairness with icount

The round-robin scheduler will iterate over the CPU list with an assigned budget until the next timer expiry and may exit early because of a TB exit. This is fine under normal operation but with icount enabled and SMP it is possible for a CPU to be starved of run time and the system live-locks. F

Re: [PATCH 08/21] Hexagon (target/hexagon) Clean up pred_written usage

On 4/26/23 22:27, Taylor Simpson wrote: We remove the last use of check_for_attrib. However, new uses will be introduced later in this series, so we change it to "static inline". This is insufficient -- clang will warn about unused inline functions within the main C file (as opposed to #includ

Re: [PATCH v3 1/2] cpu: expose qemu_cpu_list_lock for lock-guard use

On 4/27/23 03:09, Jamie Iles wrote: Expose qemu_cpu_list_lock globally so that we can use WITH_QEMU_LOCK_GUARD and QEMU_LOCK_GUARD to simplify a few code paths now and in future. Signed-off-by: Jamie Iles --- cpus-common.c | 2 +- include/exec/cpu-common.h | 1 + linux-user/elf

Re: [PATCH v3 2/2] accel/tcg/tcg-accel-ops-rr: ensure fairness with icount

On 4/27/23 03:09, Jamie Iles wrote: The round-robin scheduler will iterate over the CPU list with an assigned budget until the next timer expiry and may exit early because of a TB exit. This is fine under normal operation but with icount enabled and SMP it is possible for a CPU to be starved of

Re: [PATCH v2 1/2] igb: RX descriptors handling cleanup

On Thu, Apr 27, 2023 at 04:24:10PM +0900, Akihiko Odaki wrote: > On 2023/04/27 1:09, Tomasz Dzieciol wrote: > > Format of Intel 82576 was changed in comparison to Intel 82574 extended > > descriptors. This change updates filling of advanced descriptors fields > > accordingly: > > * remove TCP ACK d

Re: [PULL 0/7] Migration 20230426 patches

On 4/26/23 19:12, Juan Quintela wrote: The following changes since commit 9c894df3a37d675652390f7dbbe2f65b7bad7efa: migration: Create migrate_max_bandwidth() function (2023-04-24 15:01:47 +0200) are available in the Git repository at: https://gitlab.com/juan.quintela/qemu.git tags/migr

Re: [PATCH v3 03/18] hw/i386/pc_piix: Wire PIIX3 IDE ouput IRQs to ISA bus IRQs 14/15

Am 26. April 2023 12:50:08 UTC schrieb Mark Cave-Ayland : >On 02/03/2023 22:40, Philippe Mathieu-Daudé wrote: > >> Since pc_init1() has access to the ISABus*, retrieve the >> ISA IRQs with isa_bus_get_irq(). >> >> Signed-off-by: Philippe Mathieu-Daudé >> --- >> hw/i386/pc_piix.c | 8 +++

Re: [PATCH v3 03/18] hw/i386/pc_piix: Wire PIIX3 IDE ouput IRQs to ISA bus IRQs 14/15

Am 26. April 2023 12:50:08 UTC schrieb Mark Cave-Ayland : >On 02/03/2023 22:40, Philippe Mathieu-Daudé wrote: > >> Since pc_init1() has access to the ISABus*, retrieve the >> ISA IRQs with isa_bus_get_irq(). >> >> Signed-off-by: Philippe Mathieu-Daudé >> --- >> hw/i386/pc_piix.c | 8 +++

Re: [PATCH 09/21] Hexagon (target/hexagon) Don't overlap dest writes with source reads

On 4/26/23 01:42, Taylor Simpson wrote: When generating TCG, make sure we have read all the operand registers before writing to the destination registers. This is a prerequesite for short-circuiting where the source and dest operands could be the same. Signed-off-by: Taylor Simpson --- target

Re: [PATCH v20 01/21] s390x/cpu topology: add s390 specifics to CPU topology

On 25/04/2023 18.14, Pierre Morel wrote: S390 adds two new SMP levels, drawers and books to the CPU topology. The S390 CPU have specific topology features like dedication and entitlement to give to the guest indications on the host vCPUs scheduling and help the guest take the best decisions on th

Re: [PATCH 10/21] Hexagon (target/hexagon) Mark registers as read during packet analysis

On 4/26/23 01:42, Taylor Simpson wrote: Have gen_analyze_funcs mark the registers that are read by the instruction. We also mark the implicit reads using instruction attributes. Signed-off-by: Taylor Simpson --- target/hexagon/translate.h | 36 +++ target/hexagon

[PATCH] cryptodev: Handle unexpected request to avoid crash

Generally guest side should discover which services the device is able to offer, then do requests on device. However it's also possible to break this rule in a guest. Handle unexpected request here to avoid NULL pointer dereference. Fixes: e7a775fd ('cryptodev: Account statistics') Cc: Gonglei C

Re: [PATCH v11 06/13] tests/qtest: Adjust and document query-cpu-model-expansion test for arm

On 26/04/2023 20.00, Fabiano Rosas wrote: We're about to move the 32-bit CPUs under CONFIG_TCG, so adjust the query-cpu-model-expansion test to check against the cortex-a7, which is already under CONFIG_TCG. That allows the next patch to contain only code movement. While here add comments clarif

Re: [RFC PATCH 0/3] Deprecate the qemu-system-i386 binary

On 26/04/2023 12.59, Paolo Bonzini wrote: On 4/25/23 15:38, Thomas Huth wrote: - CPU types have different suffixes between the -x86_64 and -i386    variant (see TYPE_X86_CPU in cpu-qom.h) ... do we need to care    about this in the new qemu-system-i386 symlink run mode? - The code in target/i38

Re: [PATCH v5 1/2] migration: Make dirty_pages_rate atomic

On 4/26/23 22:10, Juan Quintela wrote: In this case we use qatomic operations instead of Stat64 wrapper because there is no stat64_set(). Defining the 64 bit wrapper is trivial. The one without atomics is more interesting. This does not work if CONFIG_ATOMIC64 is not defined. I actually have

Re: [PATCH v5 2/2] migration: Make dirty_bytes_last_sync atomic

On 4/26/23 22:10, Juan Quintela wrote: Don't use __nocheck() functions. Doesn't this break on 32-bit platforms? #if defined(__x86_64__) || defined(__sparc__) || defined(__mips64) # define ATOMIC_REG_SIZE 8 #else # define ATOMIC_REG_SIZE sizeof(void *) #endif #define qatomic_set(ptr, i) do

Re: [PULL 0/7] Migration 20230426 patches

Richard Henderson wrote: > On 4/26/23 19:12, Juan Quintela wrote: >> The following changes since commit 9c894df3a37d675652390f7dbbe2f65b7bad7efa: >>migration: Create migrate_max_bandwidth() function (2023-04-24 >> 15:01:47 +0200) >> are available in the Git repository at: >>https://gitlab.

Re: [RFC PATCH v2] hw/pci-bridge: Fix release ordering by embedding PCIBridgeWindows within PCIBridge

On 21/04/2023 14.25, Jonathan Cameron wrote: The lifetime of the PCIBridgeWindows instance accessed via the windows pointer in struct PCIBridge is managed separately from the PCIBridge itself. Triggered by ./qemu-system-x86_64 -M x-remote -display none -monitor stdio QEMU monitor: device_add cxl

[PULL 2/7] MAINTAINERS: Add Leonardo and Peter as reviewers

Now that David has stepped down with Migration maintainership, Leonardo and Peter has volunteer to review the migration patches. This way they got CC'd on every migration patch. Signed-off-by: Juan Quintela Acked-by: Peter Xu Acked-by: Leonardo Bras --- MAINTAINERS | 2 ++ 1 file changed, 2 in

[PULL 1/7] migration: Disable postcopy + multifd migration

From: Leonardo Bras Since the introduction of multifd, it's possible to perform a multifd migration and finish it using postcopy. A bug introduced by yank (fixed on cfc3bcf373) was previously preventing a successful use of this migration scenario, and now thing should be working on most scenario

[PULL 3/7] migration: Move migrate_use_tls() to options.c

Once there, rename it to migrate_tls() and make it return bool for consistency. Signed-off-by: Juan Quintela Reviewed-by: Vladimir Sementsov-Ogievskiy --- Fix typos found by fabiano --- migration/migration.c | 9 - migration/migration.h | 2 -- migration/options.c | 11 ++-

[PULL 4/7] migration: Move qmp_migrate_set_parameters() to options.c

Signed-off-by: Juan Quintela Reviewed-by: Vladimir Sementsov-Ogievskiy --- migration/migration.c | 420 -- migration/options.c | 418 + migration/options.h | 11 ++ 3 files changed, 429 insertions(+), 420 deleti

[PULL 7/7] vmstate-static-checker: Recognize "num" field

From: Peter Xu Recognize this field for VMS_ARRAY typed vmsd fields, then we can do proper size matching with previous patch. Note that this is compatible with old -dump-vmstate output, because when "num" is not there we'll still use the old "size" only. Signed-off-by: Peter Xu Reviewed-by: Ju

[PULL 6/7] migration/vmstate-dump: Dump array size too as "num"

From: Peter Xu For VMS_ARRAY typed vmsd fields, also dump the number of entries in the array in -vmstate-dump. Without such information, vmstate static checker can report false negatives of incompatible vmsd on VMS_ARRAY typed fields, when the src/dst do not have the same type of array defined.

Re: [RFC PATCH 0/3] Deprecate the qemu-system-i386 binary

On 4/27/23 10:13, Thomas Huth wrote: On 26/04/2023 12.59, Paolo Bonzini wrote: On 4/25/23 15:38, Thomas Huth wrote: - CPU types have different suffixes between the -x86_64 and -i386    variant (see TYPE_X86_CPU in cpu-qom.h) ... do we need to care    about this in the new qemu-system-i386 symli

[PULL 5/7] migration: Allow postcopy_ram_supported_by_host() to report err

From: Peter Xu Instead of print it to STDERR, bring the error upwards so that it can be reported via QMP responses. E.g.: { "execute": "migrate-set-capabilities" , "arguments": { "capabilities": [ { "capability": "postcopy-ram", "state": true } ] } } { "error": { "class": "GenericError",

[PULL 0/7] Migration 20230426 patches

The following changes since commit c3f9aa8e488db330197c9217e38555f6772e8f07: Merge tag 'pull-qapi-2023-04-26' of https://repo.or.cz/qemu/armbru into staging (2023-04-26 07:23:32 +0100) are available in the Git repository at: https://gitlab.com/juan.quintela/qemu.git tags/migration-20230426-

Re: [RFC PATCH 0/3] Deprecate the qemu-system-i386 binary

On Wed, Apr 26, 2023 at 12:59:13PM +0200, Paolo Bonzini wrote: > On 4/25/23 15:38, Thomas Huth wrote: > > - CPU types have different suffixes between the -x86_64 and -i386 > >variant (see TYPE_X86_CPU in cpu-qom.h) ... do we need to care > >about this in the new qemu-system-i386 symlink run

Re: [RFC PATCH 0/3] Deprecate the qemu-system-i386 binary

On Thu, Apr 27, 2023 at 10:28 AM Daniel P. Berrangé wrote: > > I wonder if we should take this a step further and rename qemu-system-x86_64 > > to qemu-system-x86! Distros can if they wish create symlinks to both > > qemu-system-i386 and qemu-system-x86_64. > > I can't help feeling this just crea

Re: [RFC PATCH 0/3] Deprecate the qemu-system-i386 binary

On Thu, Apr 27, 2023 at 10:31:00AM +0200, Paolo Bonzini wrote: > On Thu, Apr 27, 2023 at 10:28 AM Daniel P. Berrangé > wrote: > > > I wonder if we should take this a step further and rename > > > qemu-system-x86_64 > > > to qemu-system-x86! Distros can if they wish create symlinks to both > > >

Re: [PATCH v5 2/2] migration: Make dirty_bytes_last_sync atomic

Paolo Bonzini wrote: > On 4/26/23 22:10, Juan Quintela wrote: >> Don't use __nocheck() functions. > > Doesn't this break on 32-bit platforms? > > #if defined(__x86_64__) || defined(__sparc__) || defined(__mips64) > # define ATOMIC_REG_SIZE 8 > #else > # define ATOMIC_REG_SIZE sizeof(void *) > #e

Re: [PATCH v5 0/2] Migration: Make more ram_counters atomic

Juan Quintela wrote: self-NACK Working on top of paolo stat64_set() function. > Hi > > In this v5: > > Not only change the type of the counters, also use the __nocheck() > variants of the functions. > > Please, review. > > [v4] > - Change aligned_uint64_t to size_t to make (some) 32bit hosts

Re: [RFC PATCH 0/3] Deprecate the qemu-system-i386 binary

On 4/27/23 10:33, Daniel P. Berrangé wrote: On Thu, Apr 27, 2023 at 10:31:00AM +0200, Paolo Bonzini wrote: On Thu, Apr 27, 2023 at 10:28 AM Daniel P. Berrangé wrote: I wonder if we should take this a step further and rename qemu-system-x86_64 to qemu-system-x86! Distros can if they wish creat

[PATCH v4 0/3] Hyper-V Dynamic Memory Protocol driver (hv-balloon 🎈️)

From: "Maciej S. Szmigiero" This is a continuation of v3 patch series located here: https://lore.kernel.org/qemu-devel/cover.1677274611.git.maciej.szmigi...@oracle.com/ Since v3 was just a rebase a more detailed description of this driver is available in the cover letter of v2: https://lore.kern

[PATCH v4 2/3] Add Hyper-V Dynamic Memory Protocol definitions

From: "Maciej S. Szmigiero" This commit adds Hyper-V Dynamic Memory Protocol definitions, taken from hv_balloon Linux kernel driver, adapted to the QEMU coding style and definitions. Signed-off-by: Maciej S. Szmigiero --- include/hw/hyperv/dynmem-proto.h | 423 +++

[PATCH v4 3/3] Add a Hyper-V Dynamic Memory Protocol driver (hv-balloon)

From: "Maciej S. Szmigiero" This driver is like virtio-balloon on steroids: it allows both changing the guest memory allocation via ballooning and inserting pieces of extra RAM into it on demand from a provided memory backend. One of advantages of these over ACPI-based PC DIMM hotplug is that su

[PATCH v4 1/3] error: define g_autoptr() cleanup function for the Error type

From: "Maciej S. Szmigiero" Used by the hv-balloon driver for automatic memory management. Signed-off-by: Maciej S. Szmigiero --- include/qapi/error.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/qapi/error.h b/include/qapi/error.h index f21a231bb1..b0b1838e3e 100644 --- a/inc

Re: cal for agenda for QEMU developers fortnightly conference (20230502)

Hi Please, send any topic that you are interested in covering. At the end of Monday I will send an email with the agenda or the cancellation of the call, so hurry up. If I remember correctly, last week philippe was not able to attend, but there are something to discuss about single binary. An

Re: [PATCH v11 04/13] target/arm: Do not expose all -cpu max features to qtests

On 4/26/23 19:00, Fabiano Rosas wrote: We're about to move the TCG-only -cpu max configuration code under CONFIG_TCG. To be able to do that we need to make sure the qtests still have some cpu configured even when no other accelerator is available. Delineate now what is used with TCG-only and wha

Re: [PATCH v11 06/13] tests/qtest: Adjust and document query-cpu-model-expansion test for arm

On 4/26/23 19:00, Fabiano Rosas wrote: We're about to move the 32-bit CPUs under CONFIG_TCG, so adjust the query-cpu-model-expansion test to check against the cortex-a7, which is already under CONFIG_TCG. That allows the next patch to contain only code movement. While here add comments clarifyin

Re: [PATCH v11 08/13] tests/qtest: Fix tests when no KVM or TCG are present

On 4/26/23 19:00, Fabiano Rosas wrote: It is possible to have a build with both TCG and KVM disabled due to Xen requiring the i386 and x86_64 binaries to be present in an aarch64 host. If we build with --disable-tcg on the aarch64 host, we will end-up with a QEMU binary (x86) that does not suppo

Re: [PATCH v11 12/13] tests/qtest: Restrict tpm-tis-i2c-test to CONFIG_TCG

On 4/26/23 19:00, Fabiano Rosas wrote: The test set -accel tcg, so restrict it to when TCG is present. Signed-off-by: Fabiano Rosas --- tests/qtest/meson.build | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) Reviewed-by: Richard Henderson r~

Re: [PATCH v11 13/13] gitlab-ci: Check building KVM-only aarch64 target

On 4/26/23 19:00, Fabiano Rosas wrote: From: Philippe Mathieu-Daudé Add a manual new job to cross-build the aarch64 target with only the KVM accelerator enabled (in particular, no TCG). Re-enable running the similar job on the project Aarch64 custom runner. Signed-off-by: Philippe Mathieu-Daud

[PATCH v6 1/3] stat64: Add stat64_set() operation

From: Paolo Bonzini Signed-off-by: Paolo Bonzini Reviewed-by: Juan Quintela Signed-off-by: Juan Quintela --- include/qemu/stats64.h | 6 ++ util/stats64.c | 11 +++ 2 files changed, 17 insertions(+) diff --git a/include/qemu/stats64.h b/include/qemu/stats64.h index 80240

[PATCH v6 2/3] migration: Make dirty_pages_rate atomic

Signed-off-by: Juan Quintela Reviewed-by: Peter Xu --- Don't use __nocheck() variants Use stat64_get() --- migration/migration.c | 6 -- migration/ram.c | 5 +++-- migration/ram.h | 2 +- 3 files changed, 8 insertions(+), 5 deletions(-) diff --git a/migration/migration.c b/mig

[PATCH v6 3/3] migration: Make dirty_bytes_last_sync atomic

As we set its value, it needs to be operated with atomics. We rename it from remaining to better reflect its meaning. Statistics always return the real reamaining bytes. This was used to store how much pages where dirty on the previous generation, so we can calculate the expected downtime as: dir

[PATCH v6 0/3] Migration: Make more ram_counters atomic

Hi Changes in v6: - Create stat64_set() operation Impersonating Paolo in "Author" field, as he is the real author. - Update to stat64_set() - Everything is consistent and coherent under the sun. Please review. [v5] Not only change the type of the counters, also use the __nocheck() variants of

[PATCH 17/16] docs/devel/qapi-code-gen: Describe some doc markup pitfalls

Signed-off-by: Markus Armbruster --- docs/devel/qapi-code-gen.rst | 53 1 file changed, 53 insertions(+) diff --git a/docs/devel/qapi-code-gen.rst b/docs/devel/qapi-code-gen.rst index d81aac7a19..14983b074c 100644 --- a/docs/devel/qapi-code-gen.rst +++ b/docs

[PATCH 17/16] docs/devel/qapi-code-gen: Describe some doc markup pitfalls

Signed-off-by: Markus Armbruster --- docs/devel/qapi-code-gen.rst | 53 1 file changed, 53 insertions(+) diff --git a/docs/devel/qapi-code-gen.rst b/docs/devel/qapi-code-gen.rst index d81aac7a19..14983b074c 100644 --- a/docs/devel/qapi-code-gen.rst +++ b/docs

Re: [PATCH] target/riscv: Fix PMU node property for virt machine

On Thu, Apr 27, 2023 at 01:28:18PM +0800, Yu-Chien Peter Lin wrote: > Hi Conor, > > Thank you for your prompt response. > > On Fri, Apr 21, 2023 at 06:59:40PM +0100, Conor Dooley wrote: > > On Fri, Apr 21, 2023 at 09:14:37PM +0800, Yu Chien Peter Lin wrote: > > > The length of fdt_event_ctr_map[2

Re: [PATCH v6 1/3] stat64: Add stat64_set() operation

On 4/27/23 10:52, Juan Quintela wrote: From: Paolo Bonzini Signed-off-by: Paolo Bonzini Reviewed-by: Juan Quintela Signed-off-by: Juan Quintela --- include/qemu/stats64.h | 6 ++ util/stats64.c | 11 +++ 2 files changed, 17 insertions(+) Reviewed-by: Richard Henderson

Re: [PATCH v6 2/3] migration: Make dirty_pages_rate atomic

On 4/27/23 10:52, Juan Quintela wrote: Signed-off-by: Juan Quintela Reviewed-by: Peter Xu --- Don't use __nocheck() variants Use stat64_get() --- migration/migration.c | 6 -- migration/ram.c | 5 +++-- migration/ram.h | 2 +- 3 files changed, 8 insertions(+), 5 deletions(-

Re: [PATCH v6 3/3] migration: Make dirty_bytes_last_sync atomic

On 4/27/23 10:52, Juan Quintela wrote: As we set its value, it needs to be operated with atomics. We rename it from remaining to better reflect its meaning. Statistics always return the real reamaining bytes. This was used to store how much pages where dirty on the previous generation, so we ca

Apache license usage (was Re: [PULL 04/15] hw/usb: Add CanoKey Implementation)

On Tue, Jun 14, 2022 at 02:15:59PM +0200, Gerd Hoffmann wrote: > From: "Hongren (Zenithal) Zheng" > > This commit added a new emulated device called CanoKey to QEMU. > > CanoKey implements platform independent features in canokey-core > https://github.com/canokeys/canokey-core, and leaves the US

Re: [PATCH 2/9] Hexagon (target/hexagon) Add v68 scalar instructions

On 4/26/23 04:30, Taylor Simpson wrote: The following instructions are added L2_loadw_aq L4_loadd_aq R6_release_at_vi R6_release_st_vi S2_storew_rl_at_vi S4_stored_rl_at_vi S2_storew_rl_st_vi S4_stored_rl_st_vi The release instructions are nop's in qemu.

Re: [PATCH 11/21] Hexagon (target/hexagon) Short-circuit packet register writes

On 4/26/23 01:42, Taylor Simpson wrote: In certain cases, we can avoid the overhead of writing to hex_new_value and write directly to hex_gpr. We add need_commit field to DisasContext indicating if the end-of-packet commit is needed. If it is not needed, get_result_gpr() and get_result_gpr_pair

Re: [PATCH 12/21] Hexagon (target/hexagon) Short-circuit packet predicate writes

On 4/26/23 01:42, Taylor Simpson wrote: In certain cases, we can avoid the overhead of writing to hex_new_pred_value and write directly to hex_pred. We consider predicate reads/writes when computing ctx->need_commit. The get_result_pred() function uses this field to decide between hex_new_pred_

Re: [PATCH 13/21] Hexagon (target/hexagon) Short-circuit packet HVX writes

On 4/26/23 01:42, Taylor Simpson wrote: In certain cases, we can avoid the overhead of writing to future_VRegs and write directly to VRegs. We consider HVX reads/writes when computing ctx->need_commit. Then, we can early-exit from gen_commit_hvx. Signed-off-by: Taylor Simpson --- target/hexa

Re: [PATCH 14/21] Hexagon (target/hexagon) Short-circuit more HVX single instruction packets

On 4/26/23 01:42, Taylor Simpson wrote: The generated helpers for HVX use pass-by-reference, so they can't short-circuit when the reads/writes overlap. The instructions with overrides are OK because they use tcg_gen_gvec_*. We add a flag has_hvx_helper to DisasContext and extend gen_analyze_fun

[PATCH v3 0/2] igb: packet-split descriptors support

Based-on: <20230423041833.5302-1-akihiko.od...@daynix.com> ("[PATCH v3 00/47] igb: Fix for DPDK") This series of patches introduces packet-split RX descriptors support. This feature is used by Linux VF driver for MTU values from 2048. First patch makes RX descriptors handling cleanup. Second patch

[PATCH v3 1/2] igb: RX descriptors handling cleanup

Format of Intel 82576 was changed in comparison to Intel 82574 extended descriptors. This change updates filling of advanced descriptors fields accordingly: * remove TCP ACK detection * add IPv6 with extensions traffic detection * fragment checksum and IP ID is filled only when RXCSUM.IPPCSE is set

[PATCH v3 2/2] igb: packet-split descriptors support

Packet-split descriptors are used by Linux VF driver for MTU values from 2048 --- hw/net/igb_core.c | 300 +- hw/net/igb_regs.h | 6 + 2 files changed, 276 insertions(+), 30 deletions(-) diff --git a/hw/net/igb_core.c b/hw/net/igb_core.c index 1cb6440

Re: [PATCH 10/13] hw/ide/piix: Reuse PCIIDEState::{cmd,data}_ops

On 26/04/2023 21:14, Bernhard Beschow wrote: Am 26. April 2023 18:18:35 UTC schrieb Bernhard Beschow : Am 26. April 2023 11:37:48 UTC schrieb Mark Cave-Ayland : On 22/04/2023 16:07, Bernhard Beschow wrote: Now that PCIIDEState::{cmd,data}_ops are initialized in the base class constructor

Re: [PATCH 15/21] Hexagon (target/hexagon) Add overrides for disabled idef-parser insns

On 4/26/23 01:42, Taylor Simpson wrote: +tcg_gen_not_i64(tmp, tmp); +tcg_gen_and_i64(result, result, tmp); tcg_gen_andc_i64(result, result, tmp); Otherwise, Reviewed-by: Richard Henderson r~

Re: [PATCH 16/21] Hexagon (target/hexagon) Make special new_value for USR

On 4/26/23 01:42, Taylor Simpson wrote: Precursor to moving new_value from the global state to DisasContext USR will need to stay in the global state because some helpers will set it's value Signed-off-by: Taylor Simpson --- target/hexagon/cpu.h| 1 + target/hexagon/genptr.h

Re: [PATCH 17/21] Hexagon (target/hexagon) Move new_value to DisasContext

On 4/26/23 01:42, Taylor Simpson wrote: +for (i = 0; i < TOTAL_PER_THREAD_REGS; i++) { +ctx->new_value[i] = NULL; +} Perhaps memset(ctx->new_value, 0, sizeof(ctx->new_value)); Though probably the compiler would make that transformation. Or perhaps -DisasContext ctx; +

Re: QMP (without OOB) function running in thread different from the main thread as part of aio_poll

Am 26.04.2023 um 16:31 hat Fiona Ebner geschrieben: > Am 20.04.23 um 08:55 schrieb Paolo Bonzini: > > > > > > Il gio 20 apr 2023, 08:11 Markus Armbruster > > ha scritto: > > > > So, splicing in a bottom half unmoored monitor commands from the main > > loop.  We

Re: [PATCH 17/21] Hexagon (target/hexagon) Move new_value to DisasContext

On 4/27/23 12:01, Richard Henderson wrote: On 4/26/23 01:42, Taylor Simpson wrote: +    for (i = 0; i < TOTAL_PER_THREAD_REGS; i++) { +    ctx->new_value[i] = NULL; +    } Perhaps   memset(ctx->new_value, 0, sizeof(ctx->new_value)); Though probably the compiler would make that transform

Re: [PATCH 18/21] Hexagon (target/hexagon) Move new_pred_value to DisasContext

On 4/26/23 01:42, Taylor Simpson wrote: The new_pred_value array in the CPUHexagonState is only used for bookkeeping within the translation of a packet. With recent changes that eliminate the need to free TCGv variables, these make more sense to be transient and kept in DisasContext. Suggested-

Re: [PATCH 19/21] Hexagon (target/hexagon) Move pred_written to DisasContext

On 4/26/23 01:42, Taylor Simpson wrote: The pred_written variable in the CPUHexagonState is only used for bookkeeping within the translation of a packet. With recent changes that eliminate the need to free TCGv variables, these make more sense to be transient and kept in DisasContext. Suggested

Re: [PATCH 08/13] hw/ide: Rename PCIIDEState::*_bar attributes

On 26/04/2023 19:29, Bernhard Beschow wrote: Am 26. April 2023 11:21:28 UTC schrieb Mark Cave-Ayland : On 22/04/2023 16:07, Bernhard Beschow wrote: The attributes represent memory regions containing operations which are mapped by the device models into PCI BARs. Reflect this by changing the

Re: [PATCH 17/16] docs/devel/qapi-code-gen: Describe some doc markup pitfalls

Markus Armbruster wrote: > Signed-off-by: Markus Armbruster Reviewed-by: Juan Quintela > --- > docs/devel/qapi-code-gen.rst | 53 > 1 file changed, 53 insertions(+) > > diff --git a/docs/devel/qapi-code-gen.rst b/docs/devel/qapi-code-gen.rst > index d81aac

Re: [PATCH 20/21] Hexagon (target/hexagon) Move pkt_has_store_s1 to DisasContext

On 4/26/23 01:42, Taylor Simpson wrote: +static TCGv gen_slotval(DisasContext *ctx) +{ +TCGv slotval = tcg_temp_new(); +tcg_gen_movi_tl(slotval, ctx->pkt->pkt_has_store_s1 & 1); +tcg_gen_ori_tl(slotval, slotval, ctx->insn->slot << 1); +return slotval; +} This can be entirely con

Re: [PATCH 01/20] qcow2: Don't call bdrv_getlength() in coroutine_fns

Am 25.04.2023 um 20:37 hat Eric Blake geschrieben: > On Tue, Apr 25, 2023 at 07:31:39PM +0200, Kevin Wolf wrote: > > There is a bdrv_co_getlength() now, which should be used in coroutine > > context. > > > > Signed-off-by: Kevin Wolf > > --- > > block/qcow2.h | 4 +++- > > block/qcow2-

Re: [PATCH 11/13] hw/ide/sii3112: Reuse PCIIDEState::{cmd,data}_ops

On 27/04/2023 00:24, BALATON Zoltan wrote: On Wed, 26 Apr 2023, Bernhard Beschow wrote: Am 26. April 2023 11:41:54 UTC schrieb Mark Cave-Ayland : On 22/04/2023 16:07, Bernhard Beschow wrote: Allows to unexport pci_ide_{cmd,data}_le_ops and models TYPE_SII3112_PCI as a standard-compliant PCI

Re: [PATCH 04/20] block: Don't call no_coroutine_fns in qmp_block_resize()

Am 25.04.2023 um 22:08 hat Eric Blake geschrieben: > On Tue, Apr 25, 2023 at 07:31:42PM +0200, Kevin Wolf wrote: > > This QMP handler runs in a coroutine, so it must use the corresponding > > no_co_wrappers instead. > > > > Signed-off-by: Kevin Wolf > > --- > > blockdev.c | 4 ++-- > > 1 file ch

Re: [PATCH 21/21] Hexagon (target/hexagon) Move items to DisasContext

On 4/26/23 01:42, Taylor Simpson wrote: The following items in the CPUHexagonState are only used for bookkeeping within the translation of a packet. With recent changes that eliminate the need to free TCGv variables, these make more sense to be transient and kept in DisasContext. The following

Re: [PATCH v3 03/18] hw/i386/pc_piix: Wire PIIX3 IDE ouput IRQs to ISA bus IRQs 14/15

On 27/04/2023 08:58, Bernhard Beschow wrote: Am 26. April 2023 12:50:08 UTC schrieb Mark Cave-Ayland : On 02/03/2023 22:40, Philippe Mathieu-Daudé wrote: Since pc_init1() has access to the ISABus*, retrieve the ISA IRQs with isa_bus_get_irq(). Signed-off-by: Philippe Mathieu-Daudé --- h

Re: [PATCH 07/20] graph-lock: Fix GRAPH_RDLOCK_GUARD*() to be reader lock

Am 25.04.2023 um 22:36 hat Eric Blake geschrieben: > On Tue, Apr 25, 2023 at 07:31:45PM +0200, Kevin Wolf wrote: > > GRAPH_RDLOCK_GUARD() and GRAPH_RDLOCK_GUARD_MAINLOOP() only take a > > reader lock for the graph, so the correct annotation for them to use is > > TSA_ASSERT_SHARED rather than TSA_A

Re: [PATCH] meson: Pass -j option to sphinx

On Wed, Apr 26, 2023 at 01:03:46PM -0300, Fabiano Rosas wrote: > Save a bit of build time by passing the number of jobs option to > sphinx. > > To avoid warnings from sphinx, alter our plugins to inform whether > they support parallelism. The two plugins touched are quite simple and > I don't see

Re: [RFC PATCH 0/3] Deprecate the qemu-system-i386 binary

On 27/04/2023 10.33, Daniel P. Berrangé wrote: On Thu, Apr 27, 2023 at 10:31:00AM +0200, Paolo Bonzini wrote: On Thu, Apr 27, 2023 at 10:28 AM Daniel P. Berrangé wrote: I wonder if we should take this a step further and rename qemu-system-x86_64 to qemu-system-x86! Distros can if they wish cr

Re: [PATCH v2] block: add configure options for excluding vmdk, vhdx and vpc

Am 21.04.2023 um 11:27 hat Vladimir Sementsov-Ogievskiy geschrieben: > Let's add --enable / --disable configure options for these formats, > so that those who don't need them may not build them. > > Signed-off-by: Vladimir Sementsov-Ogievskiy Thanks, applied to the block branch. Kevin

Re: [RFC PATCH 0/3] Deprecate the qemu-system-i386 binary

On Thu, Apr 27, 2023 at 02:12:59PM +0200, Thomas Huth wrote: > On 27/04/2023 10.33, Daniel P. Berrangé wrote: > > On Thu, Apr 27, 2023 at 10:31:00AM +0200, Paolo Bonzini wrote: > > > On Thu, Apr 27, 2023 at 10:28 AM Daniel P. Berrangé > > > wrote: > > > > > I wonder if we should take this a step

Re: [PATCH] meson: Pass -j option to sphinx

On 26/04/2023 18.03, Fabiano Rosas wrote: Save a bit of build time by passing the number of jobs option to sphinx. To avoid warnings from sphinx, alter our plugins to inform whether they support parallelism. The two plugins touched are quite simple and I don't see anything that would indicate th

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