[PATCH 16/21] Hexagon (target/hexagon) Make special new_value for USR

Precursor to moving new_value from the global state to DisasContext USR will need to stay in the global state because some helpers will set it's value Signed-off-by: Taylor Simpson --- target/hexagon/cpu.h| 1 + target/hexagon/genptr.h | 1 + target/hexagon/macros.h

[PATCH 17/21] Hexagon (target/hexagon) Move new_value to DisasContext

The new_value array in the CPUHexagonState is only used for bookkeeping within the translation of a packet. With recent changes that eliminate the need to free TCGv variables, these make more sense to be transient and kept in DisasContext. Suggested-by: Richard Henderson Signed-off-by: Taylor Si

[PATCH 15/21] Hexagon (target/hexagon) Add overrides for disabled idef-parser insns

The following have overrides S2_insert S2_insert_rp S2_asr_r_svw_trun A2_swiz These instructions have semantics that write to the destination before all the operand reads have been completed. Therefore, the idef-parser versions were disabled with the short-circuit patch. Test cas

[PATCH 08/21] Hexagon (target/hexagon) Clean up pred_written usage

Only endloop instructions will conditionally write to a predicate. When there is an endloop instruction, we preload the values into new_pred_value. The only place pred_written is needed is when HEX_DEBUG is on. We remove the last use of check_for_attrib. However, new uses will be introduced late

[PATCH 11/21] Hexagon (target/hexagon) Short-circuit packet register writes

In certain cases, we can avoid the overhead of writing to hex_new_value and write directly to hex_gpr. We add need_commit field to DisasContext indicating if the end-of-packet commit is needed. If it is not needed, get_result_gpr() and get_result_gpr_pair() can return hex_gpr. We pass the ctx->n

[PATCH 20/21] Hexagon (target/hexagon) Move pkt_has_store_s1 to DisasContext

The pkt_has_store_s1 field is only used for bookkeeping helpers with a load. With recent changes that eliminate the need to free TCGv variables, it makes more sense to make this transient. These helpers already take the instruction slot as an argument. We combine the slot and pkt_has_store_s1 in

[PATCH 13/21] Hexagon (target/hexagon) Short-circuit packet HVX writes

In certain cases, we can avoid the overhead of writing to future_VRegs and write directly to VRegs. We consider HVX reads/writes when computing ctx->need_commit. Then, we can early-exit from gen_commit_hvx. Signed-off-by: Taylor Simpson --- target/hexagon/genptr.c| 6 - target/hexagon

[PATCH 12/21] Hexagon (target/hexagon) Short-circuit packet predicate writes

In certain cases, we can avoid the overhead of writing to hex_new_pred_value and write directly to hex_pred. We consider predicate reads/writes when computing ctx->need_commit. The get_result_pred() function uses this field to decide between hex_new_pred_value and hex_pred. Then, we can early-ex

[PATCH 21/21] Hexagon (target/hexagon) Move items to DisasContext

The following items in the CPUHexagonState are only used for bookkeeping within the translation of a packet. With recent changes that eliminate the need to free TCGv variables, these make more sense to be transient and kept in DisasContext. The following items are moved dczero_addr branch

[PATCH 14/21] Hexagon (target/hexagon) Short-circuit more HVX single instruction packets

The generated helpers for HVX use pass-by-reference, so they can't short-circuit when the reads/writes overlap. The instructions with overrides are OK because they use tcg_gen_gvec_*. We add a flag has_hvx_helper to DisasContext and extend gen_analyze_funcs to set the flag when the instruction is

[PATCH 09/21] Hexagon (target/hexagon) Don't overlap dest writes with source reads

When generating TCG, make sure we have read all the operand registers before writing to the destination registers. This is a prerequesite for short-circuiting where the source and dest operands could be the same. Signed-off-by: Taylor Simpson --- target/hexagon/genptr.c | 45 +++

[PATCH 19/21] Hexagon (target/hexagon) Move pred_written to DisasContext

The pred_written variable in the CPUHexagonState is only used for bookkeeping within the translation of a packet. With recent changes that eliminate the need to free TCGv variables, these make more sense to be transient and kept in DisasContext. Suggested-by: Richard Henderson Signed-off-by: Tay

[PATCH 10/21] Hexagon (target/hexagon) Mark registers as read during packet analysis

Have gen_analyze_funcs mark the registers that are read by the instruction. We also mark the implicit reads using instruction attributes. Signed-off-by: Taylor Simpson --- target/hexagon/translate.h | 36 +++ target/hexagon/attribs_def.h.inc| 6 +++- target/hex

[PATCH 18/21] Hexagon (target/hexagon) Move new_pred_value to DisasContext

The new_pred_value array in the CPUHexagonState is only used for bookkeeping within the translation of a packet. With recent changes that eliminate the need to free TCGv variables, these make more sense to be transient and kept in DisasContext. Suggested-by: Richard Henderson Signed-off-by: Tayl

Re: [PATCH v3 08/57] target/loongarch: Do not include tcg-ldst.h

在 2023/4/26 上午3:30, Richard Henderson 写道: This header is supposed to be private to tcg and in fact does not need to be included here at all. Signed-off-by: Richard Henderson --- target/loongarch/csr_helper.c | 1 - target/loongarch/iocsr_helper.c | 1 - 2 files changed, 2 deletions(-)

Re: [PATCH v2 4/4] migration: Allow postcopy_ram_supported_by_host() to report err

On Wed, Apr 19, 2023 at 09:51:24PM +0200, Juan Quintela wrote: > Peter Xu wrote: > > Instead of print it to STDERR, bring the error upwards so that it can be > > reported via QMP responses. > > > > E.g.: > > > > { "execute": "migrate-set-capabilities" , > > "arguments": { "capabilities": > > [

[PATCH v3] migration: Allow postcopy_ram_supported_by_host() to report err

Instead of print it to STDERR, bring the error upwards so that it can be reported via QMP responses. E.g.: { "execute": "migrate-set-capabilities" , "arguments": { "capabilities": [ { "capability": "postcopy-ram", "state": true } ] } } { "error": { "class": "GenericError", "desc": "Pos

Re: [PATCH 1/3] hw/loongarch/virt: Modify ipi as percpu device

ping ~ 在 2023/4/6 下午6:00, Song Gao 写道: ipi is used to communicate between cpus, this patch modified loongarch ipi device as percpu deivce, so that there are 2 MemoryRegions with ipi device, rather than 2*cpus MemoryRegions, which may be large than QDEV_MAX_MMIO if more cpus are added on loongarc

Re: [PATCH 2/3] hw/intc: Add NULL pointer check on LoongArch ipi device

ping ~ 在 2023/4/6 下午6:00, Song Gao 写道: When ipi mailbox is used, cpu index is decoded from iocsr register. cpu maybe does not exist. This patch adss NULL pointer check on ipi device. Signed-off-by: Song Gao --- hw/intc/loongarch_ipi.c | 31 +++ 1 file changed, 19

Re: [PATCH 3/3] hw/loongarch/virt: Set max 256 cpus support on loongarch virt machine

ping~ 在 2023/4/6 下午6:00, Song Gao 写道: Add separate macro EXTIOI_CPUS for extioi interrupt controller, extioi only supports 4 cpu. And set macro LOONGARCH_MAX_CPUS as 256 so that loongarch virt machine supports more cpus. Interrupts from external devices can only be routed cpu 0-3 because of ext

Re: [PATCH v3 13/20] block/export: rewrite vduse-blk drain code

On Wed, Apr 26, 2023 at 12:43 AM Stefan Hajnoczi wrote: > > On Fri, Apr 21, 2023 at 11:36:02AM +0800, Yongji Xie wrote: > > Hi Stefan, > > > > On Thu, Apr 20, 2023 at 7:39 PM Stefan Hajnoczi wrote: > > > > > > vduse_blk_detach_ctx() waits for in-flight requests using > > > AIO_WAIT_WHILE(). This

[PATCH 0/9] Hexagon (target/hexagon) New architecture support

Add support for new Hexagon architecture versions v68/v69/v71/v73 Taylor Simpson (9): Hexagon (target/hexagon) Add support for v68/v69/v71/v73 Hexagon (target/hexagon) Add v68 scalar instructions Hexagon (tests/tcg/hexagon) Add v68 scalar tests Hexagon (target/hexagon) Add v68 HVX instruc

[PATCH 2/9] Hexagon (target/hexagon) Add v68 scalar instructions

The following instructions are added L2_loadw_aq L4_loadd_aq R6_release_at_vi R6_release_st_vi S2_storew_rl_at_vi S4_stored_rl_at_vi S2_storew_rl_st_vi S4_stored_rl_st_vi The release instructions are nop's in qemu. The others behave as loads/stores. The encodings

[PATCH 6/9] Hexagon (target/hexagon) Add v69 HVX instructions

The following instructions are added V6_vasrvuhubrndsat V6_vasrvuhubsat V6_vasrvwuhrndsat V6_vasrvwuhsat V6_vassign_tmp V6_vcombine_tmp V6_vmpyuhvs Signed-off-by: Taylor Simpson --- target/hexagon/gen_tcg_hvx.h | 12 ++ target/hexagon/attribs_def.h

[PATCH 7/9] Hexagon (tests/tcg/hexagon) Add v69 HVX tests

The following instructions are tested V6_vasrvuhubrndsat V6_vasrvuhubsat V6_vasrvwuhrndsat V6_vasrvwuhsat V6_vassign_tmp V6_vcombine_tmp V6_vmpyuhvs Signed-off-by: Taylor Simpson --- tests/tcg/hexagon/v69_hvx.c | 318 ++ tests/tcg/hex

[PATCH 1/9] Hexagon (target/hexagon) Add support for v68/v69/v71/v73

Add support for the ELF flags Move target/hexagon/cpu.[ch] to be v73 Change the compiler flag used by "make check-tcg" The decbin instruction is removed in Hexagon v73, so check the version before trying to compile the instruction. Signed-off-by: Taylor Simpson --- configure

[PATCH 3/9] Hexagon (tests/tcg/hexagon) Add v68 scalar tests

Signed-off-by: Taylor Simpson --- tests/tcg/hexagon/v68_scalar.c| 186 ++ tests/tcg/hexagon/Makefile.target | 2 + 2 files changed, 188 insertions(+) create mode 100644 tests/tcg/hexagon/v68_scalar.c diff --git a/tests/tcg/hexagon/v68_scalar.c b/tests/tcg/hexag

[PATCH 9/9] Hexagon (tests/tcg/hexagon) Add v73 scalar tests

Tests added for the following instructions J2_callrh J2_jumprh Signed-off-by: Taylor Simpson --- tests/tcg/hexagon/v73_scalar.c| 96 +++ tests/tcg/hexagon/Makefile.target | 2 + 2 files changed, 98 insertions(+) create mode 100644 tests/tcg/hexagon/v73_s

[PATCH 5/9] Hexagon (tests/tcg/hexagon) Add v68 HVX tests

--- tests/tcg/hexagon/v6mpy_ref.h | 161 ++ tests/tcg/hexagon/v68_hvx.c | 90 + tests/tcg/hexagon/Makefile.target | 3 + 3 files changed, 254 insertions(+) create mode 100644 tests/tcg/hexagon/v6mpy_ref.h create mode 100644 tests/tcg/hexag

[PATCH 4/9] Hexagon (target/hexagon) Add v68 HVX instructions

The following instructions are added V6_v6mpyvubs10_vxx V6_v6mpyhubs10_vxx V6_v6mpyvubs10 V6_v6mpyhubs10 Signed-off-by: Taylor Simpson --- target/hexagon/mmvec/macros.h| 9 +- target/hexagon/imported/mmvec/encode_ext.def | 8 +- target/hexagon/imported/mmvec/e

[PATCH 8/9] Hexagon (target/hexagon) Add v73 scalar instructions

The following instructions are added J2_callrh J2_junprh Signed-off-by: Taylor Simpson --- target/hexagon/gen_tcg.h | 4 target/hexagon/attribs_def.h.inc | 1 + target/hexagon/imported/branch.idef | 7 ++- target/hexagon/imported/encode_pp.def | 2 ++ 4 files

Re: [PATCH v2 3/3] pci: ROM preallocation for incoming migration

On Tue, Apr 25, 2023 at 07:14:34PM +0300, Vladimir Sementsov-Ogievskiy wrote: > On incoming migration we have the following sequence to load option > ROM: > > 1. On device realize we do normal load ROM from the file > > 2. Than, on incoming migration we rewrite ROM from the incoming RAM >bloc

Re: [PATCH] cocoa: Fix warnings about invalid prototype declarations

On 2023/04/26 4:28, Philippe Mathieu-Daudé wrote: Fix the following Cocoa trivial warnings: C compiler for the host machine: cc (clang 14.0.0 "Apple clang version 14.0.0 (clang-1400.0.29.202)") Objective-C compiler for the host machine: clang (clang 14.0.0) [100/334] Compiling Objecti

Re: [RFC PATCH 1/4] pci: add handling of Enable bit in ATS Control Register

在 2023/4/24 19:21, Viktor Prutyanov 写道: According to PCIe Address Translation Services specification 5.1.3., ATS Control Register has Enable bit to enable/disable ATS. Add a new field for a trigger function which is called at the Enable bit change, so that PCIe devices can handle ATS enable/dis

Re: [RFC PATCH 1/4] pci: add handling of Enable bit in ATS Control Register

在 2023/4/26 13:31, Jason Wang 写道: 在 2023/4/24 19:21, Viktor Prutyanov 写道: According to PCIe Address Translation Services specification 5.1.3., ATS Control Register has Enable bit to enable/disable ATS. Add a new field for a trigger function which is called at the Enable bit change, so that PC

Re: [RFC PATCH 2/4] virtio-pci: add handling of ATS state change

在 2023/4/24 19:21, Viktor Prutyanov 写道: Guest may enable or disable ATS for the device. Add logic for handling these events. Signed-off-by: Viktor Prutyanov --- hw/virtio/virtio-pci.c | 12 include/hw/virtio/virtio.h | 2 ++ 2 files changed, 14 insertions(+) diff --git

Re: [RFC PATCH 4/4] vhost: register and change IOMMU flag depending on ATS state

在 2023/4/24 19:21, Viktor Prutyanov 写道: The guest can disable or never enable ATS. In these cases, Device-TLB can't be used even if enabled in QEMU. So, check ATS state before registering IOMMU notifier and select flag depending on that. Also, change IOMMU notifier flag if ATS state is changed.

[PULL 01/17] qapi: Fix error message format regression

Commit 52a474180ae3 changed reporting of errors connected to a source location without mentioning it in the commit message. For instance, $ python scripts/qapi-gen.py tests/qapi-schema/unknown-escape.json tests/qapi-schema/unknown-escape.json:3:21: unknown escape \x became scripts/q

[PULL 16/17] qapi: Improve specificity of type/member descriptions

Error messages describe object members, enumeration values, features, and variants like ROLE 'NAME', where ROLE is "member", "value", "feature", or "branch", respectively. When the member is defined in another type, e.g. inherited from a base type, we add "of type 'TYPE'". Example: test case stru

[PULL 02/17] qapi/schema: Use super()

Commit 2cae67bcb5e (qapi: Use super() now we have Python 3) converted the code to super(). Shortly after, commit f965e8fea6a (qapi: New special feature flag "deprecated") neglected to use super(). Convert it now. Signed-off-by: Markus Armbruster Message-Id: <20230316071325.492471-3-arm...@redha

[PULL 00/17] QAPI patches patches for 2023-04-26

The following changes since commit 327ec8d6c2a2223b78d311153a471036e474c5c5: Merge tag 'pull-tcg-20230423' of https://gitlab.com/rth7680/qemu into staging (2023-04-23 11:20:37 +0100) are available in the Git repository at: https://repo.or.cz/qemu/armbru.git tags/pull-qapi-2023-04-26 for

[PULL 14/17] qapi: Require boxed for conditional command and event arguments

The C code generator fails to honor 'if' conditions of command and event arguments. For instance, tests/qapi-schema/qapi-schema-test.json has { 'event': 'TEST_IF_EVENT', 'data': { 'foo': 'TestIfStruct', 'bar': { 'type': ['str'], 'if': 'TEST_IF_EVT_ARG' } }, 'if': {

[PULL 17/17] qapi: allow unions to contain further unions

From: Daniel P. Berrangé This extends the QAPI schema validation to permit unions inside unions, provided the checks for clashing fields pass. Reviewed-by: Markus Armbruster Signed-off-by: Daniel P. Berrangé Message-Id: <20230420102619.348173-4-berra...@redhat.com> Signed-off-by: Markus Armbru

[PULL 09/17] tests/qapi-schema: Improve union discriminator coverage

A union's 'discriminator' must name one of the common members. QAPISchemaVariants.check() looks it up by its c_name(), then checks the name matches exactly (because c_name() is not injective). Tests union-base-empty and union-invalid-discriminator both cover the case where lookup fails. Repurpose

[PULL 03/17] qapi: Clean up after removal of simple unions

Commit 4e99f4b12c0 (qapi: Drop simple unions) missed a bit of code dealing with simple union branches. Drop it. Signed-off-by: Markus Armbruster Message-Id: <20230316071325.492471-4-arm...@redhat.com> Reviewed-by: Eric Blake --- scripts/qapi/expr.py | 2 +- 1 file changed, 1 insertion(+), 1 de

[PULL 11/17] tests/qapi-schema: Clean up positive test for conditionals

Union TestIfUnion is conditional on macros TEST_IF_UNION and TEST_IF_STRUCT. It uses TestIfEnum, which is conditional on macro TEST_IF_ENUM. If TEST_IF_UNION and TEST_IF_STRUCT are defined, but TEST_IF_ENUM isn't, the generated code won't compile. Command test-if-cmd is conditional an macros TES

[PULL 15/17] qapi: support updating expected test output via make

From: Daniel P. Berrangé It is possible to pass --update to tests/qapi-schema/test-qapi.py to make it update the output files on error. This is inconvenient to achieve though when test-qapi.py is run indirectly by make/meson. Instead simply allow for an env variable to be set: $ QAPI_TEST_UPDA

[PULL 07/17] qapi: Fix error message when type name or array is expected

We incorrectly report "FOO should be a type name" when it could also be an array. Fix that. Signed-off-by: Markus Armbruster Message-Id: <20230316071325.492471-8-arm...@redhat.com> Reviewed-by: Eric Blake --- scripts/qapi/expr.py| 15 +++ tests/qapi-schema/e

[PULL 10/17] tests/qapi-schema: Rename a few conditionals

Positive test case { 'enum': 'TestIfEnum', 'data': [ 'foo', { 'name' : 'bar', 'if': 'TEST_IF_ENUM_BAR' } ], 'if': 'TEST_IF_ENUM' } generates #if defined(TEST_IF_ENUM) typedef enum TestIfEnum { TEST_IF_ENUM_FOO, #if defined(TEST_IF_ENUM_BAR) TEST_IF_ENU

[PULL 12/17] tests/qapi-schema: Cover optional conditional struct member

Signed-off-by: Markus Armbruster Message-Id: <20230316071325.492471-13-arm...@redhat.com> Reviewed-by: Philippe Mathieu-Daudé --- tests/qapi-schema/qapi-schema-test.json | 3 ++- tests/qapi-schema/qapi-schema-test.out | 2 ++ 2 files changed, 4 insertions(+), 1 deletion(-) diff --git a/tests/q

[PULL 04/17] qapi: Split up check_type()

check_type() can check type names, arrays, and implicit struct types. Callers pass flags to select from this menu. This makes the function somewhat hard to read. Moreover, a few minor bugs are hiding in there, as we'll see shortly. Split it into check_type_name(), check_type_name_or_array(), and

[PULL 05/17] qapi: Improve error message for unexpected array types

We reject array types in certain places with "cannot be an array". Deleting this check improves the error message to "should be a type name" or "should be an object or type name", depending on context, so do that. Signed-off-by: Markus Armbruster Message-Id: <20230316071325.492471-6-arm...@redhat

[PULL 08/17] qapi: Fix to reject 'data': 'mumble' in struct

A struct's 'data' must be a JSON object defining the struct's members. The QAPI code generator incorrectly accepts a JSON string instead, and then crashes in QAPISchema._make_members() called from ._def_struct_type(). Fix to reject it: factor check_type_implicit() out of check_type_name_or_implici

[PULL 06/17] qapi: Simplify code a bit after previous commits

Signed-off-by: Markus Armbruster Message-Id: <20230316071325.492471-7-arm...@redhat.com> Reviewed-by: Eric Blake [Commit message corrected] --- scripts/qapi/expr.py | 14 +++--- 1 file changed, 3 insertions(+), 11 deletions(-) diff --git a/scripts/qapi/expr.py b/scripts/qapi/expr.py ind

[PULL 13/17] qapi: Fix code generated for optional conditional struct member

The generated member visit neglects to emit #if around a conditional struct member's has_ variable. For instance, tests/qapi-schema/qapi-schema-test.json generates #if defined(TEST_IF_STRUCT) bool visit_type_TestIfStruct_members(Visitor *v, TestIfStruct *obj, Error **errp) { --->

Re: [PULL 61/73] hw/pci/aer: Implement PCI_ERR_UNCOR_MASK register

On Tue, Apr 25, 2023 at 08:42:17PM -0400, Peter Xu wrote: > Hi, Michael, Jonathan, > > On Tue, Mar 07, 2023 at 08:13:53PM -0500, Michael S. Tsirkin wrote: > > From: Jonathan Cameron > > > > This register in AER should be both writeable and should > > have a default value with a couple of the err

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