[PATCH v3 14/57] tcg/i386: Add have_atomic16

Notice when Intel or AMD have guaranteed that vmovdqa is atomic. The new variable will also be used in generated code. Signed-off-by: Richard Henderson --- include/qemu/cpuid.h | 18 ++ tcg/i386/tcg-target.h | 1 + tcg/i386/tcg-target.c.inc | 27

[PATCH v3 18/57] tcg/aarch64: Detect have_lse, have_lse2 for darwin

These features are present for Apple M1. Tested-by: Philippe Mathieu-Daudé Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target.c.inc | 28 1 file changed, 28 insertions(+) diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/

[PATCH v3 24/57] tcg/loongarch64: Use full load/store helpers in user-only mode

Instead of using helper_unaligned_{ld,st}, use the full load/store helpers. This will allow the fast path to increase alignment to implement atomicity while not immediately raising an alignment exception. Signed-off-by: Richard Henderson --- tcg/loongarch64/tcg-target.c.inc | 30

[PATCH v3 12/57] tcg: Add 128-bit guest memory primitives

Signed-off-by: Richard Henderson --- accel/tcg/tcg-runtime.h| 3 + include/tcg/tcg-ldst.h | 4 + accel/tcg/cputlb.c | 392 + accel/tcg/user-exec.c | 94 ++-- tcg/tcg-op.c | 184 +++- accel/

[PATCH v3 25/57] tcg/riscv: Use full load/store helpers in user-only mode

Instead of using helper_unaligned_{ld,st}, use the full load/store helpers. This will allow the fast path to increase alignment to implement atomicity while not immediately raising an alignment exception. Signed-off-by: Richard Henderson --- tcg/riscv/tcg-target.c.inc | 29 --

[PATCH v3 09/57] tcg: Unify helper_{be,le}_{ld,st}*

With the current structure of cputlb.c, there is no difference between the little-endian and big-endian entry points, aside from the assert. Unify the pairs of functions. Hoist the qemu_{ld,st}_helpers arrays to tcg.c. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- i

[PATCH v3 07/57] accel/tcg: Honor atomicity of stores

Signed-off-by: Richard Henderson --- accel/tcg/cputlb.c | 103 +++ accel/tcg/user-exec.c | 12 +- accel/tcg/ldst_atomicity.c.inc | 491 + 3 files changed, 540 insertions(+), 66 deletions(-) diff --git a/accel/tcg/cputlb.c b/accel/tcg/cput

[PATCH v3 36/57] tcg/loongarch64: Assert the host supports unaligned accesses

This should be true of all server class loongarch64. Signed-off-by: Richard Henderson --- tcg/loongarch64/tcg-target.c.inc | 6 ++ 1 file changed, 6 insertions(+) diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg-target.c.inc index e651ec5c71..ccc13ffdb4 100644 --- a/tcg/l

[PATCH v3 13/57] meson: Detect atomic128 support with optimization

There is an edge condition prior to gcc13 for which optimization is required to generate 16-byte atomic sequences. Detect this. Signed-off-by: Richard Henderson --- accel/tcg/ldst_atomicity.c.inc | 38 ++--- meson.build| 52 ++-

[PATCH v3 16/57] accel/tcg: Add aarch64 specific support in ldst_atomicity

We have code in atomic128.h noting that through GCC 8, there was no support for atomic operations on __uint128. This has been fixed in GCC 10. But we can still improve over any basic compare-and-swap loop using the ldxp/stxp instructions. Signed-off-by: Richard Henderson --- accel/tcg/ldst_ato

[PATCH v3 15/57] accel/tcg: Use have_atomic16 in ldst_atomicity.c.inc

Hosts using Intel and AMD AVX cpus are quite common. Add fast paths through ldst_atomicity using this. Signed-off-by: Richard Henderson --- accel/tcg/ldst_atomicity.c.inc | 76 +++--- 1 file changed, 60 insertions(+), 16 deletions(-) diff --git a/accel/tcg/ldst_atomi

[PATCH v3 28/57] tcg/mips: Use full load/store helpers in user-only mode

Instead of using helper_unaligned_{ld,st}, use the full load/store helpers. This will allow the fast path to increase alignment to implement atomicity while not immediately raising an alignment exception. Signed-off-by: Richard Henderson --- tcg/mips/tcg-target.c.inc | 57 ++-

[PATCH v3 46/57] tcg/loongarch64: Use atom_and_align_for_opc

Signed-off-by: Richard Henderson --- tcg/loongarch64/tcg-target.c.inc | 8 +++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg-target.c.inc index 62bf823084..43341524f2 100644 --- a/tcg/loongarch64/tcg-target.c.inc +++ b/tcg

[PATCH v3 32/57] tcg/sparc64: Rename tcg_out_movi_imm32 to tcg_out_movi_u32

Emphasize that the constant is unsigned. Signed-off-by: Richard Henderson --- tcg/sparc64/tcg-target.c.inc | 24 ++-- 1 file changed, 10 insertions(+), 14 deletions(-) diff --git a/tcg/sparc64/tcg-target.c.inc b/tcg/sparc64/tcg-target.c.inc index 2e6127d506..e244209890 10064

[PATCH v3 26/57] tcg/arm: Adjust constraints on qemu_ld/st

Always reserve r3 for tlb softmmu lookup. Fix a bug in user-only ALL_QLDST_REGS, in that r14 is clobbered by the BLNE that leads to the misaligned trap. Signed-off-by: Richard Henderson --- tcg/arm/tcg-target-con-set.h | 16 tcg/arm/tcg-target-con-str.h | 5 ++--- tcg/arm/tcg-

[PATCH v3 55/57] tcg/aarch64: Support 128-bit load/store

Use LDXP+STXP when LSE2 is not present and 16-byte atomicity is required, and LDP/STP otherwise. This requires allocating a second general-purpose temporary, as Rs cannot overlap Rn in STXP. Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target-con-set.h | 2 + tcg/aarch64/tcg-target.h

[PATCH v3 30/57] tcg/sparc64: Allocate %g2 as a third temporary

Signed-off-by: Richard Henderson --- tcg/sparc64/tcg-target.c.inc | 15 +++ 1 file changed, 7 insertions(+), 8 deletions(-) diff --git a/tcg/sparc64/tcg-target.c.inc b/tcg/sparc64/tcg-target.c.inc index e997db2645..64464ab363 100644 --- a/tcg/sparc64/tcg-target.c.inc +++ b/tcg/sparc6

[PATCH v3 45/57] tcg/arm: Use atom_and_align_for_opc

No change to the ultimate load/store routines yet, so some atomicity conditions not yet honored, but plumbs the change to alignment through the relevant functions. Signed-off-by: Richard Henderson --- tcg/arm/tcg-target.c.inc | 13 +++-- 1 file changed, 11 insertions(+), 2 deletions(-)

[PATCH v3 44/57] tcg/aarch64: Use atom_and_align_for_opc

Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target.c.inc | 38 +++- 1 file changed, 20 insertions(+), 18 deletions(-) diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc index 8e5f3d3688..1d6d382edd 100644 --- a/tcg/aarch64/tcg-target

[PATCH v3 50/57] tcg/s390x: Use atom_and_align_for_opc

Signed-off-by: Richard Henderson --- tcg/s390x/tcg-target.c.inc | 14 ++ 1 file changed, 10 insertions(+), 4 deletions(-) diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x/tcg-target.c.inc index 22f0206b5a..ddd9860a6a 100644 --- a/tcg/s390x/tcg-target.c.inc +++ b/tcg/s390x/tcg-targ

[PATCH v3 20/57] tcg: Introduce TCG_OPF_TYPE_MASK

Reorg TCG_OPF_64BIT and TCG_OPF_VECTOR into a two-bit field so that we can add TCG_OPF_128BIT without requiring another bit. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- include/tcg/tcg.h| 22 -- tcg/optimize.c | 15 +

[PATCH v3 31/57] tcg/sparc64: Rename tcg_out_movi_imm13 to tcg_out_movi_s13

Emphasize that the constant is signed. Signed-off-by: Richard Henderson --- tcg/sparc64/tcg-target.c.inc | 30 +++--- 1 file changed, 15 insertions(+), 15 deletions(-) diff --git a/tcg/sparc64/tcg-target.c.inc b/tcg/sparc64/tcg-target.c.inc index 64464ab363..2e6127d506 1

[PATCH v3 38/57] tcg/riscv: Support softmmu unaligned accesses

The system is required to emulate unaligned accesses, even if the hardware does not support it. The resulting trap may or may not be more efficient than the qemu slow path. There are linux kernel patches in flight to allow userspace to query hardware support; we can re-evaluate whether to enable

[PATCH v3 29/57] tcg/s390x: Use full load/store helpers in user-only mode

Instead of using helper_unaligned_{ld,st}, use the full load/store helpers. This will allow the fast path to increase alignment to implement atomicity while not immediately raising an alignment exception. Signed-off-by: Richard Henderson --- tcg/s390x/tcg-target.c.inc | 29 --

Re: [PATCH v3 01/57] tcg/loongarch64: Conditionalize tcg_out_exts_i32_i64

On 24/4/23 07:40, Richard Henderson wrote: Since TCG_TYPE_I32 values are kept sign-extended in registers, via ".w" instructions, we need not extend if the register matches. This is already relied upon by comparisons. Signed-off-by: Richard Henderson --- tcg/loongarch64/tcg-target.c.inc | 4 ++

[PATCH v3 39/57] tcg: Introduce tcg_target_has_memory_bswap

Replace the unparameterized TCG_TARGET_HAS_MEMORY_BSWAP macro with a function with a memop argument. Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target.h | 1 - tcg/arm/tcg-target.h | 1 - tcg/i386/tcg-target.h| 3 --- tcg/loongarch64/tcg-target.h

[PATCH v3 54/57] tcg/aarch64: Rename temporaries

We will need to allocate a second general-purpose temporary. Rename the existing temps to add a distinguishing number. Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target.c.inc | 50 ++-- 1 file changed, 25 insertions(+), 25 deletions(-) diff --git a/tcg/

[PATCH v3 02/57] accel/tcg: Add cpu_in_serial_context

Like cpu_in_exclusive_context, but also true if there is no other cpu against which we could race. Use it in tb_flush as a direct replacement. Use it in cpu_loop_exit_atomic to ensure that there is no loop against cpu_exec_step_atomic. Reviewed-by: Alex Bennée Reviewed-by: Philippe Mathieu-Daudé

[PATCH v3 35/57] accel/tcg: Remove helper_unaligned_{ld,st}

These functions are now unused. Signed-off-by: Richard Henderson --- include/tcg/tcg-ldst.h | 6 -- accel/tcg/user-exec.c | 10 -- 2 files changed, 16 deletions(-) diff --git a/include/tcg/tcg-ldst.h b/include/tcg/tcg-ldst.h index 64f48e6990..7dd57013e9 100644 --- a/include/tcg/tc

[PATCH v3 51/57] tcg/sparc64: Use atom_and_align_for_opc

Signed-off-by: Richard Henderson --- tcg/sparc64/tcg-target.c.inc | 6 -- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/tcg/sparc64/tcg-target.c.inc b/tcg/sparc64/tcg-target.c.inc index bb23038529..4f9ec02b1f 100644 --- a/tcg/sparc64/tcg-target.c.inc +++ b/tcg/sparc64/tcg-targ

[PATCH v3 42/57] tcg: Introduce atom_and_align_for_opc

Examine MemOp for atomicity and alignment, adjusting alignment as required to implement atomicity on the host. Signed-off-by: Richard Henderson --- tcg/tcg.c | 69 +++ 1 file changed, 69 insertions(+) diff --git a/tcg/tcg.c b/tcg/tcg.c index c

[PATCH v3 34/57] tcg/sparc64: Use standard slow path for softmmu

Drop the target-specific trampolines for the standard slow path. This lets us use tcg_out_helper_{ld,st}_args, and handles the new atomicity bits within MemOp. At the same time, use the full load/store helpers for user-only mode. Drop inline unaligned access support for user-only mode, as it does

[PATCH v3 43/57] tcg/i386: Use atom_and_align_for_opc

No change to the ultimate load/store routines yet, so some atomicity conditions not yet honored, but plumbs the change to alignment through the relevant functions. Signed-off-by: Richard Henderson --- tcg/i386/tcg-target.c.inc | 34 ++ 1 file changed, 22 insertion

[PATCH v3 33/57] tcg/sparc64: Split out tcg_out_movi_s32

Signed-off-by: Richard Henderson --- tcg/sparc64/tcg-target.c.inc | 10 -- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/tcg/sparc64/tcg-target.c.inc b/tcg/sparc64/tcg-target.c.inc index e244209890..4375a06377 100644 --- a/tcg/sparc64/tcg-target.c.inc +++ b/tcg/sparc64/tcg

[PATCH v3 40/57] tcg: Add INDEX_op_qemu_{ld,st}_i128

Add opcodes for backend support for 128-bit memory operations. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- include/tcg/tcg-opc.h| 8 + tcg/aarch64/tcg-target.h | 2 ++ tcg/arm/tcg-target.h | 2 ++ tcg/i386/tcg-target.h| 2 ++ tcg/

[PATCH v3 27/57] tcg/arm: Use full load/store helpers in user-only mode

Instead of using helper_unaligned_{ld,st}, use the full load/store helpers. This will allow the fast path to increase alignment to implement atomicity while not immediately raising an alignment exception. Signed-off-by: Richard Henderson --- tcg/arm/tcg-target.c.inc | 45

Re: [PATCH v3 03/57] tcg/i386: Conditionalize tcg_out_extu_i32_i64

On 24/4/23 07:40, Richard Henderson wrote: Since TCG_TYPE_I32 values are kept zero-extended in registers, via omission of the REXW bit, we need not extend if the register matches. This is already relied upon by qemu_{ld,st}. Signed-off-by: Richard Henderson --- tcg/i386/tcg-target.c.inc | 4 +

[PATCH v3 56/57] tcg/ppc: Support 128-bit load/store

Use LQ/STQ with ISA v2.07, and 16-byte atomicity is required. Note that these instructions do not require 16-byte alignment. Signed-off-by: Richard Henderson --- tcg/ppc/tcg-target-con-set.h | 2 + tcg/ppc/tcg-target-con-str.h | 1 + tcg/ppc/tcg-target.h | 3 +- tcg/ppc/tcg-target.

[PATCH v3 53/57] tcg/i386: Support 128-bit load/store with have_atomic16

Signed-off-by: Richard Henderson --- tcg/i386/tcg-target.h | 3 +- tcg/i386/tcg-target.c.inc | 184 +- 2 files changed, 182 insertions(+), 5 deletions(-) diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h index 943af6775e..7f69997e30 100644 --- a

[PATCH v3 41/57] tcg: Support TCG_TYPE_I128 in tcg_out_{ld, st}_helper_{args, ret}

Signed-off-by: Richard Henderson --- tcg/tcg.c | 174 ++ 1 file changed, 148 insertions(+), 26 deletions(-) diff --git a/tcg/tcg.c b/tcg/tcg.c index 07a9489b71..c5a0cfd846 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -206,6 +206,7 @@ static void *

[PATCH v3 22/57] tcg/aarch64: Use full load/store helpers in user-only mode

Instead of using helper_unaligned_{ld,st}, use the full load/store helpers. This will allow the fast path to increase alignment to implement atomicity while not immediately raising an alignment exception. Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target.c.inc | 35

Re: [PATCH v3 04/57] tcg: Introduce tcg_out_movext2

On 24/4/23 07:40, Richard Henderson wrote: This is common code in most qemu_{ld,st} slow paths, moving two registers when there may be overlap between sources and destinations. At present, this is only used by 32-bit hosts for 64-bit data, but will shortly be used for more than that. Signed-off-

Re: [PATCH v3 02/57] tcg/mips: Conditionalize tcg_out_exts_i32_i64

On 24/4/23 07:40, Richard Henderson wrote: Since TCG_TYPE_I32 values are kept sign-extended in registers, we need not extend if the register matches. This is already relied upon by comparisons. Signed-off-by: Richard Henderson --- tcg/mips/tcg-target.c.inc | 4 +++- 1 file changed, 3 insert

[PATCH v3 49/57] tcg/riscv: Use atom_and_align_for_opc

Signed-off-by: Richard Henderson --- tcg/riscv/tcg-target.c.inc | 8 ++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc index 5193998865..aae0512cbf 100644 --- a/tcg/riscv/tcg-target.c.inc +++ b/tcg/riscv/tcg-target.c.inc

[PATCH v3 57/57] tcg/s390x: Support 128-bit load/store

Use LPQ/STPQ when 16-byte atomicity is required. Note that these instructions require 16-byte alignment. Signed-off-by: Richard Henderson --- tcg/s390x/tcg-target-con-set.h | 2 + tcg/s390x/tcg-target.h | 2 +- tcg/s390x/tcg-target.c.inc | 100 - 3

[PATCH v3 52/57] tcg/i386: Honor 64-bit atomicity in 32-bit mode

Use the fpu to perform 64-bit loads and stores. Signed-off-by: Richard Henderson --- tcg/i386/tcg-target.c.inc | 44 +-- 1 file changed, 38 insertions(+), 6 deletions(-) diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc index 6a492bb9e7..6719

[PATCH v3 47/57] tcg/mips: Use atom_and_align_for_opc

Signed-off-by: Richard Henderson --- tcg/mips/tcg-target.c.inc | 11 --- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc index cd0254a0d7..43a8ffac17 100644 --- a/tcg/mips/tcg-target.c.inc +++ b/tcg/mips/tcg-target.c.inc

[PATCH v3 48/57] tcg/ppc: Use atom_and_align_for_opc

Signed-off-by: Richard Henderson --- tcg/ppc/tcg-target.c.inc | 17 - 1 file changed, 16 insertions(+), 1 deletion(-) diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc index c799d7c52a..743a452981 100644 --- a/tcg/ppc/tcg-target.c.inc +++ b/tcg/ppc/tcg-target.c.inc

[PATCH v3 19/57] accel/tcg: Add have_lse2 support in ldst_atomicity

Add fast paths for FEAT_LSE2, using the detection in tcg. Signed-off-by: Richard Henderson --- accel/tcg/ldst_atomicity.c.inc | 37 ++ 1 file changed, 33 insertions(+), 4 deletions(-) diff --git a/accel/tcg/ldst_atomicity.c.inc b/accel/tcg/ldst_atomicity.c.inc in

[PATCH v3 23/57] tcg/ppc: Use full load/store helpers in user-only mode

Instead of using helper_unaligned_{ld,st}, use the full load/store helpers. This will allow the fast path to increase alignment to implement atomicity while not immediately raising an alignment exception. Signed-off-by: Richard Henderson --- tcg/ppc/tcg-target.c.inc | 44

[PATCH v3 37/57] tcg/loongarch64: Support softmmu unaligned accesses

Test the final byte of an unaligned access. Use BSTRINS.D to clear the range of bits, rather than AND. Signed-off-by: Richard Henderson --- tcg/loongarch64/tcg-target.c.inc | 19 --- 1 file changed, 12 insertions(+), 7 deletions(-) diff --git a/tcg/loongarch64/tcg-target.c.inc b

[PATCH v3 21/57] tcg/i386: Use full load/store helpers in user-only mode

Instead of using helper_unaligned_{ld,st}, use the full load/store helpers. This will allow the fast path to increase alignment to implement atomicity while not immediately raising an alignment exception. Signed-off-by: Richard Henderson --- tcg/i386/tcg-target.c.inc | 48 ++-

[PATCH v3 17/57] tcg/aarch64: Detect have_lse, have_lse2 for linux

Notice when the host has additional atomic instructions. The new variables will also be used in generated code. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target.h | 3 +++ tcg/aarch64/tcg-target.c.inc | 12 2 files changed, 15 ins

Re: [PATCH v3 07/57] tcg/i386: Introduce HostAddress

On 24/4/23 07:40, Richard Henderson wrote: Collect the 4 potential parts of the host address into a struct. Reorg tcg_out_qemu_{ld,st}_direct to use it. Reorg guest_base handling to use it. Signed-off-by: Richard Henderson --- tcg/i386/tcg-target.c.inc | 165 +-

Re: [PATCH v3 08/57] tcg/i386: Drop r0+r1 local variables from tcg_out_tlb_load

On 24/4/23 07:40, Richard Henderson wrote: Use TCG_REG_L[01] constants directly. Signed-off-by: Richard Henderson --- tcg/i386/tcg-target.c.inc | 32 1 file changed, 16 insertions(+), 16 deletions(-) Reviewed-by: Philippe Mathieu-Daudé

Re: [PATCH 03/20] block: bdrv/blk_co_unref() for calls in coroutine context

On Tue, Apr 25, 2023 at 07:31:41PM +0200, Kevin Wolf wrote: > These functions must not be called in coroutine context, because they > need write access to the graph. > > Signed-off-by: Kevin Wolf > --- > include/block/block-global-state.h | 3 ++- > include/sysemu/block-backend-global-

Re: [PATCH v2 0/3] ROM migration

On Tue, Apr 25, 2023 at 07:37:43PM +0300, Vladimir Sementsov-Ogievskiy wrote: > On 25.04.23 19:14, Vladimir Sementsov-Ogievskiy wrote: > > Hi all! > > > > v2: simply ignore romfile on incoming migration when romsize is > > specified. > > > > Here I suggest a way to solve a problem, when we have e

Re: [PATCH 04/20] block: Don't call no_coroutine_fns in qmp_block_resize()

On Tue, Apr 25, 2023 at 07:31:42PM +0200, Kevin Wolf wrote: > This QMP handler runs in a coroutine, so it must use the corresponding > no_co_wrappers instead. > > Signed-off-by: Kevin Wolf > --- > blockdev.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) Reviewed-by: Eric Blake >

Re: [PATCH 05/20] test-bdrv-drain: Don't modify the graph in coroutines

On Tue, Apr 25, 2023 at 07:31:43PM +0200, Kevin Wolf wrote: > test-bdrv-drain contains a few test cases that are run both in coroutine > and non-coroutine context. Running the entire code including the setup > and shutdown in coroutines is incorrect because graph modifications can > generally not h

Re: [RFC] hw/arm/virt: Provide DT binding generation for PCI eXpander Bridges

On Tue, 25 Apr 2023 at 18:37, Jonathan Cameron wrote: > We could explore only solving the problem for pxb-cxl for now. > However, we would still be talking infrastructure in kernel only > to support emulated CXL devices and I can see that being > controversial. A normal CXL host bridge is not some

Re: [PATCH 06/20] graph-lock: Add GRAPH_UNLOCKED(_PTR)

On Tue, Apr 25, 2023 at 07:31:44PM +0200, Kevin Wolf wrote: > For some function, parts of their interface is that are called without > holding the graph lock. Add a new macro to document this. Grammar is off; maybe: For some functions, it is part of their interface to be called without holding th

[RFC PATCH v2 1/9] riscv: implement Ssqosid extension and sqoscfg CSR

From: Kornel Dulęba Implement the sqoscfg CSR defined by the Ssqosid ISA extension (Supervisor-mode Quality of Service ID). The CSR contains two fields: - Resource Control ID (RCID) used determine resource allocation - Monitoring Counter ID (MCID) used to track resource usage The CSR is def

[RFC PATCH v2 4/9] hw/riscv: implement CBQRI bandwidth controller

From: Nicolas Pitre Implement a bandwidth controller according to the Capacity and Bandwidth QoS Register Interface (CBQRI) which supports these capabilities: - Number of access types: 2 (code and data) - Usage monitoring operations: CONFIG_EVENT, READ_COUNTER - Event IDs supported: None,

[RFC PATCH v2 3/9] hw/riscv: implement CBQRI capacity controller

From: Nicolas Pitre Implement a capacity controller according to the Capacity and Bandwidth QoS Register Interface (CBQRI) which supports these capabilities: - Number of access types: 2 (code and data) - Usage monitoring operations: CONFIG_EVENT, READ_COUNTER - Event IDs supported: None, O

[RFC PATCH v2 8/9] hw/riscv: instantiate CBQRI controllers for an example SoC

From: Nicolas Pitre Instantiate a hypothetical CBQRI configuration for testing purposes with these properties: - L2 cache controllers - Resource type: Capacity - NCBLKS: 12 - Number of access types: 2 (code and data) - Usage monitoring not supported - Capacity allocation op

[RFC PATCH v2 0/9] riscv: implement Ssqosid extension and CBQRI controllers

This RFC series implements the Ssqosid extension and the sqoscfg CSR as defined in the RISC-V Capacity and Bandwidth Controller QoS Register Interface (CBQRI) specification [1]. Quality of Service (QoS) in this context is concerned with shared resources on an SoC such as cache capacity and memory b

Re: [PATCH 07/20] graph-lock: Fix GRAPH_RDLOCK_GUARD*() to be reader lock

On Tue, Apr 25, 2023 at 07:31:45PM +0200, Kevin Wolf wrote: > GRAPH_RDLOCK_GUARD() and GRAPH_RDLOCK_GUARD_MAINLOOP() only take a > reader lock for the graph, so the correct annotation for them to use is > TSA_ASSERT_SHARED rather than TSA_ASSERT. The comments at the start of graph-lock.h state tha

[RFC PATCH v2 6/9] hw/riscv: meson: add CBQRI controllers to the build

From: Nicolas Pitre Build the CBQRI controllers when RISC-V CBQRI is enabled by Kconfig. Signed-off-by: Nicolas Pitre Signed-off-by: Drew Fustini --- Changes since v1: - remove example SoC now that command line arguments supported for CBQRI hw/riscv/meson.build | 2 ++ 1 file changed, 2 inse

[RFC PATCH v2 2/9] hw/riscv: define capabilities of CBQRI controllers

From: Nicolas Pitre Define structs to represent the hardware capabilities of capacity and bandwidth controllers according to the RISC-V Capacity and Bandwidth QoS Register Interface (CBQRI). Link: https://github.com/riscv-non-isa/riscv-cbqri/blob/main/riscv-cbqri.pdf Signed-off-by: Nicolas Pitre

[RFC PATCH v2 9/9] hw/riscv: build example SoC when CBQRI_EXAMPLE_SOC enabled

Build the example SoC instantiation code when CBQRI_EXAMPLE_SOC is enabled. Signed-off-by: Nicolas Pitre Signed-off-by: Drew Fustini --- Note: the example SoC instantiation code is only included for reference and it is not required anymore for the CBQRI proof-of-concept to work. The CBQRI contro

[RFC PATCH v2 5/9] hw/riscv: Kconfig: add CBQRI options

From: Nicolas Pitre Add boolean property for CBQRI and imply it should be enabled for the RISC-V virt machine. Signed-off-by: Nicolas Pitre Signed-off-by: Drew Fustini --- Changes since v1: - remove example SoC now that command line arguments supported for CBQRI - change 'select RISC_CBQRI' to

[RFC PATCH v2 7/9] hw/riscv: add CBQRI controllers to virt machine

From: Nicolas Pitre Add CBQRI controllers to the RISC-V virt machine. The device properties can be fully configured from the command line: $ qemu-system-riscv64 -M virt ... \ -device riscv.cbqri.capacity,mmio_base=0x04828000[,...] -device riscv.cbqri.bandwidth,mmio_base=0x04829000[

Re: [PATCH 08/20] block: .bdrv_open is non-coroutine and unlocked

On Tue, Apr 25, 2023 at 07:31:46PM +0200, Kevin Wolf wrote: > Drivers were a bit confused about whether .bdrv_open can run in a > coroutine and whether or not it holds a graph lock. > > It cannot keep a graph lock from the caller across the whole function > because it both changes the graph (requi

Re: [PATCH 09/20] nbd: Remove nbd_co_flush() wrapper function

On Tue, Apr 25, 2023 at 07:31:47PM +0200, Kevin Wolf wrote: > The only thing nbd_co_flush() does is calling nbd_client_co_flush(). s/calling/call/ > Just use that function directly in the BlockDriver definitions and > remove the wrapper. > > Signed-off-by: Kevin Wolf > --- > block/nbd.c | 11 +

Re: [PATCH 10/20] nbd: Mark nbd_co_do_establish_connection() and callers GRAPH_RDLOCK

On Tue, Apr 25, 2023 at 07:31:48PM +0200, Kevin Wolf wrote: > From: Emanuele Giuseppe Esposito > > This adds GRAPH_RDLOCK annotations to declare that callers of > nbd_co_do_establish_connection() need to hold a reader lock for the > graph. > > Signed-off-by: Emanuele Giuseppe Esposito > Signed-

Re: [PATCH 11/20] vhdx: Take graph lock for accessing a node's parent list

On Tue, Apr 25, 2023 at 07:31:49PM +0200, Kevin Wolf wrote: > This adds GRAPH_RDLOCK annotations to declare that functions accessing > the parent list of a node need to hold a reader lock for the graph. As > it happens, they already do. > > Signed-off-by: Kevin Wolf > --- > block/vhdx.c | 9

Re: [PATCH 12/20] mirror: Take graph lock for accessing a node's parent list

On Tue, Apr 25, 2023 at 07:31:50PM +0200, Kevin Wolf wrote: > This adds GRAPH_RDLOCK annotations to declare that functions accessing > the parent list of a node need to hold a reader lock for the graph. As > it happens, they already do. > > Signed-off-by: Kevin Wolf > --- > block/mirror.c | 2 +-

Re: [PATCH 13/20] block: Mark bdrv_co_get_allocated_file_size() and callers GRAPH_RDLOCK

On Tue, Apr 25, 2023 at 07:31:51PM +0200, Kevin Wolf wrote: > From: Emanuele Giuseppe Esposito > > This adds GRAPH_RDLOCK annotations to declare that callers of > bdrv_co_get_allocated_file_size() need to hold a reader lock for the > graph. > > Signed-off-by: Emanuele Giuseppe Esposito > Signed

Re: [PATCH 14/20] block: Mark bdrv_co_get_info() and callers GRAPH_RDLOCK

On Tue, Apr 25, 2023 at 07:31:52PM +0200, Kevin Wolf wrote: > From: Emanuele Giuseppe Esposito > > This adds GRAPH_RDLOCK annotations to declare that callers of > bdrv_co_get_info() need to hold a reader lock for the graph. > > Signed-off-by: Emanuele Giuseppe Esposito > Signed-off-by: Kevin Wo

Re: [PATCH 15/20] block: Mark bdrv_co_debug_event() GRAPH_RDLOCK

On Tue, Apr 25, 2023 at 07:31:53PM +0200, Kevin Wolf wrote: > From: Emanuele Giuseppe Esposito > > This adds GRAPH_RDLOCK annotations to declare that callers of > bdrv_co_debug_event() need to hold a reader lock for the graph. > > Unfortunately we cannot use a co_wrapper_bdrv_rdlock, because the

Re: [PATCH 16/20] block: Mark BlockDriver callbacks for amend job GRAPH_RDLOCK

On Tue, Apr 25, 2023 at 07:31:54PM +0200, Kevin Wolf wrote: > From: Emanuele Giuseppe Esposito > > This adds GRAPH_RDLOCK annotations to declare that callers of amend > callbacks in BlockDriver need to hold a reader lock for the graph. > > Signed-off-by: Emanuele Giuseppe Esposito > Signed-off-

Re: [PATCH 17/20] block: Mark bdrv_query_bds_stats() and callers GRAPH_RDLOCK

On Tue, Apr 25, 2023 at 07:31:55PM +0200, Kevin Wolf wrote: > This adds GRAPH_RDLOCK annotations to declare that callers of > bdrv_query_bds_stats() need to hold a reader lock for the graph because > it accesses the children list of a node. > > Signed-off-by: Kevin Wolf > --- > block/qapi.c | 6

Re: [PATCH 18/20] block: Mark bdrv_query_block_graph_info() and callers GRAPH_RDLOCK

On Tue, Apr 25, 2023 at 07:31:56PM +0200, Kevin Wolf wrote: > This adds GRAPH_RDLOCK annotations to declare that callers of > bdrv_query_block_graph_info() need to hold a reader lock for the graph > because it accesses the children list of a node. > > Signed-off-by: Kevin Wolf > --- > include/bl

Re: [PATCH 19/20] block: Mark bdrv_recurse_can_replace() and callers GRAPH_RDLOCK

On Tue, Apr 25, 2023 at 07:31:57PM +0200, Kevin Wolf wrote: > This adds GRAPH_RDLOCK annotations to declare that callers of > bdrv_recurse_can_replace() need to hold a reader lock for the graph > because it accesses the children list of a node. > > Signed-off-by: Kevin Wolf > --- > include/block

Re: [PATCH 20/20] block: Mark bdrv_refresh_limits() and callers GRAPH_RDLOCK

On Tue, Apr 25, 2023 at 07:31:58PM +0200, Kevin Wolf wrote: > This adds GRAPH_RDLOCK annotations to declare that callers of > bdrv_refresh_limits() need to hold a reader lock for the graph because > it accesses the children list of a node. > > Signed-off-by: Kevin Wolf > --- > include/block/bloc

Re: [PATCH v2] hw/net: npcm7xx_emc: set MAC in register space

On Thu, Oct 6, 2022 at 6:18 AM Peter Maydell wrote: > On Mon, 3 Oct 2022 at 18:38, Patrick Venture wrote: > > > > The MAC address set from Qemu wasn't being saved into the register space. > > > > Reviewed-by: Hao Wu > > Signed-off-by: Patrick Venture > > --- > > v2: only set the registers from

[PATCH v3 0/2] tests/tcg/s390x: Enable the multiarch system tests

v2: https://lists.gnu.org/archive/html/qemu-devel/2023-04/msg04154.html v2 -> v3: The idea with sharing the QEMU headers with the tests seems to be controversial. Just rework the test to work without the explicit byte swaps. v1: https://lists.gnu.org/archive/html/qemu-devel/202

[PATCH v3 2/2] tests/tcg/s390x: Enable the multiarch system tests

Multiarch tests are written in C and need support for printing characters. Instead of implementing the runtime from scratch, just reuse the pc-bios/s390-ccw one. Run tests with -nographic in order to enable SCLP (enable this for the existing tests as well, since it does not hurt). Use the default

[PATCH v3 1/2] tests/tcg/multiarch: Make the system memory test work on big-endian

Store the bytes in descending order on big-endian. Invert the logic in the multi-byte signed tests on big-endian. Make the checks in the multi-byte signed tests stricter. Signed-off-by: Ilya Leoshkevich --- tests/tcg/multiarch/system/memory.c | 64 +++-- 1 file changed, 4

Re: [PATCH v10 9/9] KVM: Enable and expose KVM_MEM_PRIVATE

On Tue, Apr 18, 2023, Ackerley Tng wrote: > Sean Christopherson writes: > > I agree, a pure alignment check is too restrictive, and not really what I > > intended despite past me literally saying that's what I wanted :-) I think > > I may have also inverted the "less alignment" statement, but luc

Re: [PATCH v2] hw/net: npcm7xx_emc: set MAC in register space

Hi, On 3/10/22 19:38, Patrick Venture wrote: The MAC address set from Qemu wasn't being saved into the register space. Reviewed-by: Hao Wu Signed-off-by: Patrick Venture --- v2: only set the registers from qemu on reset once registers set, only read and write to them --- hw/net/npcm7xx

[PATCH 00/21] Hexagon (target/hexagon) short-circuit and move to DisasContext

This patch series achieves two major goals Goal 1: Short-circuit packet semantics In certain cases, we can avoid the overhead of writing to hex_new_value and write directly to hex_gpr. Here's a simple example of the TCG generated for 0x004000b4: 0x7800c020 { R0 = #0x1 }

[PATCH 01/21] meson.build Add CONFIG_HEXAGON_IDEF_PARSER

Enable conditional compilation depending on whether idef-parser is configured Signed-off-by: Taylor Simpson --- meson.build | 1 + 1 file changed, 1 insertion(+) diff --git a/meson.build b/meson.build index c44d05a13f..d4e438b033 100644 --- a/meson.build +++ b/meson.build @@ -1859,6 +1859,7 @@

[PATCH 02/21] Hexagon (target/hexagon) Add DisasContext arg to gen_log_reg_write

Add DisasContext arg to gen_log_reg_write_pair also Signed-off-by: Taylor Simpson --- target/hexagon/gen_tcg.h| 2 +- target/hexagon/genptr.h | 2 +- target/hexagon/genptr.c | 10 +- target/hexagon/idef-parser/parser-helpers.c

[PATCH 04/21] Hexagon (target/hexagon) Add overrides for allocframe/deallocframe

These instructions have implicit writes to registers, so we don't want them to be helpers when idef-parser is off. Signed-off-by: Taylor Simpson --- target/hexagon/gen_tcg.h | 32 + target/hexagon/genptr.c | 44 2 files change

[PATCH 03/21] Hexagon (target/hexagon) Add overrides for loop setup instructions

These instructions have implicit writes to registers, so we don't want them to be helpers when idef-parser is off. Signed-off-by: Taylor Simpson --- target/hexagon/gen_tcg.h | 21 +++ target/hexagon/genptr.c | 44 2 files changed, 65 inse

[PATCH 07/21] Hexagon (target/hexagon) Eliminate uses of log_pred_write function

These instructions have implicit writes to registers, so we don't want them to be helpers when idef-parser is off. The following instructions are overriden S2_cabacdecbin SA1_cmpeqi Remove the log_pred_write function from op_helper.c Remove references in macros.h Signed-off-by: Taylor Si

[PATCH 06/21] Hexagon (target/hexagon) Remove log_reg_write from op_helper.[ch]

With the overrides added in prior commits, this function is not used Remove references in macros.h Signed-off-by: Taylor Simpson --- target/hexagon/macros.h| 14 -- target/hexagon/op_helper.h | 4 target/hexagon/op_helper.c | 17 - 3 files changed, 35 deleti

[PATCH 05/21] Hexagon (target/hexagon) Add overrides for clr[tf]new

These instructions have implicit reads from p0, so we don't want them in helpers when idef-parser is off. Signed-off-by: Taylor Simpson --- target/hexagon/gen_tcg.h | 18 ++ target/hexagon/macros.h | 4 2 files changed, 18 insertions(+), 4 deletions(-) diff --git a/target

Re: [PULL 61/73] hw/pci/aer: Implement PCI_ERR_UNCOR_MASK register

Hi, Michael, Jonathan, On Tue, Mar 07, 2023 at 08:13:53PM -0500, Michael S. Tsirkin wrote: > From: Jonathan Cameron > > This register in AER should be both writeable and should > have a default value with a couple of the errors masked > including the Uncorrectable Internal Error used by CXL for

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