On 20/04/2023 07.46, Akihiko Odaki wrote:
It is unlikely to find more bugs with KVM so remove test_igb_nomsi_kvm
to save time to run it.
Signed-off-by: Akihiko Odaki
---
tests/avocado/netdev-ethtool.py | 12 +---
1 file changed, 1 insertion(+), 11 deletions(-)
diff --git a/tests/avo
QEMU invokes vhost_svq_add() when adding a guest's element into SVQ.
In vhost_svq_add(), it uses vhost_svq_available_slots() to check
whether QEMU can add the element into the SVQ. If there is
enough space, then QEMU combines some out descriptors and
some in descriptors into one descriptor chain, a
> On 20-Mar-2023, at 5:12 PM, Ani Sinha wrote:
>
> From: Ani Sinha
>
> Update mailmap to indicate a...@anisinha.ca and anisi...@redhat.com are one
> and
> the same person. Additionally update MAINTAINERS and bits documentation to use
> my work (redhat) email.
>
> Signed-off-by: Ani Sinha
> On 06-Apr-2023, at 1:37 PM, Igor Mammedov wrote:
>
> On Wed, 29 Mar 2023 10:27:26 +0530
> Ani Sinha wrote:
>
>> i440fx machine versions 2.3 and newer supports dynamic ram
>> resizing. See commit a1666142db6233 ("acpi-build: make ROMs RAM blocks
>> resizeable") .
>> Currently supported all
On 19/04/2023 18:28, Stefan Hajnoczi wrote:
There is no need to suspend activity between aio_disable_external() and
aio_enable_external(), which is mainly used for the block layer's drain
operation.
This is part of ongoing work to remove the aio_disable_external() API.
Reviewed-by: David Woodho
Hi Kautuk,
On 19/4/23 11:22, Kautuk Consul wrote:
Commit c0c8687ef0fd990db8db1655a8a6c5a5e35dd4bb disabled the
boot_linux.py test-case due to which the code coverage for ppc
decreased by around 2%. As per the discussion on
https://lore.kernel.org/qemu-devel/87sfdpqcy4@linaro.org/ it
was ment
On Tue, Apr 18, 2023 at 10:22 PM Eric DeVolder wrote:
>
> Currently i386 QEMU generates MADT revision 3, and reports
> MADT revision 1. ACPI 6.3 introduces MADT revision 5.
>
> For MADT revision 4, that introduces ARM GIC structures, which do
> not apply to i386.
>
> For MADT revision 5, the Local
This patch includes:
- VMAX[I].{B/H/W/D}[U];
- VMIN[I].{B/H/W/D}[U].
Signed-off-by: Song Gao
---
target/loongarch/disas.c| 33
target/loongarch/helper.h | 18 ++
target/loongarch/insn_trans/trans_lsx.c.inc | 200
target/loongarch/
This patch includes:
- VADD.{B/H/W/D/Q};
- VSUB.{B/H/W/D/Q}.
Reviewed-by: Richard Henderson
Signed-off-by: Song Gao
---
target/loongarch/disas.c| 23 +++
target/loongarch/insn_trans/trans_lsx.c.inc | 69 +
target/loongarch/insns.decode |
This patch includes:
- VADDI.{B/H/W/D}U;
- VSUBI.{B/H/W/D}U.
Reviewed-by: Richard Henderson
Signed-off-by: Song Gao
---
target/loongarch/disas.c| 14
target/loongarch/insn_trans/trans_lsx.c.inc | 37 +
target/loongarch/insns.decode
This patch includes:
- VINSGR2VR.{B/H/W/D};
- VPICKVE2GR.{B/H/W/D}[U];
- VREPLGR2VR.{B/H/W/D}.
Reviewed-by: Richard Henderson
Signed-off-by: Song Gao
---
target/loongarch/disas.c| 33 ++
target/loongarch/insn_trans/trans_lsx.c.inc | 110
target/loon
Reviewed-by: Richard Henderson
Signed-off-by: Song Gao
---
target/loongarch/insn_trans/trans_lsx.c.inc | 5 +
target/loongarch/lsx_helper.c | 6 ++
target/loongarch/meson.build| 1 +
target/loongarch/translate.c| 1 +
4 files changed, 13 inse
This patch includes:
- VSADD.{B/H/W/D}[U];
- VSSUB.{B/H/W/D}[U].
Reviewed-by: Richard Henderson
Signed-off-by: Song Gao
---
target/loongarch/disas.c| 17 +
target/loongarch/insn_trans/trans_lsx.c.inc | 17 +
target/loongarch/insns.decode
This patch includes:
- VMSKLTZ.{B/H/W/D};
- VMSKGEZ.B;
- VMSKNZ.B.
Signed-off-by: Song Gao
---
target/loongarch/disas.c| 7 ++
target/loongarch/helper.h | 7 ++
target/loongarch/insn_trans/trans_lsx.c.inc | 7 ++
target/loongarch/insns.decode
This patch includes:
- VDIV.{B/H/W/D}[U];
- VMOD.{B/H/W/D}[U].
Reviewed-by: Richard Henderson
Signed-off-by: Song Gao
---
target/loongarch/disas.c| 17 ++
target/loongarch/helper.h | 17 ++
target/loongarch/insn_trans/trans_lsx.c.inc | 17 ++
Hi,
This series adds LoongArch LSX instructions, Since the LoongArch
Vol2 is not open, So we use 'RFC' title.
About test:
V2 we use RISU test the LoongArch LSX instructions.
QEMU:
https://github.com/loongson/qemu/tree/tcg-old-abi-support-lsx
RISU:
https://github.com/loongson/risu/tree/lo
This patch includes:
- VADDW{EV/OD}.{H.B/W.H/D.W/Q.D}[U];
- VSUBW{EV/OD}.{H.B/W.H/D.W/Q.D}[U];
- VADDW{EV/OD}.{H.BU.B/W.HU.H/D.WU.W/Q.DU.D}.
Signed-off-by: Song Gao
---
target/loongarch/disas.c| 43 ++
target/loongarch/helper.h | 45 ++
target/loongarch/in
Signed-off-by: Song Gao
---
target/loongarch/cpu.c | 2 ++
target/loongarch/cpu.h | 2 ++
target/loongarch/insn_trans/trans_lsx.c.inc | 11 +++
3 files changed, 15 insertions(+)
diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c
index
This patch includes:
- VHADDW.{H.B/W.H/D.W/Q.D/HU.BU/WU.HU/DU.WU/QU.DU};
- VHSUBW.{H.B/W.H/D.W/Q.D/HU.BU/WU.HU/DU.WU/QU.DU}.
Reviewed-by: Richard Henderson
Signed-off-by: Song Gao
---
target/loongarch/disas.c| 17 +
target/loongarch/helper.h | 18 +
This patch includes:
- VEXTH.{H.B/W.H/D.W/Q.D};
- VEXTH.{HU.BU/WU.HU/DU.WU/QU.DU}.
Reviewed-by: Richard Henderson
Signed-off-by: Song Gao
---
target/loongarch/disas.c| 9 ++
target/loongarch/helper.h | 9 ++
target/loongarch/insn_trans/trans_lsx.c
Signed-off-by: Song Gao
---
linux-user/loongarch64/signal.c | 4 +-
target/loongarch/cpu.c | 2 +-
target/loongarch/cpu.h | 21 +-
target/loongarch/gdbstub.c | 4 +-
target/loongarch/internals.h| 22 ++
target/loongarch/machine.c | 115 +
This patch includes:
- VILV{L/H}.{B/H/W/D};
- VSHUF.{B/H/W/D};
- VSHUF4I.{B/H/W/D};
- VPERMI.W;
- VEXTRINS.{B/H/W/D}.
Signed-off-by: Song Gao
---
target/loongarch/disas.c| 25
target/loongarch/helper.h | 25
target/loongarch/insn_trans/trans_lsx.
This patch includes;
- VNEG.{B/H/W/D}.
Reviewed-by: Richard Henderson
Signed-off-by: Song Gao
---
target/loongarch/disas.c| 10 ++
target/loongarch/insn_trans/trans_lsx.c.inc | 20
target/loongarch/insns.decode | 7 +++
3 files
This patch includes:
- VFRSTP[I].{B/H}.
Acked-by: Richard Henderson
Signed-off-by: Song Gao
---
target/loongarch/disas.c| 5 +++
target/loongarch/helper.h | 5 +++
target/loongarch/insn_trans/trans_lsx.c.inc | 5 +++
target/loongarch/insns.decode
This patch includes:
- VABSD.{B/H/W/D}[U].
Reviewed-by: Richard Henderson
Signed-off-by: Song Gao
---
target/loongarch/disas.c| 9 ++
target/loongarch/helper.h | 9 ++
target/loongarch/insn_trans/trans_lsx.c.inc | 95 +
target/loongarc
This patch includes:
- VSRLN.{B.H/H.W/W.D};
- VSRAN.{B.H/H.W/W.D};
- VSRLNI.{B.H/H.W/W.D/D.Q};
- VSRANI.{B.H/H.W/W.D/D.Q}.
Reviewed-by: Richard Henderson
Signed-off-by: Song Gao
---
target/loongarch/disas.c| 16 +++
target/loongarch/helper.h | 16 +++
tar
This patch includes:
- VBITCLR[I].{B/H/W/D};
- VBITSET[I].{B/H/W/D};
- VBITREV[I].{B/H/W/D}.
Signed-off-by: Song Gao
---
target/loongarch/disas.c| 25 ++
target/loongarch/helper.h | 27 ++
target/loongarch/insn_trans/trans_lsx.c.inc | 305 +
This patch includes:
- VCLO.{B/H/W/D};
- VCLZ.{B/H/W/D}.
Reviewed-by: Richard Henderson
Signed-off-by: Song Gao
---
target/loongarch/disas.c| 9 ++
target/loongarch/helper.h | 9 ++
target/loongarch/insn_trans/trans_lsx.c.inc | 9 ++
target/l
This patch includes:
- V{AND/OR/XOR/NOR/ANDN/ORN}.V;
- V{AND/OR/XOR/NOR}I.B.
Signed-off-by: Song Gao
---
target/loongarch/disas.c| 12 +
target/loongarch/helper.h | 2 +
target/loongarch/insn_trans/trans_lsx.c.inc | 56 +
target/loon
This patch includes:
- VBITSEL.V;
- VBITSELI.B;
- VSET{EQZ/NEZ}.V;
- VSETANYEQZ.{B/H/W/D};
- VSETALLNEZ.{B/H/W/D}.
Signed-off-by: Song Gao
---
target/loongarch/disas.c| 20 ++
target/loongarch/helper.h | 11 +++
target/loongarch/insn_trans/trans_lsx.c.in
This patch includes:
- VSSRLRN.{B.H/H.W/W.D};
- VSSRARN.{B.H/H.W/W.D};
- VSSRLRN.{BU.H/HU.W/WU.D};
- VSSRARN.{BU.H/HU.W/WU.D};
- VSSRLRNI.{B.H/H.W/W.D/D.Q};
- VSSRARNI.{B.H/H.W/W.D/D.Q};
- VSSRLRNI.{BU.H/HU.W/WU.D/DU.Q};
- VSSRARNI.{BU.H/HU.W/WU.D/DU.Q}.
Signed-off-by: Song Gao
---
target/loonga
This patch includes:
- VFCVT{L/H}.{S.H/D.S};
- VFCVT.{H.S/S.D};
- VFRINT[{RNE/RZ/RP/RM}].{S/D};
- VFTINT[{RNE/RZ/RP/RM}].{W.S/L.D};
- VFTINT[RZ].{WU.S/LU.D};
- VFTINT[{RNE/RZ/RP/RM}].W.D;
- VFTINT[{RNE/RZ/RP/RM}]{L/H}.L.S;
- VFFINT.{S.W/D.L}[U];
- VFFINT.S.L, VFFINT{L/H}.D.W.
Signed-off-by: Song G
This patch includes:
- VLD[X], VST[X];
- VLDREPL.{B/H/W/D};
- VSTELM.{B/H/W/D}.
Signed-off-by: Song Gao
---
target/loongarch/disas.c| 34 +
target/loongarch/insn_trans/trans_lsx.c.inc | 155
target/loongarch/insns.decode | 36 +
ta
This patch includes:
- VSIGNCOV.{B/H/W/D}.
Reviewed-by: Richard Henderson
Signed-off-by: Song Gao
---
target/loongarch/disas.c| 5 ++
target/loongarch/helper.h | 5 ++
target/loongarch/insn_trans/trans_lsx.c.inc | 53 +
target/loongarc
This patch includes:
- VSAT.{B/H/W/D}[U].
Signed-off-by: Song Gao
---
target/loongarch/disas.c| 9 ++
target/loongarch/helper.h | 9 ++
target/loongarch/insn_trans/trans_lsx.c.inc | 101
target/loongarch/insns.decode |
This patch includes:
- VAVG.{B/H/W/D}[U];
- VAVGR.{B/H/W/D}[U].
Reviewed-by: Richard Henderson
Signed-off-by: Song Gao
---
target/loongarch/disas.c| 17 ++
target/loongarch/helper.h | 18 ++
target/loongarch/insn_trans/trans_lsx.c.inc | 197 ++
This patch includes:
- VSSRLN.{B.H/H.W/W.D};
- VSSRAN.{B.H/H.W/W.D};
- VSSRLN.{BU.H/HU.W/WU.D};
- VSSRAN.{BU.H/HU.W/WU.D};
- VSSRLNI.{B.H/H.W/W.D/D.Q};
- VSSRANI.{B.H/H.W/W.D/D.Q};
- VSSRLNI.{BU.H/HU.W/WU.D/DU.Q};
- VSSRANI.{BU.H/HU.W/WU.D/DU.Q}.
Reviewed-by: Richard Henderson
Signed-off-by: Song
This patch includes:
- VLDI.
Signed-off-by: Song Gao
---
target/loongarch/disas.c| 7 +
target/loongarch/insn_trans/trans_lsx.c.inc | 137
target/loongarch/insns.decode | 4 +
3 files changed, 148 insertions(+)
diff --git a/target/loong
This patch includes:
- VF{ADD/SUB/MUL/DIV}.{S/D};
- VF{MADD/MSUB/NMADD/NMSUB}.{S/D};
- VF{MAX/MIN}.{S/D};
- VF{MAXA/MINA}.{S/D};
- VFLOGB.{S/D};
- VFCLASS.{S/D};
- VF{SQRT/RECIP/RSQRT}.{S/D}.
Reviewed-by: Richard Henderson
Signed-off-by: Song Gao
---
target/loongarch/cpu.h
This patch includes:
- VREPLVE[I].{B/H/W/D};
- VBSLL.V, VBSRL.V;
- VPACK{EV/OD}.{B/H/W/D};
- VPICK{EV/OD}.{B/H/W/D}.
Reviewed-by: Richard Henderson
Signed-off-by: Song Gao
---
target/loongarch/disas.c| 35 +
target/loongarch/helper.h | 18 +++
target/
This patch includes:
- VFCMP.cond.{S/D}.
Reviewed-by: Richard Henderson
Signed-off-by: Song Gao
---
target/loongarch/disas.c| 94 +
target/loongarch/helper.h | 5 ++
target/loongarch/insn_trans/trans_lsx.c.inc | 32 +++
target/loong
This patch includes:
- VMUL.{B/H/W/D};
- VMUH.{B/H/W/D}[U];
- VMULW{EV/OD}.{H.B/W.H/D.W/Q.D}[U];
- VMULW{EV/OD}.{H.BU.B/W.HU.H/D.WU.W/Q.DU.D}.
Signed-off-by: Song Gao
---
include/tcg/tcg-op.h| 4 +
target/loongarch/disas.c| 38 ++
target/loongarch/h
Introduce set_fpr() and get_fpr() and remove cpu_fpr.
Signed-off-by: Song Gao
---
.../loongarch/insn_trans/trans_farith.c.inc | 72 +++
target/loongarch/insn_trans/trans_fcmp.c.inc | 12 ++--
.../loongarch/insn_trans/trans_fmemory.c.inc | 37 ++
target/loongarch/insn_
This patch includes:
- VSLLWIL.{H.B/W.H/D.W};
- VSLLWIL.{HU.BU/WU.HU/DU.WU};
- VEXTL.Q.D, VEXTL.QU.DU.
Reviewed-by: Richard Henderson
Signed-off-by: Song Gao
---
target/loongarch/disas.c| 9 +
target/loongarch/helper.h | 9 +
target/loongarch/insn
This patch includes:
- VPCNT.{B/H/W/D}.
Signed-off-by: Song Gao
---
target/loongarch/disas.c| 5 +
target/loongarch/helper.h | 5 +
target/loongarch/insn_trans/trans_lsx.c.inc | 5 +
target/loongarch/insns.decode | 5 +
targ
This patch includes:
- VSRLRN.{B.H/H.W/W.D};
- VSRARN.{B.H/H.W/W.D};
- VSRLRNI.{B.H/H.W/W.D/D.Q};
- VSRARNI.{B.H/H.W/W.D/D.Q}.
Signed-off-by: Song Gao
---
target/loongarch/disas.c| 16 +++
target/loongarch/helper.h | 16 +++
target/loongarch/insn_trans/tra
This patch includes:
- VSRLR[I].{B/H/W/D};
- VSRAR[I].{B/H/W/D}.
Reviewed-by: Richard Henderson
Signed-off-by: Song Gao
---
target/loongarch/disas.c| 18
target/loongarch/helper.h | 18
target/loongarch/insn_trans/trans_lsx.c.inc | 18
tar
This patch includes:
- VADDA.{B/H/W/D}.
Reviewed-by: Richard Henderson
Signed-off-by: Song Gao
---
target/loongarch/disas.c| 5 ++
target/loongarch/helper.h | 5 ++
target/loongarch/insn_trans/trans_lsx.c.inc | 53 +
target/loongarch/i
This patch includes:
- VSEQ[I].{B/H/W/D};
- VSLE[I].{B/H/W/D}[U];
- VSLT[I].{B/H/W/D/}[U].
Signed-off-by: Song Gao
---
target/loongarch/disas.c| 43 +
target/loongarch/helper.h | 23 +++
target/loongarch/insn_trans/trans_lsx.c.inc | 185 +++
Reviewed-by: Richard Henderson
Signed-off-by: Song Gao
---
target/loongarch/cpu.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c
index 55d7f9255e..c0afc21b2f 100644
--- a/target/loongarch/cpu.c
+++ b/target/loongarch/cpu.c
@@ -388,6 +388,7 @@
This patch includes:
- VMADD.{B/H/W/D};
- VMSUB.{B/H/W/D};
- VMADDW{EV/OD}.{H.B/W.H/D.W/Q.D}[U];
- VMADDW{EV/OD}.{H.BU.B/W.HU.H/D.WU.W/Q.DU.D}.
Reviewed-by: Richard Henderson
Signed-off-by: Song Gao
---
target/loongarch/disas.c| 34 ++
target/loongarch/helper.h
On 20/04/2023 09.57, Philippe Mathieu-Daudé wrote:
Hi Kautuk,
On 19/4/23 11:22, Kautuk Consul wrote:
Commit c0c8687ef0fd990db8db1655a8a6c5a5e35dd4bb disabled the
boot_linux.py test-case due to which the code coverage for ppc
decreased by around 2%. As per the discussion on
https://lore.kernel.o
This patch includes:
- VSLL[I].{B/H/W/D};
- VSRL[I].{B/H/W/D};
- VSRA[I].{B/H/W/D};
- VROTR[I].{B/H/W/D}.
Reviewed-by: Richard Henderson
Signed-off-by: Song Gao
---
target/loongarch/disas.c| 36 +
target/loongarch/insn_trans/trans_lsx.c.inc | 36 +
On Thu, Apr 20, 2023 at 1:25 PM Pei Li wrote:
>
> Hi all,
>
> My bad, I just submitted the kernel patch.
Please cc maintainers. You can get it via scripts/get_maintainer.pl
> If we are passing some generic command, still we have to add an additional
> field in the structure to indicate what is
On 19/4/23 19:28, Stefan Hajnoczi wrote:
Add a helper function to check whether the device is realized without
requiring the Big QEMU Lock. The next patch adds a second caller. The
goal is to avoid spreading DeviceState field accesses throughout the
code.
Suggested-by: Philippe Mathieu-Daudé
Si
On 19/4/23 19:28, Stefan Hajnoczi wrote:
The VuServer object has a refcount field and ref/unref APIs. The name is
confusing because it's actually an in-flight request counter instead of
a refcount.
Normally a refcount destroys the object upon reaching zero. The VuServer
counter is used to wake u
On 19/4/23 18:34, Juan Quintela wrote:
Signed-off-by: Juan Quintela
---
MAINTAINERS | 1 +
1 file changed, 1 insertion(+)
Reviewed-by: Philippe Mathieu-Daudé
On Fri, 14 Apr 2023 10:33:58 -0500
Eric Blake wrote:
> Consider what happens when performing a migration between two host
> machines connected to an NFS server serving multiple block devices to
> the guest, when the NFS server becomes unavailable. The migration
> attempts to inactivate all block
On Thu, 20 Apr 2023 at 01:17, Eugenio Perez Martin wrote:
>
> On Wed, Apr 19, 2023 at 1:50 PM Hawkins Jiawei wrote:
> >
> > This patchset allows QEMU to poll and check the device used buffer
> > after sending all SVQ control commands, instead of polling and checking
> > immediately after sending
On Thu, 20 Apr 2023 01:52:28 +0300
Vladimir Sementsov-Ogievskiy wrote:
> Hi all!
>
> COLO substem seems to be useless when CONFIG_REPLICATION is unset, as we
> simply don't allow to set x-colo capability in this case. So, let's not
> compile in unreachable code and interface we cannot use when
>
On Wed, Apr 19, 2023 at 05:49:55PM -0700, Sean Christopherson wrote:
> On Wed, Apr 19, 2023, Christian Brauner wrote:
> > On Thu, Apr 13, 2023 at 03:28:43PM -0700, Sean Christopherson wrote:
> > > > But if you want to preserve the inode number and device number of the
> > > > relevant tmpfs instanc
On 19/4/23 17:16, Mark Cave-Ayland wrote:
In order to facilitate a conversion of MemoryRegionPortioList to a QOM object
move the allocation of MemoryRegionPortioList ports to the heap instead of
using a variable-length member at the end of the MemoryRegionPortioList
structure.
Signed-off-by: Mar
On 20.04.23 11:33, Lukas Straub wrote:
On Thu, 20 Apr 2023 01:52:28 +0300
Vladimir Sementsov-Ogievskiy wrote:
Hi all!
COLO substem seems to be useless when CONFIG_REPLICATION is unset, as we
simply don't allow to set x-colo capability in this case. So, let's not
compile in unreachable code an
On 19/4/23 17:16, Mark Cave-Ayland wrote:
The aim of QOMification is so that the lifetime of the MemoryRegionPortioList
structure can be managed using QOM's in-built refcounting instead of having to
handle this manually.
Due to the use of an opaque pointer it isn't possible to model the new
TYPE
On 19/4/23 14:48, Thomas Huth wrote:
The "optarg" parameter is completely unused, so let's drop it.
Signed-off-by: Thomas Huth
---
include/exec/cpu-common.h | 2 +-
cpu.c | 2 +-
softmmu/vl.c | 2 +-
3 files changed, 3 insertions(+), 3 deletions(-)
Review
On 17/4/23 18:40, Peter Maydell wrote:
The HMP 'singlestep' command, the QMP 'query-status' command and the
HMP 'info status' command (which is just wrapping the QMP command
implementation) look at the 'singlestep' global variable. Make them
access the new TCG accelerator 'one-insn-per-tb' proper
On 17/4/23 18:40, Peter Maydell wrote:
The only place left that looks at the old 'singlestep' global
variable is the TCG curr_cflags() function. Replace the old global
with a new 'one_insn_per_tb' which is defined in tcg-all.c and
declared in accel/tcg/internal.h. This keeps it restricted to th
On 17/4/23 18:40, Peter Maydell wrote:
Document that the -singlestep command line option is now
deprecated, as it is replaced by either the TCG accelerator
property 'one-insn-per-tb' for system emulation or the new
'-one-insn-per-tb' option for usermode emulation, and remove
the only use of the d
On Mon, 2023-04-03 at 18:28 +0200, Pierre Morel wrote:
> The topology information are attributes of the CPU and are
> specified during the CPU device creation.
>
> On hot plug we:
> - calculate the default values for the topology for drawers,
> books and sockets in the case they are not specifie
On Thu, Apr 20, 2023 at 7:25 AM Pei Li wrote:
>
> Hi all,
>
> My bad, I just submitted the kernel patch. If we are passing some generic
> command, still we have to add an additional field in the structure to
> indicate what is the unbatched version of this command, and the struct
> vhost_ioctls
On Wed, Apr 19, 2023 at 03:07:19PM -0400, Peter Xu wrote:
> On Wed, Apr 19, 2023 at 06:12:05PM +0100, Daniel P. Berrangé wrote:
> > On Tue, Apr 18, 2023 at 03:26:45PM -0400, Peter Xu wrote:
> > > On Tue, Apr 18, 2023 at 05:58:44PM +0100, Daniel P. Berrangé wrote:
> > > > Libvirt has multiple APIs w
On 17/4/23 18:40, Peter Maydell wrote:
Currently we report whether the TCG accelerator is in
'one-insn-per-tb' mode in the 'info status' output. This is a pretty
minor piece of TCG specific information, and we want to deprecate the
'singlestep' field of the associated QMP command. Move the
'one
On 17/4/23 18:40, Peter Maydell wrote:
The 'singlestep' HMP command is confusing, because it doesn't
actually have anything to do with single-stepping the CPU. What it
does do is force TCG emulation to put one guest instruction in each
TB, which can be useful in some situations.
Create a new HM
On 17/4/23 18:40, Peter Maydell wrote:
The run-state.json file is missing a trailing newline; add it.
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
---
Noticed this because my editor wanted to add the newline
when I touched the file for the following patch...
---
qapi/run-state
On 17/4/23 18:40, Peter Maydell wrote:
The 'singlestep' member of StatusInfo has never done what the QMP
documentation claims it does. What it actually reports is whether
TCG is working in "one guest instruction per translation block" mode.
We no longer need this field for the HMP 'info status'
> -Original Message-
> From: Vladimir Sementsov-Ogievskiy
> Sent: Thursday, April 20, 2023 6:53 AM
> To: qemu-devel@nongnu.org
> Cc: qemu-bl...@nongnu.org; michael.r...@amd.com; arm...@redhat.com;
> ebl...@redhat.com; jasow...@redhat.com; quint...@redhat.com; Zhang,
> Hailiang ; phi...@
On 4/19/23 20:37, Alistair Francis wrote:
On Tue, Apr 18, 2023 at 12:08 AM Daniel Henrique Barboza
wrote:
This setter is doing nothing else but setting env->vext_ver. Assign the
value directly.
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: LIU Zhiwei
Reviewed-by: Weiwei Li
I thi
On 2023/04/17 18:51, Tomasz Dzieciol wrote:
Packet-split descriptors are used by Linux VF driver for MTU values from 2048
upwards.
Please rebase to:
https://patchew.org/QEMU/20230420054657.50367-1-akihiko.od...@daynix.com/
And add a cover letter with the following lines:
Based-on: <20230420054
On 17/4/23 18:40, Peter Maydell wrote:
The '-singlestep' option is confusing, because it doesn't actually
have anything to do with single-stepping the CPU. What it does do
is force TCG emulation to put one guest instruction in each TB,
which can be useful in some situations.
Create a new command
On 17/4/23 18:40, Peter Maydell wrote:
The '-singlestep' option is confusing, because it doesn't actually
have anything to do with single-stepping the CPU. What it does do
is force TCG emulation to put one guest instruction in each TB,
which can be useful in some situations.
Create a new command
On 17/4/23 19:44, Alex Bennée wrote:
John Snow writes:
On Mon, Apr 17, 2023 at 9:43 AM Alex Bennée wrote:
From: Kautuk Consul
Avocado version 101.0 has a fix to re-compute the checksum
of an asset file if the algorithm used in the *-CHECKSUM
file isn't the same as the one being passed to
On Thu, 20 Apr 2023 at 10:13, Philippe Mathieu-Daudé wrote:
>
> On 17/4/23 18:40, Peter Maydell wrote:
> > The '-singlestep' option is confusing, because it doesn't actually
> > have anything to do with single-stepping the CPU. What it does do
> > is force TCG emulation to put one guest instructio
On 17/4/23 15:43, Alex Bennée wrote:
From: Thomas Huth
We're currently facing the problem that the device-crash-test script
runs twice as long in the CI when a runner supports KVM - which sometimes
results in a timeout of the CI job. To get a more deterministic runtime
here, add an option to th
(--- Re-sending because Alistair's acks from v6 were missing ---)
Hi,
In this v7 we have three extra patches:
- patch 4 [1] and 5 [2], both from Weiwei Li, addresses an issue that
we're going to have with Zca and RVC if we push the priv spec
disabling code to the end of validation. More details
On Thu, 20 Apr 2023 at 04:13, Duan, Zhenzhong wrote:
> >From: Peter Maydell
> >Question: is it OK for an implementation of this method to call the notifier
> >for
> >translations that are in the IOMMU and which are not in the scope of the
> >notifier (ie which are outside the intersection) ? Or
This setter is doing nothing else but setting env->vext_ver. Assign the
value directly.
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: LIU Zhiwei
Reviewed-by: Weiwei Li
Reviewed-by: Alistair Francis
---
target/riscv/cpu.c | 7 +--
1 file changed, 1 insertion(+), 6 deletions(-)
diff
write_misa() must use as much common logic as possible. We want to open
code just the bits that are exclusive to the CSR write operation and TCG
internals.
Our validation is done with riscv_cpu_validate_set_extensions(), but we
need a small tweak first. When enabling RVG we're doing:
env-
Static CPUs don't want their extensions changed by user interaction. We
can prevent it during init by not exposing user facing properties, but
write_misa() is also capable of disabling/enabling extension during
runtime.
We have a way of telling whether a CPU is static or not by checking for
TYPE_R
We have 4 config settings being done in riscv_cpu_init(): ext_ifencei,
ext_icsr, mmu and pmp. This is also the constructor of the "riscv-cpu"
device, which happens to be the parent device of every RISC-V cpu.
The result is that these 4 configs are being set every time, and every
other CPU should a
The RVV verification will error out if fails and it's being done at the
end of riscv_cpu_validate_set_extensions(), after we've already set some
extensions that are dependent on RVV. Let's put it in its own function
and do it earlier.
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: LIU Zhiwe
From: Weiwei Li
Using implicitly enabled extensions such as Zca/Zcf/Zcd instead of their
super extensions can simplify the extension related check. However, they
may have higher priv version than their super extensions. So we should mask
them in the isa_string based on priv version to make them i
Let's remove more code that is open coded in riscv_cpu_realize() and put
it into a helper. Let's also add an error message instead of just
asserting out if env->misa_mxl_max != env->misa_mlx.
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: LIU Zhiwei
Reviewed-by: Weiwei Li
Reviewed-by: Alis
The setter is doing nothing special. Just set env->priv_ver directly.
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: LIU Zhiwei
Reviewed-by: Weiwei Li
Reviewed-by: Alistair Francis
---
target/riscv/cpu.c | 29 -
1 file changed, 12 insertions(+), 17 deletions(-
There is no need to init timers if we're not even sure that our
extensions are valid. Execute riscv_cpu_validate_set_extensions() before
riscv_timer_init().
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: LIU Zhiwei
Reviewed-by: Weiwei Li
Reviewed-by: Alistair Francis
---
target/riscv/cpu
On 18/04/2023 17:21, Alex Bennée wrote:
I'm still not sure how I achieve by use case of the parent class
defining the following properties:
static Property vud_properties[] = {
DEFINE_PROP_CHR("chardev", VHostUserDevice, chardev),
DEFINE_PROP_UINT16("id", VHostUserDevice, id, 0
All these generic CPUs are using the latest priv available, at this
moment PRIV_VERSION_1_12_0:
- riscv_any_cpu_init()
- rv32_base_cpu_init()
- rv64_base_cpu_init()
- rv128_base_cpu_init()
Create a new PRIV_VERSION_LATEST enum and use it in those cases. I'll
make it easier to update everything at
From: Weiwei Li
Even though Zca/Zcf/Zcd can be included by C/F/D, however, their priv
version is higher than the priv version of C/F/D. So if we use check
for them instead of check for C/F/D totally, it will trigger new
problem when we try to disable the extensions based on the configured
priv ve
We're doing env->priv_spec validation and assignment at the start of
riscv_cpu_realize(), which is fine, but then we're doing a force disable
on extensions that aren't compatible with the priv version.
This second step is being done too early. The disabled extensions might be
re-enabled again in r
On 17/4/23 18:23, Vaibhav Jain wrote:
Since commit fd8171fe52b5e("target/hexagon: import lexer for idef-parser") the
hexagon target uses 'flex', 'bison' to generate idef-parser. However default
travis builder image for 'focal' may not have these pre-installed, consequently
following error is seen
On 18/04/2023 17:21, Alex Bennée wrote:
These are useful functions for when you want proper inheritance of
functionality across realize/unrealize calls.
Signed-off-by: Alex Bennée
---
include/hw/qdev-core.h | 27 +++
1 file changed, 27 insertions(+)
diff --git a/inc
1 - 100 of 607 matches
Mail list logo
