On 2023/4/18 14:09, Weiwei Li wrote:
On 2023/4/18 13:18, LIU Zhiwei wrote:
On 2023/4/18 11:05, Weiwei Li wrote:
On 2023/4/18 10:53, Alistair Francis wrote:
On Thu, Apr 13, 2023 at 7:04 PM Weiwei Li
wrote:
Not only the matched PMP entry, Any PMP entry that overlap with
partial of
the tlb
On 18/04/2023 07.53, Kautuk Consul wrote:
Commit c0c8687ef0fd990db8db1655a8a6c5a5e35dd4bb disabled the
boot_linux.py test-case due to which the code coverage for ppc
decreased by around 2%. As per the discussion on
https://lore.kernel.org/qemu-devel/87sfdpqcy4@linaro.org/ it
was mentioned tha
On 2023/4/13 17:01, Weiwei Li wrote:
TLB should be flushed not only for pmpcfg csr changes, but also for
pmpaddr csr changes.
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
---
target/riscv/pmp.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/riscv/pmp.c b/target/riscv/
On 17/04/2023 15.43, Alex Bennée wrote:
From: Kautuk Consul
Avocado version 101.0 has a fix to re-compute the checksum
of an asset file if the algorithm used in the *-CHECKSUM
file isn't the same as the one being passed to it by the
avocado user (i.e. the avocado_qemu python module).
In the ear
On 2023/4/13 17:01, Weiwei Li wrote:
TLB needn't be flushed when pmpcfg/pmpaddr don't changes.
If we flush the tlb in pmp_update_rules, we don't need this patch.
Zhiwei
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
---
target/riscv/pmp.c | 24
1 file
On 4/17/23 18:25, Daniel Henrique Barboza wrote:
On 4/13/23 06:01, Weiwei Li wrote:
When PMP entry overlap part of the page, we'll set the tlb_size to 1, and
this will make the address set with TLB_INVALID_MASK to make the page
un-cached. However, if we clear TLB_INVALID_MASK when TLB is re-fi
On 2023/4/13 17:01, Weiwei Li wrote:
The translation block may also be affected when PMP entry changes.
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
---
target/riscv/pmp.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
index aced23c
Hi
On Wed, Mar 22, 2023 at 6:42 PM Philippe Mathieu-Daudé
wrote:
> On 22/3/23 14:27, Stefan Hajnoczi wrote:
> > On Wed, Mar 22, 2023 at 08:11:37AM +0100, Thomas Huth wrote:
> >> On 21/03/2023 17.16, Cédric Le Goater wrote:
> >>> From: Cédric Le Goater
> >>>
> >>> GCC13 reports an error :
> >>>
On 18/04/2023 08.28, Volker Rümelin wrote:
Windows sends an extra left control key up/down input event for
every right alt key up/down input event for keyboards with
international layout. Since commit 830473455f ("ui/sdl2: fix
handling of AltGr key on Windows") QEMU uses a Windows low level
keybo
On 4/18/23 09:18, Richard Henderson wrote:
- /*
- * With PAGE_WRITE_INV, we set TLB_INVALID_MASK immediately,
- * to force the next access through tlb_fill. We've just
- * called tlb_fill, so we know that this entry *is* valid.
- */
-
"you.chen" wrote:
> Add config and logics to use qatzip for page compression, in order to
> support qatzip compression better, we collect multipe pages together
> to do qatzip compression for best performance.
> And we use compile option CONFIG_QATZIP to determine whether should qatzip
> related
Before changing the flow check for sv39/48/57.
According to specification (for Supervisor mode):
Sv39 implementations support a 39-bit virtual address space, divided into 4 KiB
pages.
Instruction fetch addresses and load and store effective addresses, which are
64 bits,
must have bits 63–39 all
On Mon, Apr 17, 2023 at 9:21 PM Stefan Hajnoczi wrote:
>
> On Mon, 17 Apr 2023 at 15:08, Eugenio Perez Martin
> wrote:
> >
> > On Mon, Apr 17, 2023 at 7:14 PM Stefan Hajnoczi wrote:
> > >
> > > On Thu, Apr 13, 2023 at 12:14:24PM +0200, Eugenio Perez Martin wrote:
> > > > On Wed, Apr 12, 2023 at
On 2023/4/18 15:08, LIU Zhiwei wrote:
On 2023/4/18 14:09, Weiwei Li wrote:
On 2023/4/18 13:18, LIU Zhiwei wrote:
On 2023/4/18 11:05, Weiwei Li wrote:
On 2023/4/18 10:53, Alistair Francis wrote:
On Thu, Apr 13, 2023 at 7:04 PM Weiwei Li
wrote:
Not only the matched PMP entry, Any PMP ent
On 4/17/23 18:40, Peter Maydell wrote:
The only place left that looks at the old 'singlestep' global
variable is the TCG curr_cflags() function. Replace the old global
with a new 'one_insn_per_tb' which is defined in tcg-all.c and
declared in accel/tcg/internal.h. This keeps it restricted to th
On 4/17/23 18:40, Peter Maydell wrote:
@@ -219,8 +221,8 @@ static void tcg_set_one_insn_per_tb(Object *obj, bool
value, Error **errp)
{
TCGState *s = TCG_STATE(obj);
s->one_insn_per_tb = value;
-/* For the moment, set the global also: this changes the behaviour */
-singlest
On 4/17/23 18:40, Peter Maydell wrote:
Currently we report whether the TCG accelerator is in
'one-insn-per-tb' mode in the 'info status' output. This is a pretty
minor piece of TCG specific information, and we want to deprecate the
'singlestep' field of the associated QMP command. Move the
'one
On 4/17/23 18:40, Peter Maydell wrote:
The 'singlestep' member of StatusInfo has never done what the QMP
documentation claims it does. What it actually reports is whether
TCG is working in "one guest instruction per translation block" mode.
We no longer need this field for the HMP 'info status'
On Mon, Apr 17, 2023 at 9:33 PM Stefan Hajnoczi wrote:
>
> On Mon, 17 Apr 2023 at 15:10, Eugenio Perez Martin
> wrote:
> >
> > On Mon, Apr 17, 2023 at 5:38 PM Stefan Hajnoczi wrote:
> > >
> > > On Thu, Apr 13, 2023 at 12:14:24PM +0200, Eugenio Perez Martin wrote:
> > > > On Wed, Apr 12, 2023 at
On 4/17/23 15:58, Lawrence Hunter wrote:
From: Kiran Ostrolenk
Factor the non SEW-specific stuff out of `GEN_OPIVV_TRANS` into
function `opivv_trans` (similar to `opivi_trans`). `opivv_trans` will be
used in proceeding vector-crypto commits.
Signed-off-by: Kiran Ostrolenk
---
target/riscv/i
On 2023/4/18 15:11, LIU Zhiwei wrote:
On 2023/4/13 17:01, Weiwei Li wrote:
TLB should be flushed not only for pmpcfg csr changes, but also for
pmpaddr csr changes.
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
---
target/riscv/pmp.c | 1 +
1 file changed, 1 insertion(+)
diff --
On 4/17/23 15:58, Lawrence Hunter wrote:
From: Nazar Kazakov
Move the checks out of `do_opiv{v,x,i}_gvec{,_shift}` functions
and into the corresponding macros. This enables the functions to be
reused in proceeding commits without check duplication.
Signed-off-by: Nazar Kazakov
---
target/risc
On Mon, Apr 17, 2023 at 11:02:00PM +, Singh, Satyeshwar wrote:
> In a multi-seat scenario where multiple keyboards and mice are connected
> to the host but some are dedicated for the guests only (through pass
> through mode) and some are only for the host, there is a strong use case
> where a c
On 4/17/23 15:58, Lawrence Hunter wrote:
From: Dickon Hood
Zvbb (implemented in later commit) has a widening instruction, which
requires an extra check on the enabled extensions. Refactor
GEN_OPIVX_WIDEN_TRANS() to take a check function to avoid reimplementing
it.
Signed-off-by: Dickon Hood
--
On 2023/4/18 15:36, Richard Henderson wrote:
On 4/18/23 09:18, Richard Henderson wrote:
- /*
- * With PAGE_WRITE_INV, we set TLB_INVALID_MASK
immediately,
- * to force the next access through tlb_fill. We've just
- * called tlb_fill, so we know
On 4/17/23 15:58, Lawrence Hunter wrote:
From: Dickon Hood
Rotates have been fixed up to only allow for reasonable rotate amounts
(ie, no rotates >7 on an 8b value etc.) This fixes a problem with riscv
vector rotate instructions.
Signed-off-by: Dickon Hood
---
include/qemu/bitops.h | 24
On 4/17/23 15:58, Lawrence Hunter wrote:
From: Kiran Ostrolenk
This is for use in the RISC-V vclz and vctz instructions (implemented in
proceeding commit).
Signed-off-by: Kiran Ostrolenk
---
include/qemu/host-utils.h | 54 +++
1 file changed, 54 insertions
On 4/17/23 15:58, Lawrence Hunter wrote:
diff --git a/accel/tcg/tcg-runtime-gvec.c b/accel/tcg/tcg-runtime-gvec.c
index ac7d28c251e..322dcc0687f 100644
--- a/accel/tcg/tcg-runtime-gvec.c
+++ b/accel/tcg/tcg-runtime-gvec.c
@@ -550,6 +550,17 @@ void HELPER(gvec_ands)(void *d, void *a, uint64_t b,
On 4/17/23 15:58, Lawrence Hunter wrote:
From: Max Chou
- Share sm4_subword between different targets.
Signed-off-by: Max Chou
Reviewed-by: Frank Chang
---
include/crypto/sm4.h | 8
target/arm/tcg/crypto_helper.c | 10 ++
2 files changed, 10 insertions(+), 8
On Fri, Apr 07, 2023 at 11:25:14AM +0200, David Turner wrote:
> I meant glibc-2.17, I am using a sysroot to ensure the generated binaries
> run on older Linux distributions.
I think that would be considered an unsupported buld configuration
from QEMU's POV. Our platform policy is declared here:
On Wed, Apr 05, 2023 at 11:42:56AM +0200, Igor Mammedov wrote:
> with Q35 using ACPI PCI hotplug by default, user's request to unplug
> device is ignored when it's issued before guest OS has been booted.
> And any additional attempt to request device hot-unplug afterwards
> results in following err
On Mon, 2023-04-03 at 18:28 +0200, Pierre Morel wrote:
> S390 adds two new SMP levels, drawers and books to the CPU
> topology.
> The S390 CPU have specific topology features like dedication
> and entitlement to give to the guest indications on the host
> vCPUs scheduling and help the guest take th
On Thu, Apr 06, 2023 at 07:20:41PM +0800, Bin Meng wrote:
> Current codes using a brute-force traversal of all file descriptors
> do not scale on a system where the maximum number of file descriptors
> are set to a very large value (e.g.: in a Docker container of Manjaro
> distribution it is set to
Hi Alistair,
Sorry for the late reply, I was on PTO.
On Tue, Apr 18, 2023 at 4:22 AM Alistair Francis wrote:
>
> On Mon, Apr 17, 2023 at 8:47 PM Andrea Parri wrote:
> >
> > Hi Alistair,
> >
> > > > @@ -936,6 +936,11 @@ restart:
> > > > return TRANSLATE_FAIL;
> > > > }
> >
Hi Igor,
On 4/13/23 7:21 PM, Igor Mammedov wrote:
On Thu, 13 Apr 2023 13:50:57 +0800
Gavin Shan wrote:
On 4/12/23 7:42 PM, Peter Maydell wrote:
On Wed, 12 Apr 2023 at 02:08, Gavin Shan wrote:
On 3/27/23 9:26 PM, Igor Mammedov wrote:
On Fri, 17 Mar 2023 14:25:39 +0800
Gavin Shan wrote:
W dniu 15.04.2023 o 10:28, Jisheng Zhang pisze:
Enable the Cortex-A78 for virt to use a CPU type on the virt
board that models a specific real hardware CPU, rather than
have to use the QEMU-specific "max" CPU type.
You can use 'neoverse-n1' to have a specific real hardware CPU.
Copying Stefan as the trace subsystem maintainer
On Fri, Apr 07, 2023 at 10:04:10PM -0300, casan...@redhat.com wrote:
> From: Carlos Santos
>
> It is not useful when configuring with --enable-trace-backends=nop.
>
> Signed-off-by: Carlos Santos
> ---
> Changes v1->v2:
> Install based on chos
Hi, Richard
在 2023/4/4 上午11:39, Richard Henderson 写道:
On 3/27/23 20:06, Song Gao wrote:
+static bool trans_vldi(DisasContext *ctx, arg_vldi *a)
+{
+ int sel, vece;
+ uint64_t value;
+ CHECK_SXE;
+
+ sel = (a->imm >> 12) & 0x1;
+
+ if (sel) {
+ /* VSETI.D */
+ value
with Q35 using ACPI PCI hotplug by default, user's request to unplug
device is ignored when it's issued before guest OS has been booted.
And any additional attempt to request device hot-unplug afterwards
results in following error:
"Device XYZ is already in the process of unplug"
arguably it ca
On 4/17/23 16:32, Olaf Hering wrote:
Mon, 17 Apr 2023 14:46:54 +0200 Peter Krempa:
Switch the dockerfile to 15.4.
Given that Leap 15.5 is essentially done, please skip this meanwhile
stale version of Leap.
The reason to do this update is to be able to update libvirt-ci, if
needed for other
On 4/17/23 14:46, Peter Krempa wrote:
Update to commit which has fixes needed for OpenSUSE 15.4 and
re-generate output files.
Signed-off-by: Peter Krempa
---
.gitlab-ci.d/cirrus/freebsd-12.vars | 16 ++
.gitlab-ci.d/cirrus/freebsd-13.vars | 16 ++
.gitlab-ci.d/cirrus/ma
> On 30.07.20 17:58, Michael S. Tsirkin wrote:
> > macOS uses ACPI UIDs to build the DevicePath for NVRAM boot options,
> > while OVMF firmware gets them via an internal channel through QEMU.
> > Due to a bug in QEMU ACPI currently UEFI firmware and ACPI have
> > different values, and this makes th
On Mon, Apr 17, 2023 at 02:46:53PM +0200, Peter Krempa wrote:
> Update to commit which has fixes needed for OpenSUSE 15.4 and
> re-generate output files.
>
> Signed-off-by: Peter Krempa
> ---
> .gitlab-ci.d/cirrus/freebsd-12.vars | 16 ++
> .gitlab-ci.d/cirrus/freebsd-13.vars
On Mon, Apr 17, 2023 at 04:32:58PM +0200, Olaf Hering wrote:
> Mon, 17 Apr 2023 14:46:54 +0200 Peter Krempa :
>
> > Switch the dockerfile to 15.4.
>
> Given that Leap 15.5 is essentially done, please skip this meanwhile stale
> version of Leap.
15.4 is still the active release and doesn't have
On Tue, 18 Apr 2023 at 09:05, Richard Henderson
wrote:
>
> On 4/17/23 18:40, Peter Maydell wrote:
> > @@ -219,8 +221,8 @@ static void tcg_set_one_insn_per_tb(Object *obj, bool
> > value, Error **errp)
> > {
> > TCGState *s = TCG_STATE(obj);
> > s->one_insn_per_tb = value;
> > -/
On 4/18/23 10:53, Nina Schoetterl-Glausch wrote:
On Mon, 2023-04-03 at 18:28 +0200, Pierre Morel wrote:
S390 adds two new SMP levels, drawers and books to the CPU
topology.
The S390 CPU have specific topology features like dedication
and entitlement to give to the guest indications on the host
On Mon, Apr 17, 2023 at 9:46 PM Stefan Hajnoczi wrote:
>
> On Mon, 17 Apr 2023 at 15:12, Eugenio Perez Martin
> wrote:
> >
> > On Mon, Apr 17, 2023 at 9:08 PM Stefan Hajnoczi wrote:
> > >
> > > On Mon, 17 Apr 2023 at 14:56, Eugenio Perez Martin
> > > wrote:
> > > >
> > > > On Mon, Apr 17, 202
On Thu, 13 Apr 2023 at 12:12, Zhenzhong Duan wrote:
>
> On x86, there are two notifiers registered due to vtd-ir memory
> region splitting the entire address space. During replay of the
> address space for each notifier, the whole address space is
> scanned which is unnecessary. We only need to sc
On 18/04/2023 12.01, Pierre Morel wrote:
On 4/18/23 10:53, Nina Schoetterl-Glausch wrote:
On Mon, 2023-04-03 at 18:28 +0200, Pierre Morel wrote:
S390 adds two new SMP levels, drawers and books to the CPU
topology.
The S390 CPU have specific topology features like dedication
and entitlement to
Hi Juan,
Sorry for the late reply, I won't be able to attend this afternoon's meeting.
Regards,
Phil.
On Thu, 13 Apr 2023 at 22:55, Juan Quintela wrote:
>
>
> Hi
>
> Please, send any topic that you are interested in covering.
>
> [google calendar is very, very bad to compose messages, but gett
On 4/14/23 18:04, Peter Maydell wrote:
Bit 63 in a Table descriptor is only the NSTable bit for stage 1
translations; in stage 2 it is RES0. We were incorrectly looking at
it all the time.
This causes problems if:
* the stage 2 table descriptor was incorrectly setting the RES0 bit
* we are
在 2023/4/7 3:22, Niek Linnenbank 写道:
Hi Qianfan Zhao,
Is this change really needed as a separate patch?
Looks like it would make sense just to squash it with the original
patch 01?
The class type of TYPE_AW_SDHOST_SUN50I_A64 was introduced when patch-07.
Add patch-01 doesn't has that class.
在 2023/4/7 4:18, Niek Linnenbank 写道:
On Tue, Mar 28, 2023 at 7:47 AM wrote:
From: qianfan Zhao
A64's sd register was similar to H3, and it introduced a new register
named SAMP_DL_REG location at 0x144. The dma descriptor buffer size of
mmc2 is only 8K and the other mmc co
On 12/04/2023 16.19, Juan Quintela wrote:
Since commit:
commit 1bfc8dde505f1e6a92697c52aa9b09e81b54c78f
Author: Dr. David Alan Gilbert
Date: Mon Mar 6 15:26:12 2023 +
tests/migration: Tweek auto converge limits check
Thomas found an autoconverge test failure where the
mig
On 4/14/23 18:04, Peter Maydell wrote:
+/* Check if page table walk is to secure or non-secure PA space. */
+ptw->out_secure = (is_secure
+ && !(pte_secure
+? env->cp15.vstcr_el2 & VSTCR_SW
+
On 4/14/23 18:04, Peter Maydell wrote:
In get_phys_addr_twostage() when we set up the stage 2 translation,
we currently incorrectly set all of in_mmu_idx, in_ptw_idx and
in_secure based on s2walk_secure.
Here s2walk_secure is true if we should be doing this stage 2
walk to physical memory. ipa_s
On Tue, Apr 18, 2023 at 10:47 AM Daniel P. Berrangé
wrote:
> On Fri, Apr 07, 2023 at 11:25:14AM +0200, David Turner wrote:
> > I meant glibc-2.17, I am using a sysroot to ensure the generated binaries
> > run on older Linux distributions.
>
> I think that would be considered an unsupported buld c
From: qianfan Zhao
The CCU provides the registers to program the PLLs and the controls
most of the clock generation, division, distribution, synchronization
and gating.
This commit adds support for the Clock Control Unit which emulates
a simple read/write register interface.
Signed-off-by: qian
From: qianfan Zhao
Allwinner R40 (sun8i) SoC features a Quad-Core Cortex-A7 ARM CPU,
and a Mali400 MP2 GPU from ARM. It's also known as the Allwinner T3
for In-Car Entertainment usage, A40i and A40pro are variants that
differ in applicable temperatures range (industrial and military).
Signed-off
From: qianfan Zhao
R40 has eight UARTs, support both 16450 and 16550 compatible modes.
Signed-off-by: qianfan Zhao
---
hw/arm/allwinner-r40.c | 31 ---
include/hw/arm/allwinner-r40.h | 8
2 files changed, 36 insertions(+), 3 deletions(-)
diff --gi
From: qianfan Zhao
R40 has two ethernet controllers named as emac and gmac. The emac is
compatibled with A10, and the GMAC is compatibled with H3.
Signed-off-by: qianfan Zhao
---
hw/arm/allwinner-r40.c | 50 --
hw/arm/bananapi_m2u.c | 3 ++
inc
From: qianfan Zhao
This patch adds minimal support for AXP-221 PMU and connect it to
bananapi M2U board.
Signed-off-by: qianfan Zhao
---
hw/arm/Kconfig| 3 +-
hw/arm/bananapi_m2u.c | 6 +
hw/misc/Kconfig | 2 +-
hw/misc/axp209.c | 238 --
From: qianfan Zhao
Types of memory that the SDRAM controller supports are DDR2/DDR3
and capacities of up to 2GiB. This commit adds emulation support
of the Allwinner R40 SDRAM controller.
This driver only support 256M, 512M and 1024M memory now.
Signed-off-by: qianfan Zhao
---
hw/arm/allwinne
From: qianfan Zhao
TWI(i2c) is designed to be used as an interface between CPU host and the
serial 2-Wire bus. It can support all standard 2-Wire transfer, can be
operated in standard mode(100kbit/s) or fast-mode, supporting data rate
up to 400kbit/s.
Signed-off-by: qianfan Zhao
---
hw/arm/all
From: qianfan Zhao
A64's sd register was similar to H3, and it introduced a new register
named SAMP_DL_REG location at 0x144. The dma descriptor buffer size of
mmc2 is only 8K and the other mmc controllers has 64K.
Also fix allwinner-r40's mmc controller type.
Signed-off-by: qianfan Zhao
---
From: qianfan Zhao
Add test case for booting from initrd and sd card.
Signed-off-by: qianfan Zhao
---
tests/avocado/boot_linux_console.py | 176
1 file changed, 176 insertions(+)
diff --git a/tests/avocado/boot_linux_console.py
b/tests/avocado/boot_linux_console.
From: qianfan Zhao
Only a few important registers are added, especially the SRAM_VER
register.
Signed-off-by: qianfan Zhao
---
hw/arm/Kconfig| 1 +
hw/arm/allwinner-r40.c| 7 +-
hw/misc/Kconfig | 3 +
hw/misc/allwinner-sramc.c | 1
From: qianfan Zhao
*** history ***
# v1: 2023-03-21
The first version which add allwinner-r40 support, supported features:
+ ccu
+ dram controller
+ uart
+ i2c and pmic(axp221)
+ sdcard
+ emac/gmac
Also provide a test case under avocado, running quickly test:
$ AVOCADO_ALLOW_LARGE_STORAGE=ye
From: qianfan Zhao
Add documents for Banana Pi M2U
Signed-off-by: qianfan Zhao
---
docs/system/arm/bananapi_m2u.rst | 138 +++
1 file changed, 138 insertions(+)
create mode 100644 docs/system/arm/bananapi_m2u.rst
diff --git a/docs/system/arm/bananapi_m2u.rst b/doc
On Tue, 18 Apr 2023 at 12:01, Richard Henderson
wrote:
>
> On 4/14/23 18:04, Peter Maydell wrote:
> > +/* Check if page table walk is to secure or non-secure PA space. */
> > +ptw->out_secure = (is_secure
> > + && !(pte_secure
> > +
On Tue, 18 Apr 2023, Igor Mammedov wrote:
> with Q35 using ACPI PCI hotplug by default, user's request to unplug
> device is ignored when it's issued before guest OS has been booted.
> And any additional attempt to request device hot-unplug afterwards
> results in following error:
>
> "Device
Thomas Huth wrote:
> On 12/04/2023 16.19, Juan Quintela wrote:
>> Since commit:
>> commit 1bfc8dde505f1e6a92697c52aa9b09e81b54c78f
>> Author: Dr. David Alan Gilbert
>> Date: Mon Mar 6 15:26:12 2023 +
>> tests/migration: Tweek auto converge limits check
>> Thomas found an autoconve
On Fri, 14 Apr 2023 at 17:04, Peter Maydell wrote:
>
> In get_phys_addr_twostage() when we set up the stage 2 translation,
> we currently incorrectly set all of in_mmu_idx, in_ptw_idx and
> in_secure based on s2walk_secure.
>
> Here s2walk_secure is true if we should be doing this stage 2
> walk t
Thomas Huth wrote:
> On 12/04/2023 16.19, Juan Quintela wrote:
>> Since commit:
>> commit 1bfc8dde505f1e6a92697c52aa9b09e81b54c78f
>> Author: Dr. David Alan Gilbert
>> Date: Mon Mar 6 15:26:12 2023 +
>> tests/migration: Tweek auto converge limits check
>> Thomas found an autoconve
On Wed, Apr 05, 2023 at 07:21:07PM +0200, David 'Digit' Turner wrote:
> The source file uses VIRTIO_F_VERSION_1 which is
> not defined by on Debian 10.
>
> The system-provided which
> does not include the macro definition is included
> through , so fix the issue by including
> the standard-heade
On Wed, Apr 12, 2023 at 04:20:00PM +0200, Juan Quintela wrote:
> Otherwise we do the 1st migration iteration at a too slow speed.
>
> Signed-off-by: Juan Quintela
> ---
> tests/qtest/migration-test.c | 3 +--
> 1 file changed, 1 insertion(+), 2 deletions(-)
>
> diff --git a/tests/qtest/migratio
On Wed, 15 Mar 2023 at 14:52, Guenter Roeck wrote:
>
> The SOC on i.MX6UL and i.MX7 has 2 Ethernet interfaces. The PHY on each may
> be connected to separate MDIO busses, or both may be connected on the same
> MDIO bus using different PHY addresses. Commit 461c51ad4275 ("Add a phy-num
> property t
Daniel P. Berrangé wrote:
> On Wed, Apr 12, 2023 at 04:20:00PM +0200, Juan Quintela wrote:
>> Otherwise we do the 1st migration iteration at a too slow speed.
>>
>> Signed-off-by: Juan Quintela
>> ---
>> tests/qtest/migration-test.c | 3 +--
>> 1 file changed, 1 insertion(+), 2 deletions(-)
>>
Add CSR_CPUID register in cpu_env to save the cpu_index
value.
Signed-off-by: Tianrui Zhao
---
target/loongarch/cpu.c | 1 +
target/loongarch/cpu.h | 1 +
target/loongarch/insn_trans/trans_privileged.c.inc | 8 +---
3 files changed, 3 i
On 4/18/23 12:15, Thomas Huth wrote:
On 18/04/2023 12.01, Pierre Morel wrote:
On 4/18/23 10:53, Nina Schoetterl-Glausch wrote:
On Mon, 2023-04-03 at 18:28 +0200, Pierre Morel wrote:
S390 adds two new SMP levels, drawers and books to the CPU
topology.
The S390 CPU have specific topology feat
From: Rahul Pathak
Add a virtual CPU for Ventana's first CPU named veyron-v1. It runs
exclusively for the rv64 target. It's tested with the 'virt' board.
CPU specs and general information can be found here:
https://www.nextplatform.com/2023/02/02/the-first-risc-v-shot-across-the-datacenter-bow/
On Tue, 2023-04-18 at 12:01 +0200, Pierre Morel wrote:
> On 4/18/23 10:53, Nina Schoetterl-Glausch wrote:
> > On Mon, 2023-04-03 at 18:28 +0200, Pierre Morel wrote:
> > > S390 adds two new SMP levels, drawers and books to the CPU
> > > topology.
> > > The S390 CPU have specific topology features li
Hi, Tianrui
在 2023/4/18 下午8:20, Tianrui Zhao 写道:
Add CSR_CPUID register in cpu_env to save the cpu_index
value.
Why do we need to do this?
For tcg mode, it is enough to use cpu_index. You need to explain the reason.
Thank.
Song Gao
Signed-off-by: Tianrui Zhao
---
target/loongarch/cpu.c
On 18/04/2023 13.42, Juan Quintela wrote:
Thomas Huth wrote:
On 12/04/2023 16.19, Juan Quintela wrote:
Since commit:
commit 1bfc8dde505f1e6a92697c52aa9b09e81b54c78f
Author: Dr. David Alan Gilbert
Date: Mon Mar 6 15:26:12 2023 +
tests/migration: Tweek auto converge limits check
在 2023年04月18日 20:40, Song Gao 写道:
Hi, Tianrui
在 2023/4/18 下午8:20, Tianrui Zhao 写道:
Add CSR_CPUID register in cpu_env to save the cpu_index
value.
Why do we need to do this?
For tcg mode, it is enough to use cpu_index. You need to explain the
reason.
Thank.
Song Gao
We prepare to add kv
Thomas Huth wrote:
> On 18/04/2023 13.42, Juan Quintela wrote:
>> Thomas Huth wrote:
>>> On 12/04/2023 16.19, Juan Quintela wrote:
Since commit:
commit 1bfc8dde505f1e6a92697c52aa9b09e81b54c78f
Author: Dr. David Alan Gilbert
Date: Mon Mar 6 15:26:12 2023 +
tes
After caching the device status and features, the latency is reduced by 0.059
sec.
Signed-off-by: Shao-Chien Chiang
---
hw/virtio/vhost-vdpa.c | 16 ++--
include/hw/virtio/vhost-vdpa.h | 2 ++
2 files changed, 12 insertions(+), 6 deletions(-)
diff --git a/hw/virtio/vhost-v
On 4/14/23 18:04, Alex Bennée wrote:
This is all pretty much boilerplate.
Signed-off-by: Alex Bennée
Tested-by: Erik Schilling
Tested with d6f9fb0 of a rust-vmm SCSI device [1] and -device
vhost-user-device-pci,virtio-id=8,num_vqs=3,config_size=36,chardev=vus
[1] https://github.com/rus
The config caching is disabled when starting config interruption.
If we could know whether there is a config interruption, I think we can
invalidate the cache at that time instead of disabling the caching
mechanism.
After caching the device config, the latency is reduced by 0.066 sec.
Signed-off-
Repetitive ioctls makes vdpa devices initialization and startup slow.
This patch series is to cache Virtio status, features, and config.
For each latency test, I use vdpa-sim-net as my vdpa device.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1579
Shao-Chien Chiang (2):
vhost-vdpa: c
ping5
https://patchew.org/QEMU/cover.1677589218.git.gudkov.and...@huawei.com/
-Original Message-
From: Gudkov Andrei
Sent: Monday, April 10, 2023 18:19
To: 'qemu-devel@nongnu.org'
Cc: 'quint...@redhat.com' ; 'dgilb...@redhat.com'
; 'js...@redhat.com' ;
'ebl...@redhat.com'
Subject: RE
On 18/04/2023 15.19, Juan Quintela wrote:
Thomas Huth wrote:
On 18/04/2023 13.42, Juan Quintela wrote:
Thomas Huth wrote:
On 12/04/2023 16.19, Juan Quintela wrote:
Since commit:
commit 1bfc8dde505f1e6a92697c52aa9b09e81b54c78f
Author: Dr. David Alan Gilbert
Date: Mon Mar 6 15:26:12 2023 +
When running migration tests we monitor for a STOP event so we can skip
redundant waits. This will be needed for the RESUME event too shortly.
Signed-off-by: Daniel P. Berrangé
---
tests/qtest/migration-helpers.c | 12 +---
tests/qtest/migration-helpers.h | 1 +
2 files changed, 10 inse
This makes migration-test faster by observing that most of the pre-copy
tests don't need to be doing a live migration. They get sufficient code
coverage with the guest CPUs paused.
On my machine this cuts the overall execution time of migration-test
by 50% from 15 minutes, down to 8 minutes, witho
There are 27 pre-copy live migration scenarios being tested. In all of
these we force non-convergance and run for one iteration, then let it
converge and wait for completion during the second (or following)
iterations. At 3 mbps bandwidth limit the first iteration takes a very
long time (~30 second
On 4/18/23 14:38, Nina Schoetterl-Glausch wrote:
On Tue, 2023-04-18 at 12:01 +0200, Pierre Morel wrote:
On 4/18/23 10:53, Nina Schoetterl-Glausch wrote:
On Mon, 2023-04-03 at 18:28 +0200, Pierre Morel wrote:
S390 adds two new SMP levels, drawers and books to the CPU
topology.
The S390 CPU ha
On Tue, Apr 18, 2023 at 11:13:57AM +0100, Peter Maydell wrote:
> On Thu, 13 Apr 2023 at 12:12, Zhenzhong Duan wrote:
> >
> > On x86, there are two notifiers registered due to vtd-ir memory
> > region splitting the entire address space. During replay of the
> > address space for each notifier, the
Juan Quintela writes:
> Hi
>
> Please, send any topic that you are interested in covering.
>
>
> Call details:
Please find the recording at:
https://fileserver.linaro.org/s/nJTSCLyQBfo6GLJ
--
Alex Bennée
Virtualisation Tech Lead @ Linaro
PMP entries before the matched PMP entry(including the matched PMP entry)
may overlap partial of the tlb page, which may make different regions in
that page have different permission rights, such as for
PMP0(0x8008~0x800F, R) and PMP1(0x80001000~0x80001FFF, RWX))
write access to 0x8000
TLB should be flushed not only for pmpcfg csr changes, but also for
pmpaddr csr changes.
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
Reviewed-by: Alistair Francis
---
target/riscv/pmp.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
index
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