Am 13.03.23 um 22:16 schrieb Ilya Leoshkevich:
TCG emulates ckc, cputm, last_break and prefix, and it's quite useful
to have them during debugging.
KVM provides those as well so I dont get what you are trying to do here. (I
would understand moving out the pfault things into a KVM section)
On 3/13/23 19:21, Richard Henderson wrote:
On 3/13/23 04:44, Luis Machado wrote:
Luis: I think that rather than doing (2) with a QEMU namespace,
we should define a gdb namespace for this. That makes it clear
that this is still a gdb-upstream-sanctioned way of exposing
the pauth registers.
That
On Mon, 2023-03-13 at 19:17 -0400, Jason Andryuk wrote:
> This looks good, better than what I posted, and seems to work for both
> dm_restrict set and unset.
Thanks.
> For dm_restricted, xs_write() does fail. I verified that with a print
> statement. I think "shouldn't even try" makes sense. I
From: David Woodhouse
When dm_restrict is set, QEMU isn't permitted to update the XenStore node
to indicate its running status. Previously, the xs_write() call would fail
but the failure was ignored.
However, in refactoring to allow for emulated XenStore operations, a new
call to xs_open() was a
On 14/03/2023 08:35, David Woodhouse wrote:
From: David Woodhouse
When dm_restrict is set, QEMU isn't permitted to update the XenStore node
to indicate its running status. Previously, the xs_write() call would fail
but the failure was ignored.
However, in refactoring to allow for emulated XenS
On 14.03.23 00:38, Ilya Leoshkevich wrote:
The code uses the wrong base for relative addressing: it should use the
target instruction address and not the EXECUTE's address.
Fix by storing the target instruction address in the new CPUS390XState
member and loading it from the code generated by in2
On Mon, Mar 13, 2023 at 5:32 PM Kevin Wolf wrote:
> > So I still think that this bug is a symptom of a problem in the design
> > of request queuing.
> >
> > In fact, shouldn't request queuing was enabled at the _end_ of
> > bdrv_drained_begin (once the BlockBackend has reached a quiescent
> > stat
On Tue, 2023-03-14 at 08:06 +0100, Christian Borntraeger wrote:
>
>
> Am 13.03.23 um 22:16 schrieb Ilya Leoshkevich:
> > TCG emulates ckc, cputm, last_break and prefix, and it's quite
> > useful
> > to have them during debugging.
>
> KVM provides those as well so I dont get what you are trying t
Part 1 is a refactor/code motion patch for
qapi/machine target required for setup of
Part 2 which enables query-cpu-model-expansion
on all architectures
Part 3 implements the ',help' feature
Limitations:
Currently only 'FULL' expansion queries are implemented since
that's the only type enabled o
Moved architecture agnostic data types to their own
file to avoid "attempt to use poisoned TARGET_*"
error that results when including qapi header
with commands that aren't defined for all architectures.
Required to implement enabling `query-cpu-model-expansion`
on all architectures
Signed-off-by:
Change parsing of -cpu argument to allow -cpu cpu,help
to print options for the CPU type similar to
how the '-device' option works.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1480
Signed-off-by: Dinah Baum
---
cpu.c | 41 +++
This patch enables 'query-cpu-model-expansion' on all
architectures. Only architectures that implement
the command will return results, others will return an
error message as before.
This patch lays the groundwork for parsing a
-cpu cpu,help option as specified in
https://gitlab.com/qemu-project/q
On Mon, 13 Mar 2023 at 14:11, Thomas Huth wrote:
>
> Hi Peter!
>
> The following changes since commit 29c8a9e31a982874ce4e2c15f2bf82d5f8dc3517:
>
> Merge tag 'linux-user-for-8.0-pull-request' of
> https://gitlab.com/laurent_vivier/qemu into staging (2023-03-12 10:57:00
> +)
>
> are availa
Copying Peter Xu on this one since it's poscopy, especially the newer
postcopy preempt.
* Peter Maydell (peter.mayd...@linaro.org) wrote:
> On Sun, 12 Mar 2023 at 14:06, Peter Maydell wrote:
> >
> > On Tue, 7 Mar 2023 at 09:53, Peter Maydell wrote:
> > >
> > > On Sat, 4 Mar 2023 at 15:39, Peter
Both TCG and KVM emulate ckc, cputm, last_break and prefix, and it's
quite useful to have them during debugging. Right now they are grouped
together with KVM-only pp, pfault_token, pfault_select and
pfault_compare in s390-virt.xml, and are not available when debugging
TCG-emulated code.
Move KVM-o
On 27/2/23 17:31, Jonathan Cameron wrote:
From: Gregory Price
Defines are starting to exceed line length limits, align them for
cleanliness before making modifications.
Signed-off-by: Gregory Price
Signed-off-by: Jonathan Cameron
---
tests/qtest/cxl-test.c | 84 +++-
On 14/3/23 11:00, Dinah Baum wrote:
Moved architecture agnostic data types to their own
file to avoid "attempt to use poisoned TARGET_*"
error that results when including qapi header
with commands that aren't defined for all architectures.
Required to implement enabling `query-cpu-model-expansion
On Tue, Jan 17, 2023 at 07:16:35PM +0100, Pavel Pisa wrote:
> Dear Ben,
>
> sorry for longer response times...
I think we've both dropped the ball on this one, just got reminded about
this set and found it got deleted from work email.
We've done review upates and will try and get some branches o
On Tue, Mar 14, 2023 at 4:35 AM David Woodhouse wrote:
>
> From: David Woodhouse
>
> When dm_restrict is set, QEMU isn't permitted to update the XenStore node
> to indicate its running status. Previously, the xs_write() call would fail
> but the failure was ignored.
>
> However, in refactoring to
Add a small test that checks whether early exceptions are recognized
and whether the correct ILC and old PSW are stored when they happen.
Signed-off-by: Ilya Leoshkevich
---
tests/tcg/s390x/Makefile.softmmu-target | 1 +
tests/tcg/s390x/early-exception-recognition.S | 38 +
Generate specification exception if a reserved bit is set in the PSW
mask or if the PSW address is out of bounds dictated by the addresing
mode.
Reported-by: Nina Schoetterl-Glausch
Signed-off-by: Ilya Leoshkevich
---
target/s390x/cpu.c | 26 ++
target/s390x/
Hi,
Currently loading bad PSW flags does not lead to an exception, which is
not correct. This series fixes this by implementing what PoP calls
"Early Exception Recognition". Since it applies to both loading PSW with
LPSW/LPSWE and to interrupt handling, s390_cpu_set_psw() looks like the
right plac
On Monday, March 13, 2023 8:06:15 PM CET Dorinda Bassey wrote:
> >
> > Are you sure about sizeof(n_bytes) here? That's 4. ;-)
> >
> my bad!
>
> >
> > Volker's point was that "silence" is the center of the wave range. With
> > signed
> > range that's zero, yes, but with unsigned range that's 2^(bit
Fix this format string warning when defining MSI_DEBUG:
hw/pci/msi.c:209:28: warning: format specifies type 'char' but the argument
has type 'unsigned int' [-Wformat]
offset, nr_vectors, msi64bit, msi_per_vector_mask);
^~
Per MST in [*]: "Calling pci_add_capability when VM is running is
likely to confuse guests".
Ensure this can't happen by asserting pci_add_capability() is never
called after a PCI device is realized.
[*]
https://lore.kernel.org/qemu-devel/20230308071628-mutt-send-email-...@kernel.org/
Based-on: <
PCI capabilities can't appear magically at runtime.
Guests aren't expecting that. Assert all capabilities
are added _before_ a device instance is realized.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/pci/pci.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/hw/pci/pci.c b
This 'used' array is allocated via:
pci_qdev_realize() -> do_pci_register_device() -> pci_config_alloc()
In a perfect world where all device models are correctly QOM'ified
this can't happen. Still it occured to me while refactoring QDev and
it was not obvious to figure out. This assert helped, s
A PCI device can't magically become MSI-capable at runtime.
Guests aren't expecting that. Assert MSI is initialized
_before_ a device instance is realized.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/pci/msi.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/hw/pci/msi.c b/hw/pci/msi.c
ind
Chuang Xu writes:
> From: Peter Xu
>
> Calling RCU variance of address_space_get|to_flatview() during memory
"variants" rather than "variance", perhaps?
> commit (flatview updates, triggering memory listeners, or updating
> ioeventfds, etc.) is not 100% accurate, because commit() requires BQL
Currently, the kerneldoc Sphinx plugin doesn't honour the
--enable-werror configure option, so its warnings are never fatal.
This is because although we do pass sphinx-build the -W switch, the
warnings from kerneldoc are produced by the scripts/kernel-doc script
directly and don't go through Sphinx
Hi Volker,
Thank you for the clarification. I see the problem now.
So is it safe to say that:
@@ -104,8 +104,9 @@ playback_on_process(void *data)
/* calculate the total no of bytes to read data from buffer */
req = b->requested * v->frame_size;
if (req == 0) {
-req = 4096 *
> > diff --git a/include/hw/cxl/cxl_device.h b/include/hw/cxl/cxl_device.h
> > index 7e5ad65c1d..d589f78202 100644
> > --- a/include/hw/cxl/cxl_device.h
> > +++ b/include/hw/cxl/cxl_device.h
> > @@ -232,6 +232,14 @@ REG64(CXL_MEM_DEV_STS, 0)
> > FIELD(CXL_MEM_DEV_STS, MBOX_READY, 4, 1)
> >
On Thu, Mar 09, 2023 at 11:39:44AM +, Richard W.M. Jones wrote:
> To implement multi-conn, we will put multiple underlying NBD
> connections (ie. NBDClientConnection) inside the NBD block device
> handle (BDRVNBDState). This requires first breaking the one-to-one
> relationship between NBDClie
On 3/14/2023 2:33 AM, Michael S. Tsirkin wrote:
> On Tue, Mar 14, 2023 at 12:01:09AM -0400, Chuck Zmudzinski wrote:
> > Commit 4f67543bb8c5 ("xen/pt: reserve PCI slot 2 for Intel igd-passthru")
> > uses slot_reserved_mask to reserve slot 2 for the Intel IGD for the
> > xenfv machine when the guest
On 14/03/2023 06:33, Michael S. Tsirkin wrote:
On Tue, Mar 14, 2023 at 12:01:09AM -0400, Chuck Zmudzinski wrote:
Commit 4f67543bb8c5 ("xen/pt: reserve PCI slot 2 for Intel igd-passthru")
uses slot_reserved_mask to reserve slot 2 for the Intel IGD for the
xenfv machine when the guest is configur
On Tue, 14 Mar 2023 at 10:12, Dr. David Alan Gilbert
wrote:
>
> Copying Peter Xu on this one since it's poscopy, especially the newer
> postcopy preempt.
>
> * Peter Maydell (peter.mayd...@linaro.org) wrote:
> > On Sun, 12 Mar 2023 at 14:06, Peter Maydell
> > wrote:
> > > Here's another one, on
On Tue, Mar 14, 2023 at 12:46:18PM +, Peter Maydell wrote:
> On Tue, 14 Mar 2023 at 10:12, Dr. David Alan Gilbert
> wrote:
> >
> > Copying Peter Xu on this one since it's poscopy, especially the newer
> > postcopy preempt.
> >
> > * Peter Maydell (peter.mayd...@linaro.org) wrote:
> > > On Sun,
* Peter Maydell (peter.mayd...@linaro.org) wrote:
> On Tue, 14 Mar 2023 at 10:12, Dr. David Alan Gilbert
> wrote:
> >
> > Copying Peter Xu on this one since it's poscopy, especially the newer
> > postcopy preempt.
> >
> > * Peter Maydell (peter.mayd...@linaro.org) wrote:
> > > On Sun, 12 Mar 2023
On Tue, Mar 14, 2023 at 08:33:02AM -0400, Chuck Zmudzinski wrote:
> On 3/14/2023 2:33 AM, Michael S. Tsirkin wrote:
> > On Tue, Mar 14, 2023 at 12:01:09AM -0400, Chuck Zmudzinski wrote:
> > > Commit 4f67543bb8c5 ("xen/pt: reserve PCI slot 2 for Intel igd-passthru")
> > > uses slot_reserved_mask to
On Tue, Mar 14, 2023 at 12:43:12PM +, Mark Cave-Ayland wrote:
> On 14/03/2023 06:33, Michael S. Tsirkin wrote:
>
> > On Tue, Mar 14, 2023 at 12:01:09AM -0400, Chuck Zmudzinski wrote:
> > > Commit 4f67543bb8c5 ("xen/pt: reserve PCI slot 2 for Intel igd-passthru")
> > > uses slot_reserved_mask t
The postcopy/preempt tests seem to have a race which makes them hang
on the s390x CI runner. Disable them for the moment, while we
investigate. As with the other disabled subtest, you can opt back in
by setting QEMU_TEST_FLAKY_TESTS=1 in your environment.
Suggested-by: Dr. David Alan Gilbert
Si
From: John Snow
Signed-off-by: John Snow
Reviewed-by: Philippe Mathieu-Daudé
Message-Id: <20230202223121.252073-1-js...@redhat.com>
Signed-off-by: Laurent Vivier
---
qemu-options.hx | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/qemu-options.hx b/qemu-options.hx
index d42
* Peter Maydell (peter.mayd...@linaro.org) wrote:
> The postcopy/preempt tests seem to have a race which makes them hang
> on the s390x CI runner. Disable them for the moment, while we
> investigate. As with the other disabled subtest, you can opt back in
> by setting QEMU_TEST_FLAKY_TESTS=1 in y
On 14/03/2023 13:26, Chuck Zmudzinski wrote:
On 3/14/2023 9:17 AM, Michael S. Tsirkin wrote:
On Tue, Mar 14, 2023 at 12:43:12PM +, Mark Cave-Ayland wrote:
On 14/03/2023 06:33, Michael S. Tsirkin wrote:
On Tue, Mar 14, 2023 at 12:01:09AM -0400, Chuck Zmudzinski wrote:
Commit 4f67543bb8c5
.git
tags/trivial-branch-for-8.0-pull-request
for you to fetch changes up to fcc8f37ca3eca968932e5da716ec5e7fc05fdcf4:
MAINTAINERS: Remove CXL maintainer Ben Widawsky (2023-03-14 14:46:38 +0100)
trivial branch pull request 202303
From: Damien Hedde
Also update mailmap
Signed-off-by: Damien Hedde
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Luc Michel
Message-Id: <20230213105227.2357-1-damien.he...@dahe.fr>
Signed-off-by: Laurent Vivier
---
.mailmap| 1 +
MAINTAINERS | 2 +-
2 files changed, 2 insertions(+),
Daniel P. Berrangé writes:
> To just repeat the patch 5 description...
>
Queued to for-8.0/tweaks-and-fixes, thanks.
--
Alex Bennée
Virtualisation Tech Lead @ Linaro
From: Markus Armbruster
Ben is no longer with intel. He told me he expected to get back to
CXL, but it's not happening as quickly as he'd like, and that it's
best to remove him as maintainer. So let's do that.
Thank you for serving as maintainer, Ben!
Signed-off-by: Markus Armbruster
Acked-b
On 14/03/2023 14.33, Peter Maydell wrote:
The postcopy/preempt tests seem to have a race which makes them hang
on the s390x CI runner. Disable them for the moment, while we
investigate. As with the other disabled subtest, you can opt back in
by setting QEMU_TEST_FLAKY_TESTS=1 in your environmen
On 3/14/2023 9:17 AM, Michael S. Tsirkin wrote:
> On Tue, Mar 14, 2023 at 12:43:12PM +, Mark Cave-Ayland wrote:
> > On 14/03/2023 06:33, Michael S. Tsirkin wrote:
> >
> > > On Tue, Mar 14, 2023 at 12:01:09AM -0400, Chuck Zmudzinski wrote:
> > > > Commit 4f67543bb8c5 ("xen/pt: reserve PCI slot
On Tue, 14 Mar 2023 at 14:01, Thomas Huth wrote:
>
> On 14/03/2023 14.33, Peter Maydell wrote:
> > The postcopy/preempt tests seem to have a race which makes them hang
> > on the s390x CI runner. Disable them for the moment, while we
> > investigate. As with the other disabled subtest, you can o
On 3/14/2023 9:41 AM, Mark Cave-Ayland wrote:
> On 14/03/2023 13:26, Chuck Zmudzinski wrote:
>
> > On 3/14/2023 9:17 AM, Michael S. Tsirkin wrote:
> >> On Tue, Mar 14, 2023 at 12:43:12PM +, Mark Cave-Ayland wrote:
> >>> On 14/03/2023 06:33, Michael S. Tsirkin wrote:
> >>>
> On Tue, Mar 14,
On 3/14/2023 9:41 AM, Mark Cave-Ayland wrote:
> On 14/03/2023 13:26, Chuck Zmudzinski wrote:
>
> > On 3/14/2023 9:17 AM, Michael S. Tsirkin wrote:
> >> On Tue, Mar 14, 2023 at 12:43:12PM +, Mark Cave-Ayland wrote:
> >>> On 14/03/2023 06:33, Michael S. Tsirkin wrote:
> >>>
> On Tue, Mar 14,
On Tue, 14 Mar 2023 at 14:14, Thomas Huth wrote:
>
> On 14/03/2023 15.08, Peter Maydell wrote:
> > On Tue, 14 Mar 2023 at 14:01, Thomas Huth wrote:
> >>
> >> On 14/03/2023 14.33, Peter Maydell wrote:
> >>> The postcopy/preempt tests seem to have a race which makes them hang
> >>> on the s390x CI
On 14/03/2023 15.08, Peter Maydell wrote:
On Tue, 14 Mar 2023 at 14:01, Thomas Huth wrote:
On 14/03/2023 14.33, Peter Maydell wrote:
The postcopy/preempt tests seem to have a race which makes them hang
on the s390x CI runner. Disable them for the moment, while we
investigate. As with the ot
On Mon, 13 Mar 2023 at 18:59, Richard Henderson
wrote:
>
> Version 3 fixes a rebase error from v2 affecting ARM BFC insn.
>
>
> r~
>
>
> The following changes since commit 29c8a9e31a982874ce4e2c15f2bf82d5f8dc3517:
>
> Merge tag 'linux-user-for-8.0-pull-request' of
> https://gitlab.com/laurent_v
On 14/03/2023 14:21, Chuck Zmudzinski wrote:
On 3/14/2023 9:41 AM, Mark Cave-Ayland wrote:
On 14/03/2023 13:26, Chuck Zmudzinski wrote:
On 3/14/2023 9:17 AM, Michael S. Tsirkin wrote:
On Tue, Mar 14, 2023 at 12:43:12PM +, Mark Cave-Ayland wrote:
On 14/03/2023 06:33, Michael S. Tsirkin w
On 3/13/23 14:46, Philippe Mathieu-Daudé wrote:
+CodeSourcery folks
On 13/3/23 19:33, Thomas Huth wrote:
Marek and Chris haven't been active for Nios II since years
(the last time seems to have been in 2017), and we've got
unhandled severe Nios II bug tickets in the bug tracker since
a long tim
The 03/03/2023 15:09, Jonathan Cameron wrote:
> Current implementation is very simple so many of the corner
> cases do not exist (e.g. fragmenting larger poison list entries)
>
> Signed-off-by: Jonathan Cameron
> ---
Reviewed-by: Fan Ni
One minor thing as mentioned below.
> v4:
> - Fix off by
The 03/03/2023 15:09, Jonathan Cameron wrote:
> Very simple implementation to allow testing of corresponding
> kernel code. Note that for now we track each 64 byte section
> independently. Whilst a valid implementation choice, it may
> make sense to fuse entries so as to prove out more complex
> c
The 03/03/2023 15:09, Jonathan Cameron wrote:
> Inject poison using qmp command cxl-inject-poison to add an entry to the
> poison list.
>
> For now, the poison is not returned CXL.mem reads, but only via the
> mailbox command Get Poison List.
>
> See CXL rev 3.0, sec 8.2.9.8.4.1 Get Poison list (
On Monday, February 20, 2023 11:08:03 AM CET Bin Meng wrote:
> From: Guohuai Shi
>
> This commit implements Windows specific xxxdir() APIs for safety
> directory access.
That comment is seriously too short for this patch.
1. You should describe the behaviour implementation that you have chosen
I am currently developing tests under avocado to help debugging.
And... it helps.
There is a bug here in s390_topology_set_cpus_entitlement for dedicated
CPUs.
On 3/9/23 13:15, Pierre Morel wrote:
[...]
--- a/hw/s390x/cpu-topology.c
+++ b/hw/s390x/cpu-topology.c
@@ -87,6 +87,84 @@ static vo
From: Matheus Tavares Bernardino
This leakage can be seen through test-io-channel-tls:
$ ../configure --target-list=aarch64-softmmu --enable-sanitizers
$ make ./tests/unit/test-io-channel-tls
$ ./tests/unit/test-io-channel-tls
Indirect leak of 104 byte(s) in 1 object(s) allocated from:
#0 0
The following changes since commit 5cfda4ce79dd455f1726874a555260a70f84b2ec:
Merge tag 'pull-request-2023-03-13' of https://gitlab.com/thuth/qemu into
staging (2023-03-13 17:09:33 +)
are available in the Git repository at:
https://gitlab.com/berrange/qemu tags/misc-next-pull-request
fo
From: Willem van de Velde
To be able to use the function keys F13 to F24 these should be defined in de
keycodemapdb and added to the qapi.
The keycodemapdb is updated in its own repository, this patch enables the use
of those keys within qemu.
Signed-off-by: Willem van de Velde
Signed-off-by:
From: Ross Lagerwall
The scancodes for the Lang1 and Lang2 keys (i.e. Hangeul, Hanja) are
special since they already have the 0x80 bit set which is commonly used
to indicate a key release in AT set 1. Reportedly, real hardware does
not send a key release scancode. So, skip sending a release for t
On 3/13/23 16:38, Ilya Leoshkevich wrote:
The code uses the wrong base for relative addressing: it should use the
target instruction address and not the EXECUTE's address.
Fix by storing the target instruction address in the new CPUS390XState
member and loading it from the code generated by in2_
On 3/14/23 04:00, Ilya Leoshkevich wrote:
Generate specification exception if a reserved bit is set in the PSW
mask or if the PSW address is out of bounds dictated by the addresing
mode.
Reported-by: Nina Schoetterl-Glausch
Signed-off-by: Ilya Leoshkevich
---
target/s390x/cpu.c | 2
On 3/14/23 04:00, Ilya Leoshkevich wrote:
Add a small test that checks whether early exceptions are recognized
and whether the correct ILC and old PSW are stored when they happen.
Signed-off-by: Ilya Leoshkevich
---
tests/tcg/s390x/Makefile.softmmu-target | 1 +
tests/tcg/s390x/early-e
On Tue, Mar 14, 2023 at 10:11:53AM +, Dr. David Alan Gilbert wrote:
> OK, I think I kind of see what's happening here, one for Peter Xu.
> If I'm right it's a race something like:
> a) The test harness tells the source it wants to enter postcopy
> b) The harness then waits for the source to
The RVV verification will error out if fails and it's being done at the
end of riscv_cpu_validate_set_extensions(). Let's put it in its own
function and do it earlier.
We'll move it out of riscv_cpu_validate_set_extensions() in the near future,
but for now this is enough to clean the code a bit.
There is no need to init timers if we're not even sure that our
extensions are valid. Execute riscv_cpu_validate_set_extensions() before
riscv_timer_init().
Signed-off-by: Daniel Henrique Barboza
---
target/riscv/cpu.c | 10 --
1 file changed, 4 insertions(+), 6 deletions(-)
diff --git
In the process of creating the user-facing flags in
register_generic_cpu_props() we're also setting default values for the
cpu->cfg flags that represents MISA bits.
Leaving it as is will cause a discrepancy between users of this function
(at this moment the non-named CPUs) and named CPUs. Named CP
We have 4 config settings being done in riscv_cpu_init(): ext_ifencei,
ext_icsr, mmu and pmp. This is also the constructor of the "riscv-cpu"
device, which happens to be the parent device of every RISC-V cpu.
The result is that these 4 configs are being set every time, and every
other CPU should a
We have all MISA specific validations in riscv_cpu_validate_misa_ext(),
and we have a guarantee that env->misa_ext will always be in sync with
cpu->cfg at this point during realize time, so let's convert it to use a
'misa_ext' parameter instead of reading cpu->cfg.
This will prepare the function t
Hello,
In this v2 the most notable changes were done after Liu Zhiwei review in
[1], in particular the comments made in patch 17. To allow for
write_misa() validation, without the need to store and restore cpu->cfg
state, more design changes were required in the existing validation
logic.
The val
We're doing env->priv_spec validation and assignment at the start of
riscv_cpu_realize(), which is fine, but then we're doing a force disable
on extensions that aren't compatible with the priv version.
This second step is being done too early. The disabled extensions might be
re-enabled again in r
riscv_cpu_validate_v() consists of checking RVV related attributes, such
as vlen and elen, and setting env->vext_spec.
This can be done during riscv_cpu_validate_misa_ext() time, allowing us
to fail earlier if RVV constrains are not met.
Signed-off-by: Daniel Henrique Barboza
---
target/riscv/c
The extremely tedious code that sets cpu->cfg based on misa_ext, and
vice-versa, is scattered around riscv_cpu_validate_set_extensions() and
set_misa().
Introduce helpers to do this work, cleaning up the logic of both
functions a bit. While we're at it, add a note in cpu.h informing that
any futur
Let's remove more code that is open coded in riscv_cpu_realize() and put
it into a helper. Let's also add an error message instead of just
asserting out if env->misa_mxl_max != env->misa_mlx.
Signed-off-by: Daniel Henrique Barboza
---
target/riscv/cpu.c | 51 ++---
In the near future, write_misa() will use a variation of what we have
now as riscv_cpu_validate_set_extensions(). The pmp and epmp validation
will be required in write_misa() and it's already required here in
riscv_cpu_realize(), so move it to riscv_cpu_validate_set_extensions().
Signed-off-by: Da
We can set all RVG related extensions during realize time, before
validate_set_extensions() itself. It will also avoid re-enabling
RVG via write_misa() when the CSR start to using the same validation
code realize() does.
Note that we're setting both cfg->ext_N and env->misa_ext bits, instead
of ju
The setter is doing nothing special. Just set env->priv_ver directly.
Signed-off-by: Daniel Henrique Barboza
---
target/riscv/cpu.c | 30 +-
1 file changed, 13 insertions(+), 17 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 2752efe1eb..18032
We have a chained dependency in riscv_cpu_validate_set_extensions()
related to RVV. If RVV is set, we enable other extensions such as
Zve64d, Zve64f and Zve32f, and these depends on misa bits RVD and RVF.
Thus, we're making RVV depend on RVD and RVF.
Let's add this dependency in riscv_cpu_validate
set_misa() will be tuned up to do more than it's already doing and it
will be redundant to what riscv_cpu_validate_set_extensions() does.
Note that we don't ever change env->misa_mlx in this function, so
set_misa() can be replaced by just assigning env->misa_ext and
env->misa_ext_mask to 'ext'.
S
Similar to what we did with riscv_cpu_validate_misa_ext(), let's read
all MISA bits from a misa_ext val instead of reading from the cpu->cfg
object.
This will allow write_misa() to use riscv_cpu_validate_extensions().
Signed-off-by: Daniel Henrique Barboza
---
target/riscv/cpu.c | 25 ++
All these generic CPUs are using the latest priv available, at this
moment PRIV_VERSION_1_12_0:
- riscv_any_cpu_init()
- rv32_base_cpu_init()
- rv64_base_cpu_init()
- rv128_base_cpu_init()
Create a new PRIV_VERSION_LATEST enum and use it in those cases. I'll
make it easier to update everything at
write_misa() is able to use the same validation workflow
riscv_cpu_realize() uses. But it's still not capable of updating
cpu->cfg misa props yet.
We have no way of blocking future (and current) code from checking
env->misa_ext (via riscv_has_ext()) or reading cpu->cfg directly, so our
best altern
The 'G' bit in misa_ext is a virtual extension that enables a set of
extensions (i, m, a, f, d, icsr and ifencei). We'll want to avoid
setting it for write_misa(). Add it so we can gate write_misa() properly
against it.
Signed-off-by: Daniel Henrique Barboza
---
target/riscv/cpu.c | 4
targ
We're now ready to split riscv_cpu_validate_set_extensions() in two.
None of these steps are going to touch env->misa_ext*.
riscv_cpu_validate_extensions() will take care of all validations based
on cpu->cfg values. cpu->cfg changes that are required for the
validation are being tolerated here. Th
write_misa() must use as much common logic as possible. We want to open
code just the bits that are exclusive to the CSR write operation and TCG
internals.
Rewrite write_misa() to work as follows:
- supress RVC right after verifying that we're not updating RVG;
- mask the write using misa_ext_ma
This setter is doing nothing else but setting env->vext_ver. Assign the
value directly.
Signed-off-by: Daniel Henrique Barboza
---
target/riscv/cpu.c | 7 +--
1 file changed, 1 insertion(+), 6 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 18591aa53a..2752efe1eb 100
We have one last case where we're changing env->misa_ext* during
validation. riscv_cpu_disable_priv_spec_isa_exts(), at the end of
riscv_cpu_validate_set_extensions(), will disable cpu->cfg.ext_h and
cpu->cfg.ext_v if priv_ver check fails.
This check can be done in riscv_cpu_validate_misa_ext(). T
We're getting ready to use riscv_cpu_validate_set_extensions() to unify
the handling of write_misa() with the rest of the code base. But first
we need to deal with RVG.
The 'G' virtual extension enables a set of extensions in the CPU. At
this moment, this is done at the start of our validation ste
set_misa() is setting all 'misa' related env states and nothing else.
But other functions, namely riscv_cpu_validate_set_extensions(), uses
the config object to do its job.
This creates a need to set the single letter extensions in the cfg
object to keep both in sync. At this moment this is being
Now that the function is a no-op if 'env.misa_ext != 0', and no one that
are setting misa_ext != 0 is calling it because set_misa() is setting
the cpu cfg accordingly, remove the now deprecated code and rename the
function to register_generic_cpu_props().
This function is now doing exactly what th
Even after taking RVG off from riscv_cpu_validate_set_extensions(), the
function is still doing too much. It is validating misa bits, then
validating named extensions, and if the validation succeeds it's doing
more changes in both cpu->cfg and MISA bits.
It works for the support we have today, sin
Replace the magic number 32 with CXL_RAS_ERR_HEADER_NUM for better code
readability and maintainability.
Signed-off-by: Fan Ni
---
include/hw/cxl/cxl_device.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/hw/cxl/cxl_device.h b/include/hw/cxl/cxl_device.h
index d589f
On 14.03.23 12:00, Ilya Leoshkevich wrote:
Generate specification exception if a reserved bit is set in the PSW
mask or if the PSW address is out of bounds dictated by the addresing
mode.
Reported-by: Nina Schoetterl-Glausch
Unofficially known to be broken (and ignored) for a long time :D
S
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