Re: [PATCH v15 15/60] i386/xen: add pc_machine_kvm_type to initialize XEN_EMULATE mode

On Fri, 2023-03-10 at 11:15 +0800, Xiaoyao Li wrote: > On 3/1/2023 9:51 PM, David Woodhouse wrote: > > From: David Woodhouse > > > > The xen_overlay device (and later similar devices for event channels and > > grant tables) need to be instantiated. Do this from a kvm_type method on > > the PC mac

Re: [PATCH v15 15/60] i386/xen: add pc_machine_kvm_type to initialize XEN_EMULATE mode

On 3/10/23 09:28, David Woodhouse wrote: On Fri, 2023-03-10 at 11:15 +0800, Xiaoyao Li wrote: On 3/1/2023 9:51 PM, David Woodhouse wrote: From: David Woodhouse The xen_overlay device (and later similar devices for event channels and grant tables) need to be instantiated. Do this from a kvm_ty

Re: Re: [PATCH] target/riscv/csr.c: fix H extension TVM trap

-Original Messages- From:"LIU Zhiwei" Sent Time:2023-03-10 10:12:10 (Friday) To: chenyi2...@zju.edu.cn, qemu-devel@nongnu.org Cc: "Palmer Dabbelt" , "Alistair Francis" , "Bin Meng" , "Weiwei Li" , "Daniel Henrique Barboza" , "open list:RISC-V TCG CPUs" Subject: Re: [PATCH] target/riscv

[PATCH 04/45] target/riscv: Refactor some of the generic vector functionality

From: Kiran Ostrolenk This refactoring ensures these functions/macros can be used by both vector and vector-crypto helpers (latter implemented in proceeding commit). Signed-off-by: Kiran Ostrolenk --- target/riscv/vector_helper.c| 36 - target/riscv/vector_i

[PATCH 12/45] target/riscv: Add vbrev8.v decoding, translation and execution support

From: William Salmon Signed-off-by: William Salmon --- target/riscv/helper.h | 5 +++ target/riscv/insn32.decode | 1 + target/riscv/insn_trans/trans_rvzvkb.c.inc | 38 ++ target/riscv/vcrypto_helper.c | 21 4

[PATCH 07/45] target/riscv: Add vclmulh.vx decoding, translation and execution support

Signed-off-by: Lawrence Hunter --- target/riscv/helper.h | 1 + target/riscv/insn32.decode | 1 + target/riscv/insn_trans/trans_rvzvkb.c.inc | 1 + target/riscv/vcrypto_helper.c | 2 ++ 4 files changed, 5 insertions(+) diff --git a/target/riscv/h

[PATCH 03/45] target/riscv: Add vclmul.vv decoding, translation and execution support

Co-authored-by: Nazar Kazakov Co-authored-by: Max Chou Signed-off-by: Max Chou Signed-off-by: Nazar Kazakov Signed-off-by: Lawrence Hunter --- target/riscv/helper.h | 3 ++ target/riscv/insn32.decode | 3 ++ target/riscv/insn_trans/trans_rvzvkb.c.inc | 4

[PATCH 21/45] target/riscv: Add vaesdm.vv decoding, translation and execution support

Signed-off-by: Lawrence Hunter --- target/riscv/helper.h| 1 + target/riscv/insn32.decode | 1 + target/riscv/insn_trans/trans_rvzvkned.c.inc | 1 + target/riscv/vcrypto_helper.c| 36 4 files changed, 39 insertions(

[PATCH 11/45] target/riscv: Refactor some of the generic vector functionality

From: Kiran Ostrolenk This refactoring ensures these functions/macros can be used by both vector and vector-crypto helpers (latter implemented in proceeding commit). Signed-off-by: Kiran Ostrolenk --- target/riscv/vector_helper.c| 39 target/riscv/vector_in

[PATCH 06/45] target/riscv: Add vclmulh.vv decoding, translation and execution support

Signed-off-by: Lawrence Hunter --- target/riscv/helper.h | 1 + target/riscv/insn32.decode | 1 + target/riscv/insn_trans/trans_rvzvkb.c.inc | 1 + target/riscv/vcrypto_helper.c | 13 + 4 files changed, 16 insertions(+) diff --git

[PATCH 23/45] target/riscv: Add vaesz.vs decoding, translation and execution support

Signed-off-by: Lawrence Hunter --- target/riscv/helper.h| 1 + target/riscv/insn32.decode | 1 + target/riscv/insn_trans/trans_rvzvkned.c.inc | 1 + target/riscv/vcrypto_helper.c| 2 ++ 4 files changed, 5 insertions(+) diff --git a/target

[PATCH 14/45] target/riscv: Add vandn.[vv, vx] decoding, translation and execution support

From: Nazar Kazakov Signed-off-by: Nazar Kazakov --- accel/tcg/tcg-runtime-gvec.c | 11 +++ accel/tcg/tcg-runtime.h| 1 + target/riscv/helper.h | 9 ++ target/riscv/insn32.decode | 2 ++ target/riscv/insn_trans/tr

[PATCH 24/45] target/riscv: Add vaesem.vv decoding, translation and execution support

From: William Salmon Signed-off-by: William Salmon --- target/riscv/helper.h| 1 + target/riscv/insn32.decode | 1 + target/riscv/insn_trans/trans_rvzvkned.c.inc | 1 + target/riscv/vcrypto_helper.c| 17 + 4 files chan

[PATCH 26/45] target/riscv: Add vaeskf1.vi decoding, translation and execution support

From: Nazar Kazakov Signed-off-by: Nazar Kazakov --- target/riscv/helper.h| 1 + target/riscv/insn32.decode | 1 + target/riscv/insn_trans/trans_rvzvkned.c.inc | 58 target/riscv/vcrypto_helper.c| 44 ++

[PATCH 05/45] target/riscv: Add vclmul.vx decoding, translation and execution support

Co-authored-by: Nazar Kazakov Signed-off-by: Nazar Kazakov Signed-off-by: Lawrence Hunter --- target/riscv/helper.h | 1 + target/riscv/insn32.decode | 1 + target/riscv/insn_trans/trans_rvzvkb.c.inc | 48 ++ target/riscv/vcrypto_helper

[PATCH 29/45] target/riscv: Add zvknh cpu properties

From: Nazar Kazakov Signed-off-by: Nazar Kazakov --- target/riscv/cpu.c | 11 ++- target/riscv/cpu.h | 2 ++ 2 files changed, 12 insertions(+), 1 deletion(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index cd87eec919..3ffbdd53cc 100644 --- a/target/riscv/cpu.c +++ b/target/

[PATCH 25/45] target/riscv: Add vaesem.vs decoding, translation and execution support

From: William Salmon Signed-off-by: William Salmon --- target/riscv/helper.h| 1 + target/riscv/insn32.decode | 1 + target/riscv/insn_trans/trans_rvzvkned.c.inc | 1 + target/riscv/vcrypto_helper.c| 3 +++ 4 files changed, 6 insertions(

[PATCH 10/45] target/riscv: Add vrol.[vv, vx] and vror.[vv, vx, vi] decoding, translation and execution support

From: Dickon Hood Add an implementation of the vrol.* and vror.* instructions, with mappings between the RISC-V instructions and their internal TCG accelerated implmentations. There are some missing ror helpers, so I've bodged it by converting them to rols. Co-authored-by: Nazar Kazakov Signed

[PATCH 16/45] target/riscv: Add zvkned cpu property

From: Nazar Kazakov Signed-off-by: Nazar Kazakov --- target/riscv/cpu.c | 3 ++- target/riscv/cpu.h | 1 + 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 462615140c..00e1d007a4 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c

[PATCH 20/45] target/riscv: Add vaesdf.vs decoding, translation and execution support

Signed-off-by: Lawrence Hunter --- target/riscv/helper.h| 1 + target/riscv/insn32.decode | 1 + target/riscv/insn_trans/trans_rvzvkned.c.inc | 1 + target/riscv/vcrypto_helper.c| 3 +++ 4 files changed, 6 insertions(+) diff --git a/targe

[PATCH 08/45] target/riscv: Refactor some of the generic vector functionality

From: Kiran Ostrolenk This refactoring ensures these functions/macros can be used by both vector and vector-crypto helpers (latter implemented in proceeding commit). Also moves the checks out of `do_opiv{v,x,i}_gvec{,_shift}` functions and into the corresponding macros. This enables the function

[PATCH 02/45] target/riscv: Refactor some of the generic vector functionality

From: Kiran Ostrolenk Summary of refactoring: * take some functions/macros out of `vector_helper` and put them in a new module called `vector_internals` * factor the non SEW-specific stuff out of `GEN_OPIVV_TRANS` into function `opivv_trans` (similar to `opivi_trans`) All this refactoring ensu

[PATCH 09/45] qemu/bitops.h: Limit rotate amounts

From: Dickon Hood Rotates have been fixed up to only allow for reasonable rotate amounts (ie, no rotates >7 on an 8b value etc.) This fixes a problem with riscv vector rotate instructions. Signed-off-by: Dickon Hood --- include/qemu/bitops.h | 24 1 file changed, 16 i

[PATCH 28/45] target/riscv: Expose zvkned cpu property

From: Nazar Kazakov Signed-off-by: Nazar Kazakov --- target/riscv/cpu.c | 1 + 1 file changed, 1 insertion(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 00e1d007a4..cd87eec919 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1472,6 +1472,7 @@ static Property riscv_c

[PATCH 18/45] target/riscv: Add vaesef.vs decoding, translation and execution support

Signed-off-by: Lawrence Hunter --- target/riscv/helper.h| 1 + target/riscv/insn32.decode | 1 + target/riscv/insn_trans/trans_rvzvkned.c.inc | 20 +++ target/riscv/vcrypto_helper.c| 36 4 files changed, 58 i

[PATCH 00/45] Add RISC-V vector cryptographic instruction set support

This patchset provides an implementation for Zvkb, Zvkned, Zvknh, Zvksh, Zvkg, and Zvksed of the draft RISC-V vector cryptography extensions as per the 20230303 version of the specification(1) (1fcbb30). Please note that the Zvkt data-independent execution latency extension has not been implemen

[PATCH 17/45] target/riscv: Add vaesef.vv decoding, translation and execution support

Co-authored-by: Nazar Kazakov Signed-off-by: Nazar Kazakov Signed-off-by: Lawrence Hunter --- target/riscv/helper.h| 3 + target/riscv/insn32.decode | 4 ++ target/riscv/insn_trans/trans_rvzvkned.c.inc | 72 +++ target/riscv/op_helper.

[PATCH 27/45] target/riscv: Add vaeskf2.vi decoding, translation and execution support

From: Nazar Kazakov Signed-off-by: Nazar Kazakov --- target/riscv/helper.h| 1 + target/riscv/insn32.decode | 1 + target/riscv/insn_trans/trans_rvzvkned.c.inc | 13 + target/riscv/vcrypto_helper.c| 59 4 files

[PATCH 19/45] target/riscv: Add vaesdf.vv decoding, translation and execution support

Signed-off-by: Lawrence Hunter --- target/riscv/helper.h| 1 + target/riscv/insn32.decode | 1 + target/riscv/insn_trans/trans_rvzvkned.c.inc | 1 + target/riscv/vcrypto_helper.c| 31 4 files changed, 34 insertions(

[PATCH 22/45] target/riscv: Add vaesdm.vs decoding, translation and execution support

Signed-off-by: Lawrence Hunter --- target/riscv/helper.h| 1 + target/riscv/insn32.decode | 1 + target/riscv/insn_trans/trans_rvzvkned.c.inc | 1 + target/riscv/vcrypto_helper.c| 4 4 files changed, 7 insertions(+) diff --git a/targ

[PATCH 13/45] target/riscv: Add vrev8.v decoding, translation and execution support

From: Nazar Kazakov Signed-off-by: Nazar Kazakov --- target/riscv/helper.h | 4 target/riscv/insn32.decode | 1 + target/riscv/insn_trans/trans_rvzvkb.c.inc | 1 + target/riscv/vcrypto_helper.c | 11 +++ 4 files changed, 17 inser

[PATCH 15/45] target/riscv: Expose zvkb cpu property

From: Nazar Kazakov Signed-off-by: Nazar Kazakov --- target/riscv/cpu.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 69611408f9..462615140c 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1469,6 +1469,9 @@ static Property risc

[PATCH 01/45] target/riscv: Add zvkb cpu property

From: Nazar Kazakov Signed-off-by: Nazar Kazakov --- target/riscv/cpu.c | 13 + target/riscv/cpu.h | 1 + 2 files changed, 14 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 1e97473af2..69611408f9 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@

Re: [PATCH] target/riscv/csr.c: fix H extension TVM trap

On 2023/3/10 17:08, CHEN Yi wrote: -Original Messages- *From:*"LIU Zhiwei" *Sent Time:*2023-03-10 10:12:10 (Friday) *To:* chenyi2...@zju.edu.cn, qemu-devel@nongnu.org *Cc:* "Palmer Dabbelt" , "Alistair Francis" , "Bin Meng" , "Weiwei Li" , "Daniel Henrique B

Re: [PATCH v5 1/3] qga: Refactor guest-exec capture-output to take enum

On Thu, Mar 09, 2023 at 03:40:56PM -0700, Daniel Xu wrote: > Previously capture-output was an optional boolean flag that either > captured all output or captured none. While this is OK in most cases, it > lacks flexibility for more advanced capture cases, such as wanting to > only capture stdout. >

Re: [PATCH v5 2/3] qga: Add `merged` variant to GuestExecCaptureOutputMode

On Thu, Mar 09, 2023 at 03:40:57PM -0700, Daniel Xu wrote: > Currently, any captured output (via `capture-output`) is segregated into > separate GuestExecStatus fields (`out-data` and `err-data`). This means > that downstream consumers have no way to reassemble the captured data > back into the ori

Re: [PATCH v15 15/60] i386/xen: add pc_machine_kvm_type to initialize XEN_EMULATE mode

On Fri, 2023-03-10 at 09:52 +0100, Paolo Bonzini wrote: > > I don't think this is abusing mc->kvm_type; that is the point where > startup code tells the machine "now you have your accelerator > configuration, do what you want with that info".  In fact I find using > xen_enabled() in mc->kvm_typ

Re: [PATCH v5 2/3] qga: Add `merged` variant to GuestExecCaptureOutputMode

On Thu, Mar 09, 2023 at 03:40:57PM -0700, Daniel Xu wrote: > Currently, any captured output (via `capture-output`) is segregated into > separate GuestExecStatus fields (`out-data` and `err-data`). This means > that downstream consumers have no way to reassemble the captured data > back into the ori

[PULL V2 00/44] Net patches

The following changes since commit ee59483267de29056b5b2ee2421ef3844e5c9932: Merge tag 'qemu-openbios-20230307' of https://github.com/mcayland/qemu into staging (2023-03-09 16:55:03 +) are available in the git repository at: https://github.com/jasowang/qemu.git tags/net-pull-request fo

[PULL V2 02/44] hw/net: Add more MII definitions

From: Akihiko Odaki The definitions will be used by igb. Signed-off-by: Akihiko Odaki Signed-off-by: Jason Wang --- include/hw/net/mii.h | 13 - 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/include/hw/net/mii.h b/include/hw/net/mii.h index 4ae4dcc..c6a767a 100644

[PULL V2 12/44] e1000e: Remove pending interrupt flags

From: Akihiko Odaki They are duplicate of running throttling timer flags and incomplete as the flags are not cleared when the interrupts are fired or the device is reset. Signed-off-by: Akihiko Odaki Signed-off-by: Jason Wang --- hw/net/e1000e.c | 5 ++--- hw/net/e1000e_core.c | 19 +++-

[PULL V2 11/44] e1000e: Use memcpy to intialize registers

From: Akihiko Odaki Use memcpy instead of memmove to initialize registers. The initial register templates and register table instances will never overlap. Signed-off-by: Akihiko Odaki Signed-off-by: Jason Wang --- hw/net/e1000e_core.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)

[PULL V2 25/44] hw/net/net_tx_pkt: Implement TCP segmentation

From: Akihiko Odaki There was no proper implementation of TCP segmentation before this change, and net_tx_pkt relied solely on IPv4 fragmentation. Not only this is not aligned with the specification, but it also resulted in corrupted IPv6 packets. This is particularly problematic for the igb, a

[PULL V2 04/44] e1000: Use hw/net/mii.h

From: Akihiko Odaki hw/net/mii.h provides common definitions for MII. Signed-off-by: Akihiko Odaki Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Jason Wang --- hw/net/e1000.c | 86 +-- hw/net/e1000_regs.h| 46 --- h

[PULL V2 17/44] e1000e: Set MII_ANER_NWAY

From: Akihiko Odaki This keeps Windows driver 12.18.9.23 from generating an event with ID 30. The description of the event is as follows: > Intel(R) 82574L Gigabit Network Connection > PROBLEM: The network adapter is configured for auto-negotiation but > the link partner is not. This may result

[PULL V2 16/44] e1000e: Introduce e1000_rx_desc_union

From: Akihiko Odaki Before this change, e1000e_write_packet_to_guest() allocated the receive descriptor buffer as an array of uint8_t. This does not ensure the buffer is sufficiently aligned. Introduce e1000_rx_desc_union type, a union type of all receive descriptor types to correct this. Signe

[PULL V2 06/44] e1000e: Introduce E1000E_LOW_BITS_SET_FUNC

From: Akihiko Odaki e1000e_set_16bit and e1000e_set_12bit look so similar so define a generic macro. Signed-off-by: Akihiko Odaki Signed-off-by: Jason Wang --- hw/net/e1000e_core.c | 18 -- 1 file changed, 8 insertions(+), 10 deletions(-) diff --git a/hw/net/e1000e_core.c b/h

[PULL V2 30/44] e1000e: Combine rx traces

From: Akihiko Odaki Whether a packet will be written back to the guest depends on the remaining space of the queue. Therefore, e1000e_rx_written_to_guest and e1000e_rx_not_written_to_guest should log the index of the queue instead of generated interrupts. This also removes the need of e1000e_rx_r

[PULL V2 10/44] e1000: Use memcpy to intialize registers

From: Akihiko Odaki Use memcpy instead of memmove to initialize registers. The initial register templates and register table instances will never overlap. Signed-off-by: Akihiko Odaki Signed-off-by: Jason Wang --- hw/net/e1000.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff

[PULL V2 41/44] igb: Introduce qtest for igb device

From: Akihiko Odaki This change is derived from qtest for e1000e device. Signed-off-by: Akihiko Odaki Acked-by: Thomas Huth [Jason: make qtest work for win32 (only hotplug)] Signed-off-by: Jason Wang --- MAINTAINERS | 2 + tests/qtest/fuzz/generic_fuzz_configs.h

[PULL V2 05/44] e1000: Mask registers when writing

From: Akihiko Odaki When a register has effective bits fewer than their width, the old code inconsistently masked when writing or reading. Make the code consistent by always masking when writing, and remove some code duplication. Signed-off-by: Akihiko Odaki Signed-off-by: Jason Wang --- hw/n

[PULL V2 44/44] ebpf: fix compatibility with libbpf 1.0+

From: Shreesh Adiga <16567adigashre...@gmail.com> The current implementation fails to load on a system with libbpf 1.0 and reports that legacy map definitions in 'maps' section are not supported by libbpf v1.0+. This commit updates the Makefile to add BTF (-g flag) and appropriately updates the ma

[PULL V2 01/44] e1000e: Fix the code style

From: Akihiko Odaki igb implementation first starts off by copying e1000e code. Correct the code style before that. Signed-off-by: Akihiko Odaki Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Jason Wang --- hw/net/e1000.c | 41 ++-- hw/net/e1000e.c| 72 +

Re: [PATCH v5 3/3] qga: test: Add tests for `merged` flag

On Thu, Mar 09, 2023 at 03:40:58PM -0700, Daniel Xu wrote: > This commit adds a test to ensure `merged` functions as expected. > We also add a negative test to ensure we haven't regressed previous > functionality. > > Signed-off-by: Daniel Xu > --- > tests/unit/test-qga.c | 158 +

[PULL V2 19/44] net: Check L4 header size

From: Akihiko Odaki net_tx_pkt_build_vheader() inspects TCP header but had no check for the header size, resulting in an undefined behavior. Check the header size and drop the packet if the header is too small. Signed-off-by: Akihiko Odaki Signed-off-by: Jason Wang --- hw/net/e1000e_core.c |

[PULL V2 27/44] e1000e: Do not assert when MSI-X is disabled later

From: Akihiko Odaki Assertions will fail if MSI-X gets disabled while a timer for MSI-X interrupts is running so remove them to avoid abortions. Fortunately, nothing bad happens even if the assertions won't trigger as msix_notify(), called by timer handlers, does nothing when MSI-X is disabled.

[PULL V2 31/44] e1000: Count CRC in Tx statistics

From: Akihiko Odaki The Software Developer's Manual 13.7.4.5 "Packets Transmitted (64 Bytes) Count" says: > This register counts the number of packets transmitted that are > exactly 64 bytes (from through , > inclusively) in length. It also says similar for the other Tx statistics registers. Ad

[PULL V2 07/44] e1000e: Mask registers when writing

From: Akihiko Odaki When a register has effective bits fewer than their width, the old code inconsistently masked when writing or reading. Make the code consistent by always masking when writing, and remove some code duplication. Signed-off-by: Akihiko Odaki Signed-off-by: Jason Wang --- hw/n

[PULL V2 13/44] e1000e: Improve software reset

From: Akihiko Odaki This change makes e1000e reset more things when software reset was triggered. Some registers are exempted from software reset in the datasheet and this change also implements the behavior accordingly. Signed-off-by: Akihiko Odaki Signed-off-by: Jason Wang --- hw/net/e1000e

[PULL V2 23/44] hw/net/net_rx_pkt: Remove net_rx_pkt_has_virt_hdr

From: Akihiko Odaki When virtio-net header is not set, net_rx_pkt_get_vhdr() returns zero-filled virtio_net_hdr, which is actually valid. In fact, tap device uses zero-filled virtio_net_hdr when virtio-net header is not provided by the peer. Therefore, we can just remove net_rx_pkt_has_virt_hdr()

[PULL V2 08/44] e1000: Use more constant definitions

From: Akihiko Odaki The definitions for E1000_VFTA_ENTRY_SHIFT, E1000_VFTA_ENTRY_MASK, and E1000_VFTA_ENTRY_BIT_SHIFT_MASK were copied from: https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/tree/drivers/net/ethernet/intel/e1000/e1000_hw.h?h=v6.0.9#n306 The definitions for E1000_N

[PULL V2 21/44] net: Strip virtio-net header when dumping

From: Akihiko Odaki filter-dump specifiees Ethernet as PCAP LinkType, which does not expect virtio-net header. Having virtio-net header in such PCAP file breaks PCAP unconsumable. Unfortunately currently there is no LinkType for virtio-net so for now strip virtio-net header to convert the output

[PATCH 32/45] target/riscv: Expose zvknh cpu properties

From: Nazar Kazakov Signed-off-by: Nazar Kazakov --- target/riscv/cpu.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 3ffbdd53cc..b3f9638067 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1482,6 +1482,8 @@ static Property riscv

[PULL V2 03/44] fsl_etsec: Use hw/net/mii.h

From: Akihiko Odaki hw/net/mii.h provides common definitions for MII. Signed-off-by: Akihiko Odaki Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Jason Wang --- hw/net/fsl_etsec/etsec.c | 11 ++- hw/net/fsl_etsec/etsec.h | 17 - hw/net/fsl_etsec/miim.c | 5 +++--

[PULL V2 20/44] e1000x: Alter the signature of e1000x_is_vlan_packet

From: Akihiko Odaki e1000x_is_vlan_packet() had a pointer to uint8_t as a parameter, but it does not have to be uint8_t. Change the type to void *. Signed-off-by: Akihiko Odaki Signed-off-by: Jason Wang --- hw/net/e1000x_common.c | 2 +- hw/net/e1000x_common.h | 2 +- 2 files changed, 2 inser

[PULL V2 24/44] e1000e: Perform software segmentation for loopback

From: Akihiko Odaki e1000e didn't perform software segmentation for loopback if virtio-net header is enabled, which is wrong. To fix the problem, introduce net_tx_pkt_send_custom(), which allows the caller to specify whether offloading should be assumed or not. net_tx_pkt_send_custom() also all

[PATCH 35/45] target/riscv: Add vsm3c.vi decoding, translation and execution support

From: Kiran Ostrolenk Signed-off-by: Kiran Ostrolenk --- target/riscv/helper.h | 1 + target/riscv/insn32.decode | 1 + target/riscv/insn_trans/trans_rvzvksh.c.inc | 6 ++ target/riscv/vcrypto_helper.c | 95 + 4 files c

[PULL V2 22/44] hw/net/net_tx_pkt: Automatically determine if virtio-net header is used

From: Akihiko Odaki The new function qemu_get_using_vnet_hdr() allows to automatically determine if virtio-net header is used. Signed-off-by: Akihiko Odaki Signed-off-by: Jason Wang --- hw/net/e1000e_core.c | 3 +-- hw/net/net_tx_pkt.c | 19 ++- hw/net/net_tx_pkt.h | 3 +--

[PULL V2 35/44] net/eth: Introduce EthL4HdrProto

From: Akihiko Odaki igb, a new network device emulation, will need SCTP checksum offloading. Currently eth_get_protocols() has a bool parameter for each protocol currently it supports, but there will be a bit too many parameters if we add yet another protocol. Introduce an enum type, EthL4HdrPro

[PATCH 31/45] target/riscv: Add vsha2c[hl].vv decoding, translation and execution support

Co-authored-by: Nazar Kazakov Signed-off-by: Nazar Kazakov Signed-off-by: Lawrence Hunter --- target/riscv/helper.h | 2 + target/riscv/insn32.decode | 2 + target/riscv/insn_trans/trans_rvzvknh.c.inc | 2 + target/riscv/vcrypto_helper.c

[PULL V2 14/44] e1000: Configure ResettableClass

From: Akihiko Odaki This is part of recent efforts of refactoring e1000 and e1000e. DeviceClass's reset member is deprecated so migrate to ResettableClass. There is no behavioral difference. Signed-off-by: Akihiko Odaki Reviewed-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé Signed-of

[PULL V2 39/44] tests/qtest/e1000e-test: Fabricate ethernet header

From: Akihiko Odaki e1000e understands ethernet header so fabricate something convincing. Signed-off-by: Akihiko Odaki Reviewed-by: Thomas Huth Signed-off-by: Jason Wang --- tests/qtest/e1000e-test.c | 25 +++-- tests/qtest/libqos/e1000e.h | 2 ++ 2 files changed, 17 i

[PULL V2 26/44] hw/net/net_tx_pkt: Check the payload length

From: Akihiko Odaki Check the payload length if checksumming to ensure the payload contains the space for the resulting value. This bug was found by Alexander Bulekov with the fuzzer: https://patchew.org/QEMU/20230129053316.1071513-1-alx...@bu.edu/ The fixed test case is: fuzz/crash_6aeaa33e721

[PULL V2 09/44] e1000e: Use more constant definitions

From: Akihiko Odaki The definitions of SW Semaphore Register were copied from: https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/tree/drivers/net/ethernet/intel/e1000e/defines.h?h=v6.0.9#n374 Signed-off-by: Akihiko Odaki Signed-off-by: Jason Wang --- hw/net/e1000_regs.h | 7 +

[PULL V2 37/44] e1000: Split header files

From: Akihiko Odaki Some definitions in the header files are invalid for igb so extract them to new header files to keep igb from referring to them. Signed-off-by: Gal Hammer Signed-off-by: Marcel Apfelbaum Signed-off-by: Akihiko Odaki Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Jason

[PULL V2 34/44] e1000e: Implement system clock

From: Akihiko Odaki The system clock is necessary to implement PTP features. While we are not implementing PTP features for e1000e yet, we do have a plan to implement them for igb, a new network device derived from e1000e, so add system clock to the common base first. Signed-off-by: Akihiko Odak

[PULL V2 33/44] net/eth: Report if headers are actually present

From: Akihiko Odaki The values returned by eth_get_protocols() are used to perform RSS, checksumming and segmentation. Even when a packet signals the use of the protocols which these operations can be applied to, the headers for them may not be present because of too short packet or fragmentation

[PULL V2 32/44] e1000e: Count CRC in Tx statistics

From: Akihiko Odaki The datasheet 8.19.29 "Good Packets Transmitted Count - GPTC (0x04080; RC)" says: > This register counts the number of good (no errors) packets > transmitted. A good transmit packet is considered one that is 64 or > more bytes in length (from through , > inclusively) in lengt

[PULL V2 36/44] pcie: Introduce pcie_sriov_num_vfs

From: Akihiko Odaki igb can use this function to change its behavior depending on the number of virtual functions currently enabled. Signed-off-by: Gal Hammer Signed-off-by: Marcel Apfelbaum Signed-off-by: Akihiko Odaki Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Jason Wang --- hw/p

[PULL V2 28/44] MAINTAINERS: Add Akihiko Odaki as a e1000e reviewer

From: Akihiko Odaki I want to know to be notified when there is a new change for e1000e as e1000e is similar to igb and such a change may also be applicable for igb. Signed-off-by: Akihiko Odaki Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Jason Wang --- MAINTAINERS | 2 ++ 1 file chan

[PATCH 37/45] target/riscv: Add zvkg cpu property

Signed-off-by: Lawrence Hunter --- target/riscv/cpu.c | 5 +++-- target/riscv/cpu.h | 1 + 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index c136a17112..79079d517d 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -110,6 +110,7

[PATCH 34/45] target/riscv: Add vsm3me.vv decoding, translation and execution support

Co-authored-by: Kiran Ostrolenk Signed-off-by: Lawrence Hunter Signed-off-by: Kiran Ostrolenk --- target/riscv/helper.h | 2 ++ target/riscv/insn32.decode | 3 ++ target/riscv/insn_trans/trans_rvzvksh.c.inc | 37 +++ target/riscv/translat

[PULL V2 43/44] docs/system/devices/igb: Add igb documentation

From: Akihiko Odaki Signed-off-by: Akihiko Odaki Reviewed-by: Cédric Le Goater Signed-off-by: Jason Wang --- MAINTAINERS | 1 + docs/system/device-emulation.rst | 1 + docs/system/devices/igb.rst | 71 3 files changed, 73 in

[PATCH 40/45] target/riscv: Expose zvkg cpu property

Signed-off-by: Lawrence Hunter --- target/riscv/cpu.c | 1 + 1 file changed, 1 insertion(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 79079d517d..323e0c462b 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1484,6 +1484,7 @@ static Property riscv_cpu_extensions[] = {

[PULL V2 15/44] e1000e: Configure ResettableClass

From: Akihiko Odaki This is part of recent efforts of refactoring e1000 and e1000e. DeviceClass's reset member is deprecated so migrate to ResettableClass. There is no behavioral difference. Signed-off-by: Akihiko Odaki Reviewed-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé Signed-of

[PULL V2 40/44] tests/qtest/libqos/e1000e: Export macreg functions

From: Akihiko Odaki They will be useful for igb testing. Signed-off-by: Akihiko Odaki Reviewed-by: Thomas Huth Signed-off-by: Jason Wang --- tests/qtest/libqos/e1000e.c | 12 tests/qtest/libqos/e1000e.h | 12 2 files changed, 12 insertions(+), 12 deletions(-) diff

[PULL V2 29/44] MAINTAINERS: Add e1000e test files

From: Akihiko Odaki Signed-off-by: Akihiko Odaki Acked-by: Thomas Huth Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Jason Wang --- MAINTAINERS | 2 ++ 1 file changed, 2 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 141eb67..d61d1ef 100644 --- a/MAINTAINERS +++ b/MAINTAINE

[PULL V2 42/44] tests/avocado: Add igb test

From: Akihiko Odaki This automates ethtool tests for igb registers, interrupts, etc. Signed-off-by: Akihiko Odaki Reviewed-by: Cédric Le Goater Signed-off-by: Jason Wang --- MAINTAINERS| 1 + scripts/ci/org.centos/stream/8/x86_64/test-avocado | 1 +

[PATCH 44/45] target/riscv: Add Zvksed support

From: Max Chou - add vsm4k, vsm4r instructions Signed-off-by: Max Chou Reviewed-by: Frank Chang [lawrence.hun...@codethink.co.uk: Moved SM4 functions from crypto_helper.c to vcrypto_helper.c] [nazar.kaza...@codethink.co.uk: Added alignment checks, refactored code to use macros, and minor s

[PULL V2 18/44] e1000e: Remove extra pointer indirection

From: Akihiko Odaki e1000e_write_packet_to_guest() passes the reference of variable ba as a pointer to an array, and that pointer indirection is just unnecessary; all functions which uses the passed reference performs no pointer operation on the pointer and they simply dereference the passed poin

[PATCH 43/45] target/riscv: Add zvksed cfg property

From: Max Chou Signed-off-by: Max Chou Reviewed-by: Frank Chang --- target/riscv/cpu.c | 3 ++- target/riscv/cpu.h | 1 + 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 323e0c462b..84a225bf5f 100644 --- a/target/riscv/cpu.c +++ b/tar

[PATCH 45/45] target/riscv: Expose Zvksed property

From: Max Chou Signed-off-by: Max Chou Reviewed-by: Frank Chang --- target/riscv/cpu.c | 1 + 1 file changed, 1 insertion(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 84a225bf5f..8caa485f28 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1489,6 +1489,7 @@ static

[PATCH 36/45] target/riscv: Expose zvksh cpu property

From: Kiran Ostrolenk Signed-off-by: Kiran Ostrolenk --- target/riscv/cpu.c | 1 + 1 file changed, 1 insertion(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index e218a00a2d..c136a17112 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1486,6 +1486,7 @@ static Property ris

[PATCH 41/45] crypto: Create sm4_subword

From: Max Chou - Share sm4_subword between different targets. Signed-off-by: Max Chou Reviewed-by: Frank Chang --- include/crypto/sm4.h | 8 target/arm/tcg/crypto_helper.c | 10 ++ 2 files changed, 10 insertions(+), 8 deletions(-) diff --git a/include/crypto/s

[PATCH 39/45] target/riscv: Add vghsh.vv decoding, translation and execution support

Signed-off-by: Lawrence Hunter --- target/riscv/helper.h | 1 + target/riscv/insn32.decode | 1 + target/riscv/insn_trans/trans_rvzvkg.c.inc | 10 ++ target/riscv/vcrypto_helper.c | 38 ++ 4 files changed, 50 insertions(+

[PATCH 42/45] crypto: Add SM4 constant parameter CK

From: Max Chou Signed-off-by: Max Chou Reviewed-by: Frank Chang --- crypto/sm4.c | 10 ++ include/crypto/sm4.h | 1 + 2 files changed, 11 insertions(+) diff --git a/crypto/sm4.c b/crypto/sm4.c index 9f0cd452c7..2987306cf7 100644 --- a/crypto/sm4.c +++ b/crypto/sm4.c @@ -47,3

[PATCH 38/45] target/riscv: Add vgmul.vv decoding, translation and execution support

Co-authored-by: Nazar Kazakov Signed-off-by: Nazar Kazakov Signed-off-by: Lawrence Hunter --- target/riscv/helper.h | 2 ++ target/riscv/insn32.decode | 3 ++ target/riscv/insn_trans/trans_rvzvkg.c.inc | 30 +++ target/riscv/translate.c

[PATCH 33/45] target/riscv: Add zvksh cpu property

From: Kiran Ostrolenk Signed-off-by: Kiran Ostrolenk --- target/riscv/cpu.c | 4 +++- target/riscv/cpu.h | 1 + 2 files changed, 4 insertions(+), 1 deletion(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index b3f9638067..e218a00a2d 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/c

[PATCH 30/45] target/riscv: Add vsha2ms.vv decoding, translation and execution support

From: Kiran Ostrolenk Co-authored-by: Nazar Kazakov Signed-off-by: Nazar Kazakov Signed-off-by: Kiran Ostrolenk --- target/riscv/helper.h | 2 + target/riscv/insn32.decode | 3 + target/riscv/insn_trans/trans_rvzvknh.c.inc | 82 + t

Re: [PATCH v2 02/18] ui/dbus: unregister clipboard on connection close

On Tue, Mar 07, 2023 at 03:56:21PM +0400, marcandre.lur...@redhat.com wrote: > From: Marc-André Lureau > > Fixes unregistration with p2p connections, since they don't have an > associated name owner. > > Signed-off-by: Marc-André Lureau > --- > ui/dbus-clipboard.c | 18 +++--- > 1

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