On Sat, 2023-03-04 at 01:28 +0100, Thomas Gleixner wrote:
> David!
>
> On Fri, Mar 03 2023 at 16:54, David Woodhouse wrote:
> > On Fri, 2023-03-03 at 17:51 +0100, Thomas Gleixner wrote:
> > > >
> > > > [ 0.577173] ACPI: \_SB_.LNKC: Enabled at IRQ 11
> > > > [ 0.578149] The affinity mask was
On Sat, 2023-03-04 at 09:57 +, David Woodhouse wrote:
> I wonder if the EOI is going missing because it's coming
> from the wrong CPU? Note no 'EOI broadcast' after the last line in the
> log I showed above; it isn't just that I trimmed it there.
I'm running on a host kernel without commit fce
Commit bb98e0f59cde ("hw/isa/vt82c686: Remove intermediate IRQ forwarder")
passes s->cpu_intr to i8259_init() in via_isa_realize() directly. However,
s->cpu_intr isn't initialized yet since that happens after the south
bridge's pci_realize_and_unref() in board code. Fix this by initializing s-
>cpu
There is also pci_create_simple() which creates non-multifunction PCI
devices. Accordingly the parameter is always set to true when a multi
function PCI device is to be created.
The reason for the parameter's existence seems to be that it is used in the
internal PCI code as well which is the only
Commit cef2e7148e32 ("hw/isa/i82378: Remove intermediate IRQ forwarder")
passes s->cpu_intr to i8259_init() in i82378_realize() directly. However, s-
>cpu_intr isn't initialized yet since that happens after the south bridge's
pci_realize_and_unref() in board code. Fix this by initializing s->cpu_in
A recent series [1] attempted to remove some PIC -> CPU interrupt indirections.
This inadvertantly caused NULL qemu_irqs to be passed to the i8259 because the
qemu_irqs aren't initialized at that time yet. This series provides a fix by
initializing the qemu_irq of the respective south bridges befor
There is also pci_new() which creates non-multifunction PCI devices.
Accordingly the parameter is always set to true when a multi function PCI
device is to be created.
The reason for the parameter's existence seems to be that it is used in the
internal PCI code as well which is the only location w
Commit cef2e7148e32 ("hw/isa/i82378: Remove intermediate IRQ forwarder")
passes s->cpu_intr to i8259_init() in i82378_realize() directly. However, s-
>cpu_intr isn't initialized yet since that happens after the south bridge's
pci_realize_and_unref() in board code. Fix this by initializing s->cpu_in
Am 3. März 2023 07:46:31 UTC schrieb Mark Cave-Ayland
:
>On 03/03/2023 06:58, David Woodhouse wrote:
>
>> On 2 March 2023 22:40:40 GMT, "Philippe Mathieu-Daudé"
>> wrote:
>>> Since v2: rebased
>>>
>>> I'm posting this series as it to not block Bernhard's PIIX
>>> cleanup work. I don't have code c
On Sat, Mar 4, 2023 at 12:40 PM Bernhard Beschow wrote:
> A recent series [1] attempted to remove some PIC -> CPU interrupt
> indirections.
> This inadvertantly caused NULL qemu_irqs to be passed to the i8259 because
> the
> qemu_irqs aren't initialized at that time yet. This series provides a fi
Fabiano Rosas writes:
> Matheus Tavares Bernardino writes:
>
>> Hi,
>>
>> We noticed that local `make check-tcg` is rebuilding the docker image
>> for qemu-hexagon at every run, whereas previously it would say "Image is
>> up to date" and move on.
>>
>> This was changed at 0b1a649047 (tests/do
On Sat, 4 Mar 2023, Bernhard Beschow wrote:
Commit bb98e0f59cde ("hw/isa/vt82c686: Remove intermediate IRQ forwarder")
passes s->cpu_intr to i8259_init() in via_isa_realize() directly. However,
s->cpu_intr isn't initialized yet since that happens after the south
bridge's pci_realize_and_unref() i
On Sat, 4 Mar 2023, Bernhard Beschow wrote:
A recent series [1] attempted to remove some PIC -> CPU interrupt indirections.
This inadvertantly caused NULL qemu_irqs to be passed to the i8259 because the
qemu_irqs aren't initialized at that time yet. This series provides a fix by
initializing the
Hi
On Fri, Mar 3, 2023 at 8:00 PM Dorinda Bassey wrote:
>
> This commit adds a new audiodev backend to allow QEMU to use Pipewire as
> both an audio sink and source. This backend is available on most systems
>
> Add Pipewire entry points for QEMU Pipewire audio backend
> Add wrappers for QEMU Pip
On Thu, 2 Mar 2023 at 16:21, Juan Quintela wrote:
>
> The following changes since commit 262312d7ba6e2966acedb4f9c134fd19176b4083:
>
> Merge tag 'pull-testing-next-010323-1' of https://gitlab.com/stsquad/qemu
> into staging (2023-03-02 13:02:53 +)
>
> are available in the Git repository at:
On Fri, 3 Mar 2023 at 02:41, Song Gao wrote:
>
> The following changes since commit 262312d7ba6e2966acedb4f9c134fd19176b4083:
>
> Merge tag 'pull-testing-next-010323-1' of https://gitlab.com/stsquad/qemu
> into staging (2023-03-02 13:02:53 +)
>
> are available in the Git repository at:
>
>
On Thu, 2 Mar 2023 at 17:42, Cédric Le Goater wrote:
>
> The following changes since commit a2b5f8b8ab7b2c947823088103a40f0ff11fe06b:
>
> Merge tag 'pull-tcg-20230301' of https://gitlab.com/rth7680/qemu into
> staging (2023-03-01 19:19:20 +)
>
> are available in the Git repository at:
>
>
On 2/28/23 23:39, Igor Mammedov wrote:
On Tue, 28 Feb 2023 21:34:33 +0700
Bui Quang Minh wrote:
On 2/27/23 23:07, Igor Mammedov wrote:
On Sat, 25 Feb 2023 17:15:17 +0700
Bui Quang Minh wrote:
On 2/24/23 21:29, Igor Mammedov wrote:
On Tue, 21 Feb 2023 23:04:57 +0700
Bui Quang Minh wrot
On Fri, 3 Mar 2023 at 20:59, Fabiano Rosas wrote:
>
> Peter Maydell writes:
>
> > On Tue, 28 Feb 2023 at 19:28, Fabiano Rosas wrote:
> >>
> >> The migration tests are currently broken for an aarch64 host because
> >> the tests pass no 'machine' and 'cpu' options on the QEMU command
> >> line.
>
On Sat, 4 Mar 2023 at 13:30, BALATON Zoltan wrote:
>
> On Sat, 4 Mar 2023, Bernhard Beschow wrote:
> > A recent series [1] attempted to remove some PIC -> CPU interrupt
> > indirections.
> > This inadvertantly caused NULL qemu_irqs to be passed to the i8259 because
> > the
> > qemu_irqs aren't i
From: Bernhard Beschow
According to the PCI specification, PCI_INTERRUPT_LINE shall have no
effect on hardware operations. Now that the VIA south bridges implement
the internal PCI interrupt router let's be more conformant to the PCI
specification.
Signed-off-by: Bernhard Beschow
Signed-off-by:
According to the PegasosII schematics the PCI interrupt lines are
connected to both the gpp pins of the Mv64361 north bridge and the
PINT pins of the VT8231 south bridge so guests can get interrupts from
either of these. So far we only had the MV64361 connections which
worked for on board devices b
Add basic implementation of the AC'97 sound part used in VIA south
bridge chips. Not all features of the device is emulated, only one
playback channel is supported for now but this is enough to get sound
output from some guests using this device on pegasos2.
Signed-off-by: BALATON Zoltan
Reviewed
Latest version of series with the following changes since v5:
v6:
- Replaced work around for level sensitive interrupt needed by MorphOS
with patch from David Woodhouse that implements it in i8259 model
- Added R-b, T-b tags
- Moved revert patch to the end so it's easier to drop it to help
merging
The real VIA south bridges implement a PCI IRQ router which is configured
by the BIOS or the OS. In order to respect these configurations, QEMU
needs to implement it as well. The real chip may allow routing IRQs from
internal functions independently of PCI interrupts but since guests
usually config
This partially reverts commit bb98e0f59cde84d9fddc60ae74ef7ddfca17
keeping the rename of a state field but reverting other cahanges which
break interrupts on pegasos2.
Signed-off-by: BALATON Zoltan
Tested-by: Rene Engel
---
hw/isa/vt82c686.c | 10 +-
1 file changed, 9 insertions(+),
From: David Woodhouse
Back in the mists of time, before EISA came along and required per-pin
level control in the ELCR register, the i8259 had a single chip-wide
level-mode control in bit 3 of ICW1.
Even in the PIIX3 datasheet from 1996 this is documented as 'This bit is
disabled', but apparentl
Add a property to allow disabling pixman and always use the fallbacks
for different operations which is useful for testing different drawing
methods or debugging pixman related issues.
Signed-off-by: BALATON Zoltan
Tested-by: Rene Engel
---
hw/display/sm501.c | 18 +++---
1 file cha
Hello everyone
I was thinking about working on the RDB Server project, and thus just
wanted clarification of IronRDB status. The GSoC Project description [1]
states that IronRDB [2] lacks some server support. So what are the
essential features that IronRDB is missing?
Also, another possibility is
These properties are class properties in i440fx. No need to handle them
differently in q35.
Signed-off-by: Bernhard Beschow
---
hw/pci-host/q35.c | 32
1 file changed, 16 insertions(+), 16 deletions(-)
diff --git a/hw/pci-host/q35.c b/hw/pci-host/q35.c
index 23d
Variables of type PCIHostState* are typically named "phb" in QEMU.
Follow this convention here as well for consistency.
Signed-off-by: Bernhard Beschow
---
hw/pci-host/q35.c | 14 +++---
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/hw/pci-host/q35.c b/hw/pci-host/q35.c
i
The boundaries of the PCI hole depend on a property only which doesn't
change at runtime. There is no need to reevaluate the boundaries
whenever the PCI configuration space changes.
While at it, move the pci_hole attribute into the host device since it
is only used there.
Signed-off-by: Bernhard
The Q35 PCI host currently sets the PC machine's PCI bus attribute
through global state, thereby assuming the machine to be a PC machine.
The Q35 machine code already holds on to Q35's pci bus attribute, so can
easily set its own property while preserving encapsulation.
Signed-off-by: Bernhard Bes
q35_host_realize() has an errp parameter. Use that to be able to
propagate the error instead of terminating abruptly.
Signed-off-by: Bernhard Beschow
---
hw/pci-host/q35.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/hw/pci-host/q35.c b/hw/pci-host/q35.c
index cf9fb35064
The variable is redundant to "phb" and is never used by its real type.
Signed-off-by: Bernhard Beschow
Reviewed-by: Thomas Huth
---
hw/i386/pc_q35.c | 29 ++---
1 file changed, 14 insertions(+), 15 deletions(-)
diff --git a/hw/i386/pc_q35.c b/hw/i386/pc_q35.c
index 5a1e
This series mostly cleans up QOM-related initialization code. It also performs
some modernization and fixing.
The first patch originates from "PC and ICH9 clanups" series [1] which has been
dropped in v3 in favor of another series [2]. Review comments in [2] suggest it
needs more work, so bring th
This patch prepares movement of the MemoryRegion pointers (which are set
through properties) into the host state. Moreover, it's usually the
parent device which maps the memory regions of its child devices into
its address space. Do the same in q35.
Signed-off-by: Bernhard Beschow
---
hw/pci-hos
Commit bafc90bdc594 ("q35: implement TSEG") uses
memory_region_set_address() for updating the address of mch->tseg_window
but uses memory_region_del_subregion() and
memory_region_add_subregion_overlap() for doing the same on mch-
>tseg_blackhole. The latter seems to be the old, cumbersome
way of ch
Fixes the following clangd warning (-Winitializer-overrides):
q35.c:297:19: Initializer overrides prior initialization of this subobject
q35.c:292:19: previous initialization is here
Settle on native endian which causes the least overhead.
Fixes: bafc90bdc594 ("q35: implement TSEG")
Signed-o
The pointers are set through the host device's properties and are only
used during its realization phase.
Signed-off-by: Bernhard Beschow
---
include/hw/pci-host/q35.h | 10 +++
hw/pci-host/q35.c | 56 +++
2 files changed, 33 insertions(+), 33 dele
Introduce a macro to avoid copy and pasting strings which can easily
cause typos.
Suggested-by: Michael S. Tsirkin
Signed-off-by: Bernhard Beschow
---
include/hw/pci/pci_host.h | 2 ++
hw/pci/pci_host.c | 2 +-
2 files changed, 3 insertions(+), 1 deletion(-)
diff --git a/include/hw/pci/
The Q35 PCI host already has a "bypass-iommu" property. However, the
host initializes this property itself by accessing global machine state,
thereby assuming it to be a PC machine. Avoid this by having board code
set this property.
Signed-off-by: Bernhard Beschow
---
hw/i386/pc_q35.c | 2 ++
h
Although not used there, the attributes for Q35's "pci-hole64-size" and
"short_root_bus" properties currently reside in its child device. This
causes the default values to be overwritten during the child's
object_initialize() phase, requiring the host to re-assign the default
values manually again.
On Thu, 2 Mar 2023 at 17:22, Peter Maydell wrote:
>
> migration-test has been flaky for a long time, both in CI and
> otherwise:
>
> In the cases where I've looked at the underlying log, this seems to
> be in the migration/multifd/tcp/plain/cancel subtest. Disable that
> specific subtest by def
On Fri, 3 Mar 2023 at 21:28, Daniel Henrique Barboza
wrote:
>
> The following changes since commit 66577e9e1caee48c6ebc1a2161b5d9857fcde8b3:
>
> Merge tag 'for_upstream' of
> https://git.kernel.org/pub/scm/virt/kvm/mst/qemu into staging (2023-03-03
> 13:35:54 +)
>
> are available in the Gi
On Wed, 1 Mar 2023 at 13:33, Kevin Wolf wrote:
>
> Am 01.03.2023 um 12:34 hat Thomas Huth geschrieben:
> > The enablement of -Wthread-safety broke compilation on macOS (if
> > -Werror is enabled, like in our CI). Disable it there by default
> > until the problems are resolved.
> >
> > Signed-off-b
Success from trans_* subroutines should be true.
Fixes: 5fa38eedbd ("target/mips: Convert Vr54xx MACC* opcodes to decodetree")
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
target/mips/tcg/vr54xx_translate.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff
Move the tcg_temp_free_* and tcg_temp_ebb_new_* declarations
and inlines to the new header. These are private to the
implementation, and will prevent tcg_temp_free_* from creeping
back into the guest front ends.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
include/tcg/tcg-te
Translators are no longer required to free tcg temporaries.
Signed-off-by: Richard Henderson
---
Cc: Philippe Mathieu-Daudé
Cc: Aurelien Jarno
Cc: Jiaxun Yang
Cc: Aleksandar Rikalo
---
target/mips/tcg/msa_translate.c | 9 -
1 file changed, 9 deletions(-)
diff --git a/target/mips/tcg
Translators are no longer required to free tcg temporaries.
Signed-off-by: Richard Henderson
---
Cc: Philippe Mathieu-Daudé
Cc: Aurelien Jarno
Cc: Jiaxun Yang
Cc: Aleksandar Rikalo
---
target/mips/tcg/translate.c | 537 +---
1 file changed, 14 insertions(+), 5
Translators are no longer required to free tcg temporaries.
Remove the g1 and g2 members of DisasCompare, as they were
used to track which temps needed to be freed.
Signed-off-by: Richard Henderson
---
Cc: David Hildenbrand
Cc: Ilya Leoshkevich
Cc: Thomas Huth
Cc: qemu-s3...@nongnu.org
---
ta
Translators are no longer required to free tcg temporaries.
Signed-off-by: Richard Henderson
---
Cc: Philippe Mathieu-Daudé
Cc: Aurelien Jarno
Cc: Jiaxun Yang
Cc: Aleksandar Rikalo
---
target/mips/tcg/mips16e_translate.c.inc | 6 --
1 file changed, 6 deletions(-)
diff --git a/target/mip
Translators are no longer required to free tcg temporaries.
Signed-off-by: Richard Henderson
---
Cc: Bastian Koppelmann
---
target/tricore/translate.c | 540 +
1 file changed, 4 insertions(+), 536 deletions(-)
diff --git a/target/tricore/translate.c b/target
Translators are no longer required to free tcg temporaries.
Signed-off-by: Richard Henderson
---
Cc: Philippe Mathieu-Daudé
Cc: Aurelien Jarno
Cc: Jiaxun Yang
Cc: Aleksandar Rikalo
---
target/mips/tcg/nanomips_translate.c.inc | 127 ++-
1 file changed, 10 insertions(+), 1
Translators are no longer required to free tcg temporaries.
Signed-off-by: Richard Henderson
---
Cc: Philippe Mathieu-Daudé
Cc: Aurelien Jarno
Cc: Jiaxun Yang
Cc: Aleksandar Rikalo
---
target/mips/tcg/tx79_translate.c | 41
1 file changed, 41 deletions(-)
di
I've queued the reviewed patches from v2 to tcg-next; these are
the ones that remain. Please review.
Just in case, the tree is
https://gitlab.com/rth7680/qemu.git tcg-free
r~
Richard Henderson (20):
target/i386: Drop tcg_temp_free
target/mips: Drop tcg_temp_free from micromips_translate
Translators are no longer required to free tcg temporaries.
Signed-off-by: Richard Henderson
---
Cc: Philippe Mathieu-Daudé
Cc: Aurelien Jarno
Cc: Jiaxun Yang
Cc: Aleksandar Rikalo
---
target/mips/tcg/vr54xx_translate.c | 4
1 file changed, 4 deletions(-)
diff --git a/target/mips/tcg/v
Translators are no longer required to free tcg temporaries.
Signed-off-by: Richard Henderson
---
Cc: Paolo Bonzini
Cc: Eduardo Habkost
---
target/i386/tcg/translate.c | 41
target/i386/tcg/decode-new.c.inc | 15
target/i386/tcg/emit.c.inc
These were trying to determine if o->in2 was available for
use as a temporary. It's better to just allocate a new one.
Signed-off-by: Richard Henderson
---
Cc: David Hildenbrand
Cc: Ilya Leoshkevich
Cc: Thomas Huth
Cc: qemu-s3...@nongnu.org
---
target/s390x/tcg/translate.c | 20 ++---
This file, and a couple of uses, got left behind when the
tcg stuff was removed from tracetool.
Fixes: 126d4123c50a ("tracing: excise the tcg related from tracetool")
Signed-off-by: Richard Henderson
---
Cc: Stefan Hajnoczi
---
meson.build| 1 -
scripts/tracetool/__init__.
Translators are no longer required to free tcg temporaries.
Signed-off-by: Richard Henderson
---
Cc: Philippe Mathieu-Daudé
Cc: Aurelien Jarno
Cc: Jiaxun Yang
Cc: Aleksandar Rikalo
---
target/mips/tcg/mxu_translate.c | 51 -
1 file changed, 51 deletions(-)
di
Translators are no longer required to free tcg temporaries.
Signed-off-by: Richard Henderson
---
Cc: David Hildenbrand
Cc: Ilya Leoshkevich
Cc: Thomas Huth
Cc: qemu-s3...@nongnu.org
---
target/s390x/tcg/translate_vx.c.inc | 143
1 file changed, 143 deletions(-)
d
Translators are no longer required to free tcg temporaries.
Signed-off-by: Richard Henderson
---
Cc: Philippe Mathieu-Daudé
Cc: Aurelien Jarno
Cc: Jiaxun Yang
Cc: Aleksandar Rikalo
---
target/mips/tcg/micromips_translate.c.inc | 8
1 file changed, 8 deletions(-)
diff --git a/target
These fields are no longer read, so remove them and the writes.
Signed-off-by: Richard Henderson
---
Cc: David Hildenbrand
Cc: Ilya Leoshkevich
Cc: Thomas Huth
Cc: qemu-s3...@nongnu.org
---
target/s390x/tcg/translate.c | 17 -
1 file changed, 17 deletions(-)
diff --git a/targ
Translators are no longer required to free tcg temporaries.
Signed-off-by: Richard Henderson
---
Cc: David Hildenbrand
Cc: Ilya Leoshkevich
Cc: Thomas Huth
Cc: qemu-s3...@nongnu.org
---
target/s390x/tcg/translate.c | 105 ---
1 file changed, 105 deletions(-)
d
Translators are no longer required to free tcg temporaries.
Signed-off-by: Richard Henderson
---
Cc: Philippe Mathieu-Daudé
Cc: Aurelien Jarno
Cc: Jiaxun Yang
Cc: Aleksandar Rikalo
---
target/mips/tcg/octeon_translate.c | 23 ---
1 file changed, 23 deletions(-)
diff --gi
Translators are no longer required to free tcg temporaries.
Signed-off-by: Richard Henderson
---
Cc: Philippe Mathieu-Daudé
Cc: Aurelien Jarno
Cc: Jiaxun Yang
Cc: Aleksandar Rikalo
---
target/mips/tcg/translate_addr_const.c | 7 ---
1 file changed, 7 deletions(-)
diff --git a/target/mip
On 3/3/23 00:49, Richard W.M. Jones wrote:
When CONFIG_PROFILER is set there are various undefined references to
profile_getclock. Include the header which defines this function.
For example:
../tcg/tcg.c: In function ‘tcg_gen_code’:
../tcg/tcg.c:4905:51: warning: implicit declaration of funct
On 3/3/23 15:26, Taylor Simpson wrote:
+/* Generic ops. */
+
+static void last_is_label_use(TCGLabel *l) {
It would be more clear to name this function "add_label_use".
I've used "add_last_as_label_use" to emphasize where the use is coming from.
Thanks.
r~
On 3/3/23 16:27, Taylor Simpson wrote:
You need this series of patches to see this pattern from Hexagon
https://patchew.org/QEMU/20230131225647.25274-1-tsimp...@quicinc.com/
I have an update to that series for your tcg_temp_local_* series, but I'm
wondering if I should wait for your tcg_temp_fr
02.03.2023 11:25, Michael S. Tsirkin wrote:
From: "Dr. David Alan Gilbert"
In bad9c5a516 ("virtio-rng-pci: fix migration compat for vectors") I
fixed the virtio-rng-pci migration compatibility, but it was discovered
that we also need to fix the other aliases of the device for the
transitional c
On Wed, 1 Mar 2023 11:52:42 +
Mark Cave-Ayland wrote:
> I've done a quick grep for similar examples for serial devices that use
> keyboard_layout but it looks like this would be the first.
Thanks again for your reply!
It is probably not a very common solution with hardware in the keyboard
t
> 2023年3月4日 18:18，Richard Henderson 写道：
>
> Translators are no longer required to free tcg temporaries.
>
> Signed-off-by: Richard Henderson
Reviewed-by: Jiaxun Yang
Thanks.
> ---
> 2.34.1
>
MIPS Trickbox is a emulated device present in MIPS's IASIM simulator
for decades. It's capable of managing simulator status, signaling
interrupts, doing DMA and EJTAG signal stimulations.
For now we just use definition of this device and implement power
management related functions.
Signed-off-by
MIPS virt board is design to utilize existing VirtIO infrastures
but also comptitable with MIPS's existing internal simulation tools.
It includes virtio-pci, virtio-mmio, pcie gpex, flash rom, fw_cfg,
goldfish-rtc and MIPS CPS system.
It should be able to cooperate with any MIPS CPU cores.
Signe
Hi there,
This patchset is to add a new machine type for MIPS architecture, which
is purely a VirtIO machine.
It is design to utilize existing VirtIO infrastures but also comptitable
with MIPS's existing internal simulation tools.
It should be able to cooperate with any MIPS core and boot Generi
Hello,
I think this patch is sufficient to remediate the priv ledge escalation via the
repair and catching the VSS com registration boxes that were being invoked
frivolously.
Long term the repair function not validating if the user has admin should be
addressed as well since their is still a
Am 4. März 2023 14:48:20 UTC schrieb BALATON Zoltan :
>The real VIA south bridges implement a PCI IRQ router which is configured
>by the BIOS or the OS. In order to respect these configurations, QEMU
>needs to implement it as well. The real chip may allow routing IRQs from
>internal functions in
Am 4. März 2023 14:48:23 UTC schrieb BALATON Zoltan :
>From: Bernhard Beschow
>
>According to the PCI specification, PCI_INTERRUPT_LINE shall have no
>effect on hardware operations. Now that the VIA south bridges implement
>the internal PCI interrupt router let's be more conformant to the PCI
>
Am 2. März 2023 21:54:56 UTC schrieb Bernhard Beschow :
>
>
>Am 1. März 2023 21:49:37 UTC schrieb "Michael S. Tsirkin" :
>>On Tue, Feb 21, 2023 at 03:39:28PM +, Bernhard Beschow wrote:
>>>
>>>
>>> Am 14. Februar 2023 13:14:29 UTC schrieb Bernhard Beschow
>>> :
>>> >This series mostly clea
Am 13. Februar 2023 16:45:05 UTC schrieb Bernhard Beschow :
>
>
>Am 13. Februar 2023 16:19:55 UTC schrieb Bernhard Beschow :
>>This series contains some cleanups I came across when working on the PC
>>
>>machines. It consists of reducing the usage of global variables and
>>eliminating
>>
>>some
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