Re: [PATCH v4 01/15] vdpa net: move iova tree creation from init to start

On Fri, Mar 3, 2023 at 4:32 AM Jason Wang wrote: > > > 在 2023/3/1 15:01, Eugenio Perez Martin 写道: > > On Mon, Feb 27, 2023 at 8:04 AM Jason Wang wrote: > >> > >> 在 2023/2/24 23:54, Eugenio Pérez 写道: > >>> Only create iova_tree if and when it is needed. > >>> > >>> The cleanup keeps being responsi

Re: [PATCH v2 0/7] hw/net/eepro100: Finish QDev conversion

On Tue, Feb 28, 2023 at 9:40 PM Philippe Mathieu-Daudé wrote: > > Hi Jason, do you Ack this series? Sorry for the late reply. I've queued this series. Thanks > > On 23/2/23 16:16, Philippe Mathieu-Daudé wrote: > > ping > > > > On 13/2/23 11:10, Philippe Mathieu-Daudé wrote: > >> Convert EEPRO1

Re: [virtio-dev] [RFC QEMU] docs: vhost-user: Add custom memory mapping support

On 01-03-23, 10:47, Stefan Hajnoczi wrote: > Resend - for some reason my email didn't make it out. How about this (will send a formal patch later). Author: Viresh Kumar Date: Tue Feb 21 14:36:30 2023 +0530 docs: vhost-user: Add Xen specific memory mapping support The current model of

Re: [PATCH 2/5] iotests: allow test discovery before building

On 02/03/2023 19.46, Daniel P. Berrangé wrote: The 'check' script can be invoked in "dry run" mode, in which case it merely does test discovery and prints out all their names. Despite only doing test discovery it still validates that the various QEMU binaries can be found. This makes it impossibl

Re: [PATCH 4/5] iotests: print TAP protocol version when reporting tests

On 02/03/2023 19.46, Daniel P. Berrangé wrote: Recently meson started complaining that TAP test reports don't include the TAP protocol version. While this warning is bogus and has since been removed from Meson, it looks like good practice to include this header going forward. The GLib library tes

Re: [PATCH] hw/acpi: Set memory regions to native endian as a work around

On Tue, Feb 21, 2023 at 03:02:41PM +0100, Paolo Bonzini wrote: > On 2/21/23 13:48, BALATON Zoltan wrote: > > My patch works and don't see what else could it break. > > I strongly suspect that your patch, while fixing access to one byte of the > (2-byte) registers, breaks access to the other byte.

Re: [PATCH 0/5] iotests: make meson aware of individual I/O tests

On 02/03/2023 19.46, Daniel P. Berrangé wrote: To just repeat the patch 5 description... Currently meson registers a single test that invokes an entire group of I/O tests, hiding the test granularity from meson. There are various downsides of doing this * You cannot ask 'meson test' to invoke

Re: [PATCH v4 04/26] gdbstub: clean-up indent on gdb_exit

On 3/2/23 16:08, Alex Bennée wrote: Otherwise checkpatch will throw a hissy fit on the later patches that split this function up. Signed-off-by: Alex Bennée --- Reviewed-by: Daniel Henrique Barboza gdbstub/gdbstub.c | 28 ++-- 1 file changed, 14 insertions(+),

[PULL 02/59] target/riscv: do not mask unsupported QEMU extensions in write_misa()

From: Daniel Henrique Barboza The masking done using env->misa_ext_mask already filters any extension that QEMU doesn't support. If the hart supports the extension then QEMU supports it as well. If the masking done by env->misa_ext_mask is somehow letting unsupported QEMU extensions pass by, mis

[PULL 12/59] target/riscv: Fix the relationship between Zhinxmin and Zhinx

From: Weiwei Li Just like zfh and zfhmin, Zhinxmin is part of Zhinx so Zhinxmin will be enabled when Zhinx is enabled. Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Daniel Henrique Barboza Message-ID: <20230215020539.4788-3-liwei...@iscas.ac.cn> Signed-off-by: Palmer Dabb

[PULL 03/59] target/riscv: allow MISA writes as experimental

From: Daniel Henrique Barboza At this moment, and apparently since ever, we have no way of enabling RISCV_FEATURE_MISA. This means that all the code from write_misa(), all the nuts and bolts that handles how to properly write this CSR, has always been a no-op as well because write_misa() will alw

[PULL 18/59] target/riscv: Simplify check for Zve32f and Zve64f

From: Weiwei Li V/Zve64f depend on Zve32f, so we can only check Zve32f in these cases. Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Daniel Henrique Barboza Message-ID: <20230215020539.4788-9-liwei...@iscas.ac.cn> Signed-off-by: Palmer Dabbelt --- target/riscv/cpu_helpe

[PULL 22/59] target/riscv: Fix check for vector load/store instructions when EEW=64

From: Weiwei Li The V extension supports all vector load and store instructions except the V extension does not support EEW=64 for index values when XLEN=32. (Section 18.3) Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Daniel Henrique Barboza Message-ID: <20230215020539.4

[PULL 07/59] target/riscv: remove RISCV_FEATURE_PMP

From: Daniel Henrique Barboza RISCV_FEATURE_PMP is being set via riscv_set_feature() by mirroring the cpu->cfg.pmp flag. Use the flag instead. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Weiwei Li Reviewed-by: Bin Meng Reviewed-by: Andrew Jones Reviewed-by: LIU Zhiwei Message-ID: <2

[PULL 45/59] target/riscv: Add support for Zicond extension

From: Weiwei Li The spec can be found in https://github.com/riscv/riscv-zicond. Two instructions are added: - czero.eqz: Moves zero to a register rd, if the condition rs2 is equal to zero, otherwise moves rs1 to rd. - czero.nez: Moves zero to a register rd, if the condition rs2 is nonzero

[PULL 37/59] target/riscv: Allow debugger to access user timer and counter CSRs

From: Bin Meng At present user timer and counter CSRs are not reported in the CSR XML hence gdb cannot access them. Fix it by adding a debugger check in their predicate() routine. Signed-off-by: Bin Meng Reviewed-by: Weiwei Li Reviewed-by: LIU Zhiwei Message-ID: <20230228104035.1879882-14-bm

[PULL 24/59] target/riscv: Expose properties for Zv* extensions

From: Weiwei Li Expose Zve64d,Zvfh,Zvfhmin properties. Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Daniel Henrique Barboza Message-ID: <20230215020539.4788-15-liwei...@iscas.ac.cn> Signed-off-by: Palmer Dabbelt --- target/riscv/cpu.c | 7 +++ 1 file changed, 7 ins

[PULL 08/59] hw/riscv/virt.c: do not use RISCV_FEATURE_MMU in create_fdt_socket_cpus()

From: Daniel Henrique Barboza Read cpu_ptr->cfg.mmu directly. As a bonus, use cpu_ptr in riscv_isa_string(). Signed-off-by: Daniel Henrique Barboza Reviewed-by: Weiwei Li Reviewed-by: Bin Meng Reviewed-by: Andrew Jones Reviewed-by: LIU Zhiwei Message-ID: <20230222185205.355361-9-dbarb...@ve

[PULL 53/59] target/riscv: Export Svadu property

From: Weiwei Li Set it default true for backward compatibility Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Daniel Henrique Barboza Message-ID: <20230224040852.37109-7-liwei...@iscas.ac.cn> Signed-off-by: Palmer Dabbelt --- target/riscv/cpu.c | 3 +++ 1 file changed, 3

[PULL 38/59] target/riscv: Allow debugger to access seed CSR

From: Bin Meng At present seed CSR is not reported in the CSR XML hence gdb cannot access it. Fix it by adding a debugger check in its predicate() routine. Signed-off-by: Bin Meng Reviewed-by: Weiwei Li Reviewed-by: LIU Zhiwei Message-ID: <20230228104035.1879882-15-bm...@tinylab.org> Signed-

[PULL 25/59] target/riscv: gdbstub: Check priv spec version before reporting CSR

From: Bin Meng The gdbstub CSR XML is dynamically generated according to the result of the CSR predicate() result. This has been working fine until commit 7100fe6c2441 ("target/riscv: Enable privileged spec version 1.12") introduced the privilege spec version check in riscv_csrrw_check(). When d

[PULL 23/59] target/riscv: Simplify check for EEW = 64 in trans_rvv.c.inc

From: Weiwei Li Only V extension supports EEW = 64 in these cases: Zve64* extensions don't support EEW = 64 in these cases as commented before the check. Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Daniel Henrique Barboza Message-ID: <20230215020539.4788-14-liwei...@isc

[PULL 04/59] target/riscv: remove RISCV_FEATURE_DEBUG

From: Daniel Henrique Barboza RISCV_FEATURE_DEBUG will always follow the value defined by cpu->cfg.debug flag. Read the flag instead. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Weiwei Li Reviewed-by: Bin Meng Reviewed-by: Andrew Jones Reviewed-by: LIU Zhiwei Message-ID: <2023022218

[PULL 27/59] target/riscv: Use g_assert() for the predicate() NULL check

From: Bin Meng At present riscv_csrrw_check() checks the CSR predicate() against NULL and throws RISCV_EXCP_ILLEGAL_INST if it is NULL. But this is a pure software check, and has nothing to do with the emulation of the hardware behavior, thus it is inappropriate to return illegal instruction exce

[PULL 20/59] target/riscv: Remove redundunt check for zve32f and zve64f

From: Weiwei Li Require_zve32/64f have been overlapped by require_rvf/require_scale_rvf. Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Daniel Henrique Barboza Message-ID: <20230215020539.4788-11-liwei...@iscas.ac.cn> [Palmer: commit text] Signed-off-by: Palmer Dabbelt --

[PULL 47/59] hw/riscv: Move the dtb load bits outside of create_fdt()

From: Bin Meng Move the dtb load bits outside of create_fdt(), and put it explicitly in sifive_u_machine_init() and virt_machine_init(). With such change create_fdt() does exactly what its function name tells us. Suggested-by: Daniel Henrique Barboza Signed-off-by: Bin Meng Reviewed-by: Daniel

[PULL 51/59] target/riscv: Add *envcfg.PBMTE related check in address translation

From: Weiwei Li menvcfg.PBMTE bit controls whether the Svpbmt extension is available for use in S-mode and G-stage address translation. henvcfg.PBMTE bit controls whether the Svpbmt extension is available for use in VS-stage address translation. Set *envcfg.PBMTE default true for backward compa

[PULL 34/59] target/riscv: Avoid reporting odd-numbered pmpcfgX in the CSR XML for RV64

From: Bin Meng At present the odd-numbered PMP configuration registers for RV64 are reported in the CSR XML by QEMU gdbstub. However these registers do not exist on RV64 so trying to access them from gdb results in 'E14'. Move the pmpcfgX index check from the actual read/write routine to the PMP

[PULL 42/59] target/riscv: Group all predicate() routines together

From: Bin Meng Move sstc()/sstc32() to where all predicate() routines live, and smstateen_acc_ok() to near {read,write}_xenvcfg(). Signed-off-by: Bin Meng Reviewed-by: Weiwei Li Message-ID: <20230228104035.1879882-19-bm...@tinylab.org> Signed-off-by: Palmer Dabbelt --- target/riscv/csr.c | 1

[PULL 54/59] target/riscv/csr.c: use env_archcpu() in ctr()

From: Daniel Henrique Barboza We don't need to use env_cpu() and CPUState(). Signed-off-by: Daniel Henrique Barboza Reviewed-by: Richard Henderson Message-ID: <20230224174520.92490-2-dbarb...@ventanamicro.com> Signed-off-by: Palmer Dabbelt --- target/riscv/csr.c | 3 +-- 1 file changed, 1 in

[PULL 44/59] RISC-V: XTheadMemPair: Remove register restrictions for store-pair

From: Christoph Müllner The XTheadMemPair does not define any restrictions for store-pair instructions (th.sdd or th.swd). However, the current code enforces the restrictions that are required for load-pair instructions. Let's fix this by removing this code. Signed-off-by: Christoph Müllner Rev

[PULL 05/59] target/riscv/cpu.c: error out if EPMP is enabled without PMP

From: Daniel Henrique Barboza Instead of silently ignoring the EPMP setting if there is no PMP available, error out informing the user that EPMP depends on PMP support: $ ./qemu-system-riscv64 -cpu rv64,pmp=false,x-epmp=true qemu-system-riscv64: Invalid configuration: EPMP requires PMP support

[PULL 14/59] target/riscv: Add cfg properties for Zv* extensions

From: Weiwei Li Add properties for Zve64d,Zvfh,Zvfhmin extensions. Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Daniel Henrique Barboza Message-ID: <20230215020539.4788-5-liwei...@iscas.ac.cn> Signed-off-by: Palmer Dabbelt --- target/riscv/cpu.h | 3 +++ 1 file changed

[PULL 49/59] target/riscv: Fix the relationship of PBMTE/STCE fields between menvcfg and henvcfg

From: Weiwei Li henvcfg.PBMTE/STCE are read-only zero if menvcfg.PBMTE/STCE are zero. Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Daniel Henrique Barboza Message-ID: <20230224040852.37109-3-liwei...@iscas.ac.cn> Signed-off-by: Palmer Dabbelt --- target/riscv/csr.c | 1

[PULL 35/59] target/riscv: gdbstub: Turn on debugger mode before calling CSR predicate()

From: Bin Meng Since commit 94452ac4cf26 ("target/riscv: remove fflags, frm, and fcsr from riscv-*-fpu.xml") the 3 FPU CSRs are removed from the XML target decription. The original intent of that commit was based on the assumption that the 3 FPU CSRs will show up in the riscv-csr.xml so the ones

[PULL 36/59] target/riscv: gdbstub: Drop the vector CSRs in riscv-vector.xml

From: Bin Meng It's worth noting that the vector CSR predicate() has a similar run-time check logic to the FPU CSR. With the previous patch our gdbstub can correctly report these vector CSRs via the CSR xml. Commit 719d3561b269 ("target/riscv: gdb: support vector registers for rv64 & rv32") ins

[PULL 16/59] target/riscv: Add property check for Zvfh{min} extensions

From: Weiwei Li Add check for Zvfh and Zvfhmin. Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Daniel Henrique Barboza Message-ID: <20230215020539.4788-7-liwei...@iscas.ac.cn> [Palmer: commit text] Signed-off-by: Palmer Dabbelt --- target/riscv/cpu.c | 14 ++

[PULL 58/59] target/riscv/vector_helper.c: create vext_set_tail_elems_1s()

From: Daniel Henrique Barboza Commit 752614cab8e6 ("target/riscv: rvv: Add tail agnostic for vector load / store instructions") added code to set the tail elements to 1 in the end of vext_ldst_stride(), vext_ldst_us(), vext_ldst_index() and vext_ldff(). Aside from a env->vl versus an evl value be

[PULL 28/59] target/riscv: gdbstub: Minor change for better readability

From: Bin Meng Use a variable 'base_reg' to represent cs->gdb_num_regs so that the call to ricsv_gen_dynamic_vector_xml() can be placed in one single line for better readability. Signed-off-by: Bin Meng Reviewed-by: Weiwei Li Reviewed-by: LIU Zhiwei Message-ID: <20230228104035.1879882-5-bm...

[PULL 26/59] target/riscv: Add some comments to clarify the priority policy of riscv_csrrw_check()

From: Bin Meng The priority policy of riscv_csrrw_check() was once adjusted in commit eacaf4401956 ("target/riscv: Fix priority of csr related check in riscv_csrrw_check") whose commit message says the CSR existence check should come before the access control check, but the code changes did not

[PULL 13/59] target/riscv: Simplify the check for Zfhmin and Zhinxmin

From: Weiwei Li We needn't check Zfh and Zhinx in these instructions. Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Daniel Henrique Barboza Message-ID: <20230215020539.4788-4-liwei...@iscas.ac.cn> Signed-off-by: Palmer Dabbelt --- target/riscv/insn_trans/trans_rvzfh.c.i

Re: [PATCH v4 09/15] vdpa: add vdpa net migration state notifier

On Fri, Mar 3, 2023 at 4:34 AM Jason Wang wrote: > > > 在 2023/3/2 03:26, Eugenio Perez Martin 写道: > > On Mon, Feb 27, 2023 at 9:08 AM Jason Wang wrote: > >> > >> 在 2023/2/24 23:54, Eugenio Pérez 写道: > >>> This allows net to restart the device backend to configure SVQ on it. > >>> > >>> Ideally, t

[PULL 11/59] target/riscv: Fix the relationship between Zfhmin and Zfh

From: Weiwei Li Zfhmin is part of Zfh, so Zfhmin will be enabled when Zfh is enabled. Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Daniel Henrique Barboza Message-ID: <20230215020539.4788-2-liwei...@iscas.ac.cn> Signed-off-by: Palmer Dabbelt --- target/riscv/cpu.c | 6

[PULL 33/59] target/riscv: Simplify getting RISCVCPU pointer from env

From: Bin Meng Use env_archcpu() to get RISCVCPU pointer from env directly. Signed-off-by: Bin Meng Reviewed-by: Weiwei Li Reviewed-by: LIU Zhiwei Message-ID: <20230228104035.1879882-10-bm...@tinylab.org> Signed-off-by: Palmer Dabbelt --- target/riscv/csr.c | 36

[PULL 06/59] target/riscv: remove RISCV_FEATURE_EPMP

From: Daniel Henrique Barboza RISCV_FEATURE_EPMP is always set to the same value as the cpu->cfg.epmp flag. Use the flag directly. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Weiwei Li Reviewed-by: Bin Meng Reviewed-by: Andrew Jones Reviewed-by: LIU Zhiwei Message-ID: <2023022218520

[PULL 31/59] target/riscv: Use 'bool' type for read_only

From: Bin Meng The read_only variable is currently declared as an 'int', but it should really be a 'bool'. Signed-off-by: Bin Meng Reviewed-by: Weiwei Li Reviewed-by: LIU Zhiwei Message-ID: <20230228104035.1879882-8-bm...@tinylab.org> Signed-off-by: Palmer Dabbelt --- target/riscv/csr.c | 2

[PULL 40/59] target/riscv: Allow debugger to access sstc CSRs

From: Bin Meng At present with a debugger attached sstc CSRs can only be accssed when CPU is in M-mode, or configured correctly. Fix it by adjusting their predicate() routine logic so that the static config check comes before the run-time check, as well as adding a debugger check. Signed-off-by

[PULL 15/59] target/riscv: Fix relationship between V, Zve*, F and D

From: Weiwei Li Add dependence chain: * V => Zve64d => Zve64f => Zve32f => F * V => Zve64d => D Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Daniel Henrique Barboza Message-ID: <20230215020539.4788-6-liwei...@iscas.ac.cn> Signed-off-by: Palmer Dabbelt --- target/risc

[PULL 30/59] target/riscv: Coding style fixes in csr.c

From: Bin Meng Fix various places that violate QEMU coding style: - correct multi-line comment format - indent to opening parenthesis Signed-off-by: Bin Meng Reviewed-by: Weiwei Li Reviewed-by: LIU Zhiwei Message-ID: <20230228104035.1879882-7-bm...@tinylab.org> Signed-off-by: Palmer Dabbelt

[PULL 00/59] Fifth RISC-V PR for QEMU 8.0

ository at: https://gitlab.com/palmer-dabbelt/qemu.git tags/pull-riscv-to-apply-20230303 for you to fetch changes up to 37151032989ecf6e7ce8b65bc7bcb400d0318b2c: Merge patch series "target/riscv: some vector_helper.c cleanups&quo

[PULL 19/59] target/riscv: Replace check for F/D to Zve32f/Zve64d in trans_rvv.c.inc

From: Weiwei Li Check for Zve32f/Zve64d can overlap check for F/D. Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Daniel Henrique Barboza Message-ID: <20230215020539.4788-10-liwei...@iscas.ac.cn> Signed-off-by: Palmer Dabbelt --- target/riscv/insn_trans/trans_rvv.c.inc |

[PULL 59/59] target/riscv/vector_helper.c: avoid env_archcpu() when reading RISCVCPUConfig

From: Daniel Henrique Barboza This file has several uses of env_archcpu() that are used solely to read cfg->vlen. Use the new riscv_cpu_cfg() inline instead. Suggested-by: Weiwei Li Signed-off-by: Daniel Henrique Barboza Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Weiwei Li Message-ID: <

[PULL 21/59] target/riscv: Add support for Zvfh/zvfhmin extensions

From: Weiwei Li Zvfh supports vector float point instructions with SEW = 16 and supports conversions between 8-bit integers and binary16 values. Zvfhmin supports vfwcvt.f.f.v and vfncvt.f.f.w instructions. Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Daniel Henrique Barb

[PULL 50/59] target/riscv: Add csr support for svadu

From: Weiwei Li Add ext_svadu property Add HADE field in *envcfg: * menvcfg.HADE is read-only zero if Svadu is not implemented. * henvcfg.HADE is read-only zero if menvcfg.HADE is zero. Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Daniel Henrique Barboza Message-ID: <202

[PULL 55/59] target/riscv/csr.c: simplify mctr()

From: Daniel Henrique Barboza Use riscv_cpu_cfg() to retrieve pmu_num. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Weiwei Li Reviewed-by: Richard Henderson Message-ID: <20230224174520.92490-3-dbarb...@ventanamicro.com> Signed-off-by: Palmer Dabbelt --- target/riscv/csr.c | 5 ++---

[PULL 56/59] target/riscv/csr.c: use riscv_cpu_cfg() to avoid env_cpu() pointers

From: Daniel Henrique Barboza A common trend in this file is to retrieve a RISCVCPU pointer by first retrieving a CPUState pointer via env_cpu(). The CPU pointer is used only to access the RISCVCPUConfig object and nothing else. Let's use riscv_cpu_cfg() to access what we need directly without t

[PULL 46/59] hw/riscv: Skip re-generating DT nodes for a given DTB

From: Bin Meng Launch qemu-system-riscv64 with a given dtb for 'sifive_u' and 'virt' machines, QEMU complains: qemu_fdt_add_subnode: Failed to create subnode /soc: FDT_ERR_EXISTS The whole DT generation logic should be skipped when a given DTB is present. Fixes: b1f19f238cae ("hw/riscv: writ

[PULL 43/59] target/riscv: Fix checking of whether instruciton at 'pc_next' spans pages

From: Shaobo Song This bug has a noticeable behavior of falling back to the main loop and respawning a redundant translation block including a single instruction when the end address of the compressive instruction is exactly on a page boundary, and slows down running system performance. Signed-o

[PULL 32/59] target/riscv: Simplify {read, write}_pmpcfg() a little bit

From: Bin Meng Use the register index that has already been calculated in the pmpcfg_csr_{read,write} call. Signed-off-by: Bin Meng Reviewed-by: Weiwei Li Reviewed-by: LIU Zhiwei Message-ID: <20230228104035.1879882-9-bm...@tinylab.org> Signed-off-by: Palmer Dabbelt --- target/riscv/csr.c |

[PULL 52/59] target/riscv: Add *envcfg.HADE related check in address translation

From: Weiwei Li When menvcfg.HADE is 1, hardware updating of PTE A/D bits is enabled during single-stage address translation. When the hypervisor extension is implemented, if menvcfg.HADE is 1, hardware updating of PTE A/D bits is enabled during G-stage address translation. Set *envcfg.HADE defa

[PULL 29/59] target/riscv: gdbstub: Do not generate CSR XML if Zicsr is disabled

From: Bin Meng There is no need to generate the CSR XML if the Zicsr extension is not enabled. Signed-off-by: Bin Meng Reviewed-by: Weiwei Li Reviewed-by: LIU Zhiwei Message-ID: <20230228104035.1879882-6-bm...@tinylab.org> Signed-off-by: Palmer Dabbelt --- target/riscv/gdbstub.c | 9 ++-

Re: [PATCH 1/4] pnv_phb4_pec: Keep track of instantiated PHBs

On 3/2/23 19:21, Philippe Mathieu-Daudé wrote: Hi Frederic, On 2/3/23 17:37, Frederic Barrat wrote: Add an array on the PEC object to keep track of the PHBs which are instantiated. The array can be sparsely populated when using user-created PHBs. It will be useful for the next patch to only

[PULL 39/59] target/riscv: Allow debugger to access {h, s}stateen CSRs

From: Bin Meng At present {h,s}stateen CSRs are not reported in the CSR XML hence gdb cannot access them. Fix it by adjusting their predicate() routine logic so that the static config check comes before the run-time check, as well as adding a debugger check. Signed-off-by: Bin Meng Reviewed-by

[PULL 10/59] target/riscv/cpu: remove CPUArchState::features and friends

From: Daniel Henrique Barboza The attribute is no longer used since we can retrieve all the enabled features in the hart by using cpu->cfg instead. Remove env->feature, riscv_feature() and riscv_set_feature(). We also need to bump vmstate_riscv_cpu version_id and minimal_version_id since 'featur

[PULL 48/59] target/riscv: Fix the relationship between menvcfg.PBMTE/STCE and Svpbmt/Sstc extensions

From: Weiwei Li menvcfg.PBMTE/STCE are read-only zero if Svpbmt/Sstc are not implemented. Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Daniel Henrique Barboza Message-ID: <20230224040852.37109-2-liwei...@iscas.ac.cn> Signed-off-by: Palmer Dabbelt --- target/riscv/csr.c

[PULL 09/59] target/riscv: remove RISCV_FEATURE_MMU

From: Daniel Henrique Barboza RISCV_FEATURE_MMU is set whether cpu->cfg.mmu is set, so let's just use the flag directly instead. With this change the enum is also removed. It is worth noticing that this enum, and all the RISCV_FEATURES_* that were contained in it, predates the existence of the c

[PULL 01/59] target/riscv: introduce riscv_cpu_cfg()

From: Daniel Henrique Barboza We're going to do changes that requires accessing the RISCVCPUConfig struct from the RISCVCPU, having access only to a CPURISCVState 'env' pointer. Add a helper to make the code easier to read. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Bin Meng Reviewed-

[PATCH v2] tcg: Include "qemu/timer.h" for profile_getclock

When CONFIG_PROFILER is set there are various undefined references to profile_getclock. Include the header which defines this function. For example: ../tcg/tcg.c: In function ‘tcg_gen_code’: ../tcg/tcg.c:4905:51: warning: implicit declaration of function ‘profile_getclock’ [-Wimplicit-function-

[PULL 41/59] target/riscv: Drop priv level check in mseccfg predicate()

From: Bin Meng riscv_csrrw_check() already does the generic privilege level check hence there is no need to do the specific M-mode access check in the mseccfg predicate(). With this change debugger can access the mseccfg CSR anytime. Signed-off-by: Bin Meng Reviewed-by: Weiwei Li Message-ID:

[PULL 17/59] target/riscv: Indent fixes in cpu.c

From: Weiwei Li Fix indent problems in vector related check. Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Daniel Henrique Barboza Message-ID: <20230215020539.4788-8-liwei...@iscas.ac.cn> Signed-off-by: Palmer Dabbelt --- target/riscv/cpu.c | 44 ++--

[PULL 57/59] target/riscv/csr.c: avoid env_archcpu() usages when reading RISCVCPUConfig

From: Daniel Henrique Barboza Retrieving the CPU pointer using env_archcpu() just to access cpu->cfg can be avoided by using riscv_cpu_cfg(). Suggested-by: LIU Zhiwei Signed-off-by: Daniel Henrique Barboza Reviewed-by: Weiwei Li Reviewed-by: Richard Henderson Message-ID: <20230224174520.9249

Re: [PATCH 0/5] iotests: make meson aware of individual I/O tests

On Fri, Mar 03, 2023 at 09:30:39AM +0100, Thomas Huth wrote: > On 02/03/2023 19.46, Daniel P. Berrangé wrote: > > To just repeat the patch 5 description... > > > > Currently meson registers a single test that invokes an entire group of > > I/O tests, hiding the test granularity from meson. There a

Re: [PATCH v4 12/15] vdpa: block migration if device has unsupported features

On Fri, Mar 3, 2023 at 4:48 AM Jason Wang wrote: > > > 在 2023/3/2 03:32, Eugenio Perez Martin 写道: > > On Mon, Feb 27, 2023 at 9:20 AM Jason Wang wrote: > >> On Mon, Feb 27, 2023 at 4:15 PM Jason Wang wrote: > >>> > >>> 在 2023/2/24 23:54, Eugenio Pérez 写道: > A vdpa net device must initialize

Re: [PATCH] scsi: megasas: Internal cdbs have 16-byte length

Am 28.02.23 um 18:11 schrieb Guenter Roeck: > Host drivers do not necessarily set cdb_len in megasas io commands. > With commits 6d1511cea0 ("scsi: Reject commands if the CDB length > exceeds buf_len") and fe9d8927e2 ("scsi: Add buf_len parameter to > scsi_req_new()"), this results in failures to b

Re: [PATCH] tests/qtest/migration-test: Disable migration/multifd/tcp/plain/cancel

Peter Maydell wrote: > migration-test has been flaky for a long time, both in CI and > otherwise: > > https://gitlab.com/qemu-project/qemu/-/jobs/3806090216 > (a FreeBSD job) > 32/648 > ERROR:../tests/qtest/migration-helpers.c:205:wait_for_migration_status: > assertion failed: (g_test_timer_el

Re: [PATCH] vhost: accept VIRTIO_F_ORDER_PLATFORM as a valid SVQ feature

On Fri, Mar 3, 2023 at 12:31 AM Michael S. Tsirkin wrote: > > On Thu, Mar 02, 2023 at 03:47:48PM +0100, Eugenio Perez Martin wrote: > > On Thu, Mar 2, 2023 at 12:43 PM Michael S. Tsirkin wrote: > > > > > > On Thu, Mar 02, 2023 at 12:30:52PM +0100, Eugenio Perez Martin wrote: > > > > > You need to

Re: [PATCH] tests/qtest/migration-test: Disable migration/multifd/tcp/plain/cancel

Daniel P. Berrangé wrote: > On Thu, Mar 02, 2023 at 05:22:11PM +, Peter Maydell wrote: >> migration-test has been flaky for a long time, both in CI and >> otherwise: >> >> https://gitlab.com/qemu-project/qemu/-/jobs/3806090216 >> (a FreeBSD job) >> 32/648 >> ERROR:../tests/qtest/migration-

Re: [PATCH RFC 0/4] memory: Fix (/ Discuss) a few rcu issues

On 02.03.23 22:50, Peter Xu wrote: On Thu, Mar 02, 2023 at 04:11:56PM +0100, David Hildenbrand wrote: I guess the main concern here would be overhead from gabbing/releasing the BQL very often, and blocking the BQL while we're eventually in the kernel, clearing bitmaps, correct? More or less ye

Re: [PATCH] tests/qtest/migration-test: Disable migration/multifd/tcp/plain/cancel

On Fri, Mar 03, 2023 at 10:10:28AM +0100, Juan Quintela wrote: > Daniel P. Berrangé wrote: > > On Thu, Mar 02, 2023 at 05:22:11PM +, Peter Maydell wrote: > >> migration-test has been flaky for a long time, both in CI and > >> otherwise: > >> > >> https://gitlab.com/qemu-project/qemu/-/jobs/38

RE: Future of icount discussion for next KVM call?

On Thursday, February 16, 2023 10:36 PM, Wang, Wei W wrote: > > On Thursday, February 16, 2023 9:57 PM, Juan Quintela wrote: > > > Just to see what we are having now: > > > > > > - single qemu binary moved to next slot (moved to next week?) > > > Phillipe proposal > > > - TDX migration: we have t

Re: [PATCH] vhost: accept VIRTIO_F_ORDER_PLATFORM as a valid SVQ feature

On Fri, Mar 03, 2023 at 10:08:17AM +0100, Eugenio Perez Martin wrote: > On Fri, Mar 3, 2023 at 12:31 AM Michael S. Tsirkin wrote: > > > > On Thu, Mar 02, 2023 at 03:47:48PM +0100, Eugenio Perez Martin wrote: > > > On Thu, Mar 2, 2023 at 12:43 PM Michael S. Tsirkin > > > wrote: > > > > > > > > On

Re: [PATCH v5 4/7] hw/ppc/pegasos2: Fix PCI interrupt routing

Hi, It seems that I can't pick this patch standalone. It will break pegasos2 boot without patches 2 and 3 that comes beforehand. Phil, this patch already has my ack, so feel free to slide it together with patches 2 and 3 in your PR. Thanks, Daniel On 2/28/23 21:17, BALATON Zoltan wrote: Acc

Re: [PATCH 1/4] pnv_phb4_pec: Keep track of instantiated PHBs

On 3/2/23 13:37, Frederic Barrat wrote: Add an array on the PEC object to keep track of the PHBs which are instantiated. The array can be sparsely populated when using user-created PHBs. It will be useful for the next patch to only export instantiated PHBs in the device tree. Signed-off-by: F

Re: [PATCH 2/4] pnv_phb4_pec: Only export existing PHBs to the device tree

On 3/2/23 13:37, Frederic Barrat wrote: So far, we were always exporting all possible PHBs to the device tree. It works well when using the default config but it potentially adds non-existing devices when using '-nodefaults' and user-created PHBs, causing the firmware (skiboot) to report error

Re: [PATCH 3/4] pnv_phb4_pec: Move pnv_phb4_get_pec() to rightful file

On 3/2/23 13:37, Frederic Barrat wrote: The function pnv_phb4_get_pec() exposes some internals of the PEC and PHB logic, yet it was in the higher level hw/ppc/pnv.c file for historical reasons: P8 implements the PHBs from pnv.c directly, but on P9/P10, it's done through the CEC model, which ha

Re: [PATCH 4/4] pnv_phb4_pec: Simplify/align code to parent user-created PHBs

On 3/2/23 13:37, Frederic Barrat wrote: When instantiating a user-created PHB on P9/P10, we don't really have a reason any more to go through an indirection in pnv_chip_add_phb() in pnv.c, we can go straight to the right function in pnv_phb4_pec.c. That way, default PHBs and user-created PHBs

Re: [PATCH v2] tcg: Include "qemu/timer.h" for profile_getclock

On 3/3/23 09:49, Richard W.M. Jones wrote: When CONFIG_PROFILER is set there are various undefined references to profile_getclock. Include the header which defines this function. For example: ../tcg/tcg.c: In function ‘tcg_gen_code’: ../tcg/tcg.c:4905:51: warning: implicit declaration of funct

Re: [PATCH 0/4] user-created PHB cleanup

On 3/2/23 13:37, Frederic Barrat wrote: A short series with some cleanup around user-created PHB. The main point is to remove errors seen from the firmware (skiboot) when using user-created PHBs, as we were always showing all the default PHBs in the device tree, so skiboot tried to probe non-e

Re: [PATCH 5/5] iotests: register each I/O test separately with meson

On 02/03/2023 19.46, Daniel P. Berrangé wrote: Currently meson registers a single test that invokes an entire group of I/O tests, hiding the test granularity from meson. There are various downsides of doing this * You cannot ask 'meson test' to invoke a single I/O test * The meson test timeo

Re: [PATCH v2] vfio: Fix vfio_get_dev_region() trace event

On 3/3/23 08:43, Cédric Le Goater wrote: From: Cédric Le Goater Simply revert 'x8' to fix the typo and remove the ending '8' Fixes: e61a424f05 ("vfio: Create device specific region info helper") Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1526 Signed-off-by: Cédric Le Goater ---

Re: Emulating graviton G3

Cc'ing qemu-arm@ list On 3/3/23 08:20, Robert Henry wrote: I cannot figure out how to make QEMU TCG emulate aarch64 Graviton G3. I'm working against master/head of the QEMU source. I come up with feature names by consulting https://marcin.juszkiewicz.com.pl/download/tables/arm-socs.html

Re: [PATCH 0/5] iotests: make meson aware of individual I/O tests

On Fri, Mar 03, 2023 at 08:53:32AM +, Daniel P. Berrangé wrote: > On Fri, Mar 03, 2023 at 09:30:39AM +0100, Thomas Huth wrote: > > On 02/03/2023 19.46, Daniel P. Berrangé wrote: > > > To just repeat the patch 5 description... > > > > > > Currently meson registers a single test that invokes an

Re: regression: insmod module failed in VM with nvdimm on #forregzbot

[TLDR: This mail in primarily relevant for Linux regression tracking. A change or fix related to the regression discussed in this thread was posted or applied, but it did not use a Link: tag to point to the report, as Linus and the documentation call for. Things happen, no worries -- but now the re

Re: [PATCH v4.5 26/29] gdbstub: Remove gdb_do_syscallv

On 3/3/23 03:58, Richard Henderson wrote: This function is unused, except to implement gdb_do_syscall. Fold the implementations together. Signed-off-by: Richard Henderson --- include/gdbstub/syscalls.h | 11 --- gdbstub/syscalls.c | 26 ++ 2 files cha

Re: [PATCH v4.5 27/29] gdbstub: Adjust gdb_do_syscall to only use uint32_t and uint64_t

On 3/3/23 03:58, Richard Henderson wrote: Pass %x as uint32_t and %lx as uint64_t; pass the address of %s as uint64_t and the length as uint32_t. Add casts in semihosting/syscalls.c from target_ulong to uint64_t; add casts from int to uint32_t for clarity. Signed-off-by: Richard Henderson ---

Re: [PATCH v2] vfio: Fix vfio_get_dev_region() trace event

On 3/3/23 10:34, Philippe Mathieu-Daudé wrote: On 3/3/23 08:43, Cédric Le Goater wrote: From: Cédric Le Goater Simply revert 'x8' to fix the typo and remove the ending '8' Fixes: e61a424f05 ("vfio: Create device specific region info helper") Resolves: https://gitlab.com/qemu-project/qemu/-/is

Re: [PATCH v4.5 28/29] gdbstub: Build syscall.c once

On 3/3/23 03:58, Richard Henderson wrote: There is no longer anything target specific. Signed-off-by: Richard Henderson --- gdbstub/syscalls.c | 5 + gdbstub/meson.build | 3 +-- 2 files changed, 2 insertions(+), 6 deletions(-) Reviewed-by: Philippe Mathieu-Daudé

Re: [PATCH v2 0/6] Deprecate support for 32-bit x86 and arm hosts

On 02/03/2023 23.07, Philippe Mathieu-Daudé wrote: On 2/3/23 17:31, Thomas Huth wrote: We're struggling quite badly with our CI minutes on the shared gitlab runners, so we urgently need to think of ways to cut down our supported build and target environments. qemu-system-i386 and qemu-system-arm

Re: [PATCH v3 6/6] hw/cxl: Add clear poison mailbox command support.

On Thu, 2 Mar 2023 17:05:22 -0800 Ira Weiny wrote: > Jonathan Cameron wrote: > > Current implementation is very simple so many of the corner > > cases do not exist (e.g. fragmenting larger poison list entries) > > > > Signed-off-by: Jonathan Cameron > > --- > > v2: > > - Endian fix > > --- > >

Re: [PATCH 3/6] Add the aehd-apic device type.

Hi Haitao, On 3/3/23 03:26, Haitao Shan wrote: The aehd-apic device type represents the AEHD in kernel APIC. The irqchips should be always in kernel when AEHD is used. Signed-off-by: Haitao Shan --- MAINTAINERS | 2 + hw/i386/aehd/apic.c | 204 +++

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