On Sun, Feb 26, 2023 at 01:58:10AM +, Damien Zammit wrote:
> Currently, the one-shot (mode 1) PIT expires far too quickly,
> due to the output being set under the wrong logic.
> This change fixes the one-shot PIT mode to behave similarly to mode 0.
>
> TESTED: using the one-shot PIT mode to ca
Hi Michael,
Thanks for reviewing this on a weekend!
On 26/2/23 19:51, Michael S. Tsirkin wrote:
> On Sun, Feb 26, 2023 at 01:58:10AM +, Damien Zammit wrote:
>> case 0:
>> -out = (d >= s->count);
>> -break;
>
>
> I think you need something like
> /* FALLTHRU */
> he
On Sun, Feb 26, 2023 at 1:18 AM Damien Zammit wrote:
>
> Hi Michael,
>
> Thanks for reviewing this on a weekend!
>
> On 26/2/23 19:51, Michael S. Tsirkin wrote:
> > On Sun, Feb 26, 2023 at 01:58:10AM +, Damien Zammit wrote:
> >> case 0:
> >> -out = (d >= s->count);
> >> -
On Sun, 26 Feb 2023, Max Filippov wrote:
On Sun, Feb 26, 2023 at 1:18 AM Damien Zammit wrote:
Hi Michael,
Thanks for reviewing this on a weekend!
On 26/2/23 19:51, Michael S. Tsirkin wrote:
On Sun, Feb 26, 2023 at 01:58:10AM +, Damien Zammit wrote:
case 0:
-out = (d >= s-
On Sat, Feb 25, 2023 at 1:49 PM Philippe Mathieu-Daudé
wrote:
> All series reviewed.
>
> Since v5:
> - reword one commit description (Thomas)
> - drop CONFIG_SOFTMMU, unify softmmu_ss (Richard)
>
> Since v4:
> - more unused headers removed
> - KISS, use a bit of #ifdef'ry to avoid a stub file
>
>
On 2023/2/25 17:14, Richard Henderson wrote:
Translators are no longer required to free tcg temporaries,
therefore there's no need to record temps for later freeing.
Replace the few uses with tcg_temp_new_i64.
Signed-off-by: Richard Henderson
How about the temp_new?
Regards,
Weiwei Li
-
On 2023/2/25 17:14, Richard Henderson wrote:
Translators are no longer required to free tcg temporaries,
therefore there's no need to record temps for later freeing.
Replace the few uses with tcg_temp_new.
Signed-off-by: Richard Henderson
Oh. It's here.
Reviewed-by: Weiwei Li
Weiwei Li
On 2023/2/25 17:14, Richard Henderson wrote:
Translators are no longer required to free tcg temporaries,
therefore there's no need to record temps for later freeing.
Replace the few uses with tcg_temp_new_i64.
Signed-off-by: Richard Henderson
Reviewed-by: Weiwei Li
Weiwei Li
---
target/
On Sun, Feb 26, 2023 at 01:11:19PM +0100, BALATON Zoltan wrote:
> On Sun, 26 Feb 2023, Max Filippov wrote:
> > On Sun, Feb 26, 2023 at 1:18 AM Damien Zammit wrote:
> > >
> > > Hi Michael,
> > >
> > > Thanks for reviewing this on a weekend!
> > >
> > > On 26/2/23 19:51, Michael S. Tsirkin wrote:
On 2023/2/25 17:14, Richard Henderson wrote:
Translators are no longer required to free tcg temporaries.
Signed-off-by: Richard Henderson
Reviewed-by: Weiwei Li
Weiwei Li
---
target/riscv/translate.c | 7 ---
target/riscv/insn_trans/trans_rvb.c.inc| 24 --
Hi
On Fri, Feb 17, 2023 at 9:08 PM Dorinda Bassey wrote:
>
> This commit adds a new audiodev backend to allow QEMU to use Pipewire as
> both an audio sink and source. This backend is available on most systems
>
> Add Pipewire entry points for QEMU Pipewire audio backend
> Add wrappers for QEMU Pi
On 23/02/2023 23:16, Alex Williamson wrote:
External email: Use caution opening links or attachments
On Thu, 23 Feb 2023 17:25:12 +0200
Avihai Horon wrote:
On 22/02/2023 22:58, Alex Williamson wrote:
External email: Use caution opening links or attachments
On Wed, 22 Feb 2023 19:48:58 +
On 23/02/2023 22:54, Jason Gunthorpe wrote:
On Thu, Feb 23, 2023 at 01:16:40PM -0700, Alex Williamson wrote:
On Thu, 23 Feb 2023 15:30:28 -0400
Jason Gunthorpe wrote:
On Thu, Feb 23, 2023 at 12:27:23PM -0700, Alex Williamson wrote:
So again, I think I'm just looking for a better comment th
On 24/02/2023 21:26, Joao Martins wrote:
External email: Use caution opening links or attachments
On 23/02/2023 14:56, Avihai Horon wrote:
On 22/02/2023 22:55, Alex Williamson wrote:
There are various errors running this through the CI on gitlab.
This one seems bogus but needs to be resolv
Commit 752614cab8e6 ("target/riscv: rvv: Add tail agnostic for vector
load / store instructions") added code to set the tail elements to 1 in
the end of vext_ldst_stride(), vext_ldst_us(), vext_ldst_index() and
vext_ldff(). Aside from a env->vl versus an evl value being used in the
first loop, the
This file has several uses of env_archcpu() that are used solely to read
cfg->vlen. Use the new riscv_cpu_cfg() inline instead.
Suggested-by: Weiwei Li
Signed-off-by: Daniel Henrique Barboza
---
target/riscv/vector_helper.c | 20 ++--
1 file changed, 10 insertions(+), 10 deletio
Based-on: 20230222185205.355361-2-dbarb...@ventanamicro.com
("[PATCH v7 01/10] target/riscv: introduce riscv_cpu_cfg()")
Hi,
This is a re-send of patch 1, which is already reviewed, with a
follow-up that uses riscv_cpu_cfg() in the remaining of the file. This
was suggested by Weiwei Li in the "[P
On 2/25/23 03:47, liweiwei wrote:
On 2023/2/25 01:45, Daniel Henrique Barboza wrote:
Hi,
These cleanups were suggested by LIU Zhiwei during the review of the
RISCV_FEATURE_* cleanups, currently on version 7 [1].
These are dependent on the patch "[PATCH v7 01/10] target/riscv: introduce
ris
Thanks for the reviews!
I decided to take this patch (acks included) and send it in together with
a cleanup of the env_archcpu() usages in vector_helper.c:
https://lists.gnu.org/archive/html/qemu-devel/2023-02/msg07566.html
Thanks,
Daniel
On 2/21/23 15:45, Daniel Henrique Barboza wrote:
On 26/2/23 18:05, Daniel Henrique Barboza wrote:
Commit 752614cab8e6 ("target/riscv: rvv: Add tail agnostic for vector
load / store instructions") added code to set the tail elements to 1 in
the end of vext_ldst_stride(), vext_ldst_us(), vext_ldst_index() and
vext_ldff(). Aside from a env->vl ver
On 26/2/23 18:05, Daniel Henrique Barboza wrote:
This file has several uses of env_archcpu() that are used solely to read
cfg->vlen. Use the new riscv_cpu_cfg() inline instead.
Suggested-by: Weiwei Li
Signed-off-by: Daniel Henrique Barboza
---
target/riscv/vector_helper.c | 20 ++
On Fri, 24 Feb 2023 at 21:23, Philippe Mathieu-Daudé wrote:
>
> On 24/2/23 20:52, Alex Bennée wrote:
> >
> > Peter Maydell writes:
> >
> >> On Thu, 23 Feb 2023 at 15:57, Alex Bennée wrote:
> >>>
> >>> The following changes since commit
> >>> 79b677d658d3d35e1e776826ac4abb28cdce69b8:
> >>>
> >>>
Am 24. Februar 2023 16:22:48 UTC schrieb "Michael S. Tsirkin" :
>On Thu, Jan 26, 2023 at 10:17:30PM +0100, Bernhard Beschow wrote:
>> This series resolves the global "isabus" variable and is basically a v2 of
>> [1].
>> Note that the majority of the work consists of fixing ISA API calls in PIIX
On 30/1/23 18:00, Bernhard Beschow wrote:
Am 26. Januar 2023 21:17:36 UTC schrieb Bernhard Beschow :
These legacy ISA IRQs allow the PIIX IDE functions to be wired up in
their south bridges and the VIA IDE functions to disuse
PCI_INTERRUPT_LINE as outlined in https://lists.nongnu.org/archive/h
On 26/2/23 13:39, Marc-André Lureau wrote:
Philippe Mathieu-Daudé (5):
dump: Replace tswapN() -> cpu_to_dumpN()
dump: Replace TARGET_PAGE_SIZE -> qemu_target_page_size()
dump: Clean included headers
dump: Simplify compiling win_dump.o by introducing
win_d
On 16/2/23 15:40, BALATON Zoltan wrote:
Add simple implementation for two raster operations that are used by
AmigaOS which fixes graphics problems in some progtams using these.
Typo "programs".
Signed-off-by: BALATON Zoltan
---
For definitions of these see:
https://learn.microsoft.com/en-us/
CMD_TLBI_S2_IPA: As S1+S2 is not enabled, for now this can be the
same as CMD_TLBI_NH_VAA.
CMD_TLBI_S12_VMALL: Added new function to invalidate TLB by VMID.
For stage-1 only commands, add a check to to throw CERROR_ILL if used
when stage-1 is not supported.
Signed-off-by: Mostafa Saleh
---
Chan
In preparation for adding stage-2 support.
Add IDR0 fields related to stage-2.
VMID16: 16-bit VMID supported.
S2P: Stage-2 translation supported.
They are described in 6.3.1 SMMU_IDR0.
No functional change intended.
Reviewed-by: Richard Henderson
Reviewed-by: Eric Auger
Signed-off-by: Mostafa
Allow TLB to be tagged with VMID.
If stage-1 is only supported, VMID is set to -1 and ignored from STE
and CMD_TLBI_NH* cmds.
Update smmu_iotlb_insert trace event to have vmid.
Signed-off-by: Mostafa Saleh
---
Changes in v2:
-Fix TLB aliasing issue from missing check in smmu_iotlb_key_equal.
-A
OAS used to be hardcoded to 44 bits, however according to SMMU manual
6.3.6 SMMU_IDR5, OAS must match the system physical address size, so
we read it from CPU PARANGE.
Remove PA_MAX and pa_range as they were not used.
Add SMMUv3State as an argument to decode_cd, so it can read the SMMU
OAS.
As C
Right now, either stage-1 or stage-2 are supported, this simplifies
how we can deal with TLBs.
This patch makes TLB lookup work if stage-2 is enabled instead of
stage-1.
TLB lookup is done before a PTW, if a valid entry is found we won't
do the PTW.
To be able to do TLB lookup, we need the correct
In preparation for adding stage-2 support, rename smmu_ptw_64 to
smmu_ptw_64_s1 and refactor some of the code so it can be reused in
stage-2 page table walk.
Remove AA64 check from PTW as decode_cd already ensures that AA64 is
used, otherwise it faults with C_BAD_CD.
A stage member is added to SM
This patch series adds stage-2 translation support for SMMUv3. It is
controlled by a new system property “arm-smmuv3.stage”.
- When set to “1”: Stage-1 only would be advertised and supported (default
behaviour)
- When set to “2”: Stage-2 only would be advertised and supported.
- Value “all” is rese
As everything is in place, we can use a new system property to
advertise which stage is supported and remove bad_ste from STE
stage2 config.
The property added arm-smmuv3.stage can have 3 values:
- "1": Stage-1 only is advertised.
- "2": Stage-2 only is advertised.
- "all": Stage-1 + Stage-2 are s
In smmuv3_notify_iova, read the granule based on translation stage
and use VMID if valid value is sent.
Signed-off-by: Mostafa Saleh
---
hw/arm/smmuv3.c | 39 ++-
hw/arm/trace-events | 2 +-
2 files changed, 27 insertions(+), 14 deletions(-)
diff --git a
Parse stage-2 configuration from STE and populate it in SMMUS2Cfg.
Validity of these value are checked when possible.
Only AA64 tables are supported and STT is not supported.
According to SMMUv3 user manual "5.2 Stream Table Entry": All fields
with an S2 prefix (with the exception of S2VMID) are
In preparation for adding stage-2 support, add a S2 config
struct(SMMUS2Cfg), composed of the following fields and embedded in
the main SMMUTransCfg:
-tsz: Input range
-sl0: start level of translation
-affd: AF fault disable
-granule_sz: Granule page shift
-vmid: VMID
-vttb: PA of translation
In preparation for adding stage-2 support, add Stage-2 PTW code.
Only Aarch64 format is supported as stage-1.
Nesting stage-1 and stage-2 is not supported right now.
HTTU is not supported, SW is expected to maintain the Access flag.
This is described in the SMMUv3 manual "5.2. Stream Table Entry"
According to the PegasosII schematics the PCI interrupt lines are
connected to both the gpp pins of the Mv64361 north bridge and the
PINT pins of the VT8231 south bridge so guests can get interrupts from
either of these. So far we only had the MV64361 connections which
worked for on board devices b
Add simple implementation for two raster operations that are used by
AmigaOS which fixes graphics problems in some programs using these.
Signed-off-by: BALATON Zoltan
Reported-by: Rene Engel
Tested-by: Rene Engel
Reviewed-by: Daniel Henrique Barboza
---
These are documented for example at:
htt
Pixman may return false if it does not have a suitable implementation.
Add fallbacks to handle such cases.
Signed-off-by: BALATON Zoltan
Reported-by: Rene Engel
Tested-by: Rene Engel
---
hw/display/sm501.c | 75 --
1 file changed, 52 insertions(+), 2
These can be shared with other AC97 implementations.
Signed-off-by: BALATON Zoltan
---
hw/audio/ac97.c | 43 +---
hw/audio/ac97.h | 65 +
2 files changed, 66 insertions(+), 42 deletions(-)
create mode 100644 hw/audio/ac
Add a property to allow disabling pixman and always use the fallbacks
for different operations which is useful for testing different drawing
methods or debugging pixman related issues.
Signed-off-by: BALATON Zoltan
---
hw/display/sm501.c | 18 +++---
1 file changed, 15 insertions(+),
Add basic implementation of the AC'97 sound part used in VIA south
bridge chips. Not all features of the device is emulated, only one
playback channel is supported for now but this is enough to get sound
output from some guests using this device on pegasos2.
Signed-off-by: BALATON Zoltan
Tested-b
From: Bernhard Beschow
The real VIA south bridges implement a PCI IRQ router which is configured
by the BIOS or the OS. In order to respect these configurations, QEMU
needs to implement it as well.
Note: The implementation was taken from piix4_set_irq() in hw/isa/piix4.
Signed-off-by: Bernhard
Hello,
This is marked v3 to avoid confusion with previously separate patches
that already had v2, even if the series had no v2 yet.
This series now includes all patches needed to get AmigaOS 4.1 run
well on pegasos2 and add audio output to this board. It has 3 parts:
patches 1-3 improve hw/displa
From: Bernhard Beschow
According to the PCI specification, PCI_INTERRUPT_LINE shall have no
effect on hardware operations. Now that the VIA south bridges implement
the internal PCI interrupt router let's be more conformant to the PCI
specification.
Signed-off-by: Bernhard Beschow
Signed-off-by:
On Sun, 26 Feb 2023, Philippe Mathieu-Daudé wrote:
On 16/2/23 15:40, BALATON Zoltan wrote:
Add simple implementation for two raster operations that are used by
AmigaOS which fixes graphics problems in some progtams using these.
Typo "programs".
Fixed in v3 (was just in time for that :-) ).
On Sat, 25 Feb 2023, Philippe Mathieu-Daudé wrote:
On 21/2/23 19:44, BALATON Zoltan wrote:
These can be shared with other AC97 implementations.
Signed-off-by: BALATON Zoltan
---
hw/audio/ac97.c | 43 +---
hw/audio/ac97.h | 65 +
On 25/1/22 20:48, BALATON Zoltan wrote:
These can be shared with other AC97 implementations.
Signed-off-by: BALATON Zoltan
---
hw/audio/ac97.c | 43 +---
hw/audio/ac97.h | 65 +
2 files changed, 66 insertions(+), 42
On Sat, 25 Feb 2023, Philippe Mathieu-Daudé wrote:
On 21/2/23 19:44, BALATON Zoltan wrote:
According to the PegasosII schematics the PCI interrupt lines are
connected to both the gpp pins of the Mv64361 north bridge and the
PINT pins of the VT8231 south bridge so guests can get interrupts from
e
On 25/2/23 19:11, BALATON Zoltan wrote:
From: Bernhard Beschow
The real VIA south bridges implement a PCI IRQ router which is configured
by the BIOS or the OS. In order to respect these configurations, QEMU
needs to implement it as well.
Note: The implementation was taken from piix4_set_irq()
On Sun, 26 Feb 2023, Philippe Mathieu-Daudé wrote:
On 25/2/23 19:11, BALATON Zoltan wrote:
From: Bernhard Beschow
The real VIA south bridges implement a PCI IRQ router which is configured
by the BIOS or the OS. In order to respect these configurations, QEMU
needs to implement it as well.
Note
Am 16. Februar 2023 20:27:32 UTC schrieb BALATON Zoltan :
>According to the PegasosII schematics the PCI interrupt lines are
>connected to both the gpp pins of the Mv64361 north bridge and the
>PINT pins of the VT8231 south bridge so guests can get interrupts from
>either of these. So far we onl
Am 25. Februar 2023 18:11:49 UTC schrieb BALATON Zoltan :
>From: Bernhard Beschow
>
>The real VIA south bridges implement a PCI IRQ router which is configured
>by the BIOS or the OS. In order to respect these configurations, QEMU
>needs to implement it as well.
>
>Note: The implementation was t
Am 26. Februar 2023 22:27:50 UTC schrieb "Philippe Mathieu-Daudé"
:
>On 25/2/23 19:11, BALATON Zoltan wrote:
>> From: Bernhard Beschow
>>
>> The real VIA south bridges implement a PCI IRQ router which is configured
>> by the BIOS or the OS. In order to respect these configurations, QEMU
>> ne
On Sun, 26 Feb 2023, Bernhard Beschow wrote:
Am 25. Februar 2023 18:11:49 UTC schrieb BALATON Zoltan :
From: Bernhard Beschow
The real VIA south bridges implement a PCI IRQ router which is configured
by the BIOS or the OS. In order to respect these configurations, QEMU
needs to implement it as
On Sun, 26 Feb 2023, Bernhard Beschow wrote:
Am 26. Februar 2023 22:27:50 UTC schrieb "Philippe Mathieu-Daudé"
:
On 25/2/23 19:11, BALATON Zoltan wrote:
From: Bernhard Beschow
The real VIA south bridges implement a PCI IRQ router which is configured
by the BIOS or the OS. In order to respect
On Sun, 26 Feb 2023, Bernhard Beschow wrote:
Am 16. Februar 2023 20:27:32 UTC schrieb BALATON Zoltan :
According to the PegasosII schematics the PCI interrupt lines are
connected to both the gpp pins of the Mv64361 north bridge and the
PINT pins of the VT8231 south bridge so guests can get inter
On Sun, 26 Feb 2023, Bernhard Beschow wrote:
Am 26. Februar 2023 22:27:50 UTC schrieb "Philippe Mathieu-Daudé"
:
On 25/2/23 19:11, BALATON Zoltan wrote:
From: Bernhard Beschow
The real VIA south bridges implement a PCI IRQ router which is configured
by the BIOS or the OS. In order to respect
On 2023/2/27 01:05, Daniel Henrique Barboza wrote:
This file has several uses of env_archcpu() that are used solely to read
cfg->vlen. Use the new riscv_cpu_cfg() inline instead.
Suggested-by: Weiwei Li
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Weiwei Li
Weiwei Li
---
targe
> On Fri, Feb 24, 2023 at 08:23:40AM +, Yangming wrote:
> >
> > Optimize the virtio-balloon feature on the ARM platform by adding a
> variable to keep track of the current hot-plugged pc-dimm size, instead of
> traversing the virtual machine's memory modules to count the current RAM
> size d
在 2023/2/26 上午2:38, Richard Henderson 写道:
On 2/25/23 00:22, Daniel Henrique Barboza wrote:
Richard,
Not sure if I forgot or missed something but this patch breaks my
build as follows:
$ make -j
GIT ui/keycodemapdb tests/fp/berkeley-testfloat-3
tests/fp/berkeley-softfloat-3 dtc
[1
On Tue, Feb 21, 2023 at 7:32 PM Daniel Henrique Barboza
wrote:
>
>
>
> On 2/21/23 03:12, Bin Meng wrote:
> > Lanuch qemu-system-riscv64 with a given dtb for 'sifive_u' and 'virt'
> > machines, QEMU complains:
> >
> >qemu_fdt_add_subnode: Failed to create subnode /soc: FDT_ERR_EXISTS
> >
> > Th
On Sat, Feb 25, 2023 at 5:26 AM Palmer Dabbelt wrote:
>
> The OpenSBI build has been using docker:19.03.1, which appears to be old
> enough that v2 of the manifest is no longer supported. Something has
> started serving us those manifests, resulting in errors along the lines
> of
>
> $ docker
在 2023/2/25 下午5:13, Richard Henderson 写道:
Translators are no longer required to free tcg temporaries,
therefore there's no need to record temps for later freeing.
Replace the few uses with tcg_temp_new.
Signed-off-by: Richard Henderson
---
target/loongarch/translate.h | 3
在 2023/2/25 下午5:13, Richard Henderson 写道:
Translators are no longer required to free tcg temporaries.
Signed-off-by: Richard Henderson
---
target/loongarch/insn_trans/trans_arith.c.inc | 12 ---
.../loongarch/insn_trans/trans_atomic.c.inc | 3 --
target/loongarch/insn_trans/trans_b
Hi,
I'm looking to get more involved in contributing to QEMU. I noticed that
there are some issues in the tracker where a sample patch has been
contributed but never got merged, like a proposal to add multiboot2
support: https://gitlab.com/qemu-project/qemu/-/issues/389
Is another dev allowed to
Since the EDK2 had already support LoongArch, update build bios,
and update cpu type, cross-tools.
Signed-off-by: Song Gao
Message-Id: <20230208094133.2945979-1-gaos...@loongson.cn>
---
.../loongarch/{loongson3.rst => virt.rst} | 97 ---
1 file changed, 38 insertions(+), 59 d
LoongArch has enabled CONFIG_SMBIOS, but didn't enable CLI '-smbios'.
Fixes: 3efa6fa1e629 ("hw/loongarch: Add smbios support")
Acked-by: Michael S. Tsirkin
Reviewed-by: Markus Armbruster
Signed-off-by: Song Gao
Message-Id: <20230208094133.2945979-2-gaos...@loongson.cn>
---
qemu-options.hx | 2
Hi all,
On Mon, Feb 20, 2023 at 11:50 AM Daniel P. Berrangé wrote:
>
> On Sun, Feb 19, 2023 at 06:20:58PM +0200, Andrew Melnychenko wrote:
> > Added a function to check the stamp in the helper.
> > eBPF helper should have a special symbol that generates during the build.
> > QEMU checks the helpe
Hi,
On Mon, Feb 20, 2023 at 11:54 AM Daniel P. Berrangé wrote:
>
> On Sun, Feb 19, 2023 at 06:20:59PM +0200, Andrew Melnychenko wrote:
> > Helper program. Loads eBPF RSS program and maps and passes them through
> > unix socket.
> > Libvirt may launch this helper and pass eBPF fds to qemu virtio-
In the last stage of live migration or memory slot removal, the
backup bitmap needs to be synchronized when it has been enabled.
Signed-off-by: Gavin Shan
Reviewed-by: Peter Xu
Tested-by: Zhenyu Zhang
---
accel/kvm/kvm-all.c | 11 +++
include/sysemu/kvm_int.h | 1 +
2 files chang
arm64 has different capability from x86 to enable the dirty ring, which
is KVM_CAP_DIRTY_LOG_RING_ACQ_REL. Besides, arm64 also needs the backup
bitmap extension (KVM_CAP_DIRTY_LOG_RING_WITH_BITMAP) when 'kvm-arm-gicv3'
or 'arm-its-kvm' device is enabled. Here the extension is always enabled
and the
This series intends to support dirty ring for live migration for arm64. The
dirty ring use discrete buffer to track dirty pages. For arm64, the speciality
is to use backup bitmap to track dirty pages when there is no-running-vcpu
context. It's known that the backup bitmap needs to be synchronized w
The global dirty log synchronization is used when KVM and dirty ring
are enabled. There is a particularity for ARM64 where the backup
bitmap is used to track dirty pages in non-running-vcpu situations.
It means the dirty ring works with the combination of ring buffer
and backup bitmap. The dirty bi
Due to multiple capabilities associated with the dirty ring for different
architectures: KVM_CAP_DIRTY_{LOG_RING, LOG_RING_ACQ_REL} for x86 and
arm64 separately. There will be more to be done in order to support the
dirty ring for arm64.
Lets add helper kvm_dirty_ring_init() to enable the dirty ri
Since commit ee6d3dd4ed48 ("driver core: make kobj_type constant.")
the driver core allows the usage of const struct kobj_type.
Take advantage of this to constify the structure definition to prevent
modification at runtime.
Signed-off-by: Thomas Weißschuh
---
drivers/firmware/qemu_fw_cfg.c | 2
Since all temps allocated by guest front-ends are now TEMP_TB,
and we don't recycle TEMP_TB, there's no point in requiring
that the front-ends free the temps at all. Begin by dropping
the inner-most checks that all temps have been freed.
Signed-off-by: Richard Henderson
---
include/tcg/tcg.h
Translators are no longer required to free tcg temporaries.
Signed-off-by: Richard Henderson
---
target/arm/translate-neon.c | 131 +---
1 file changed, 1 insertion(+), 130 deletions(-)
diff --git a/target/arm/translate-neon.c b/target/arm/translate-neon.c
index
Translators are no longer required to free tcg temporaries.
Signed-off-by: Richard Henderson
---
target/hexagon/gen_tcg_funcs.py | 79 +
1 file changed, 1 insertion(+), 78 deletions(-)
diff --git a/target/hexagon/gen_tcg_funcs.py b/target/hexagon/gen_tcg_funcs.py
Translators are no longer required to free tcg temporaries.
Signed-off-by: Richard Henderson
---
target/arm/translate-a64.c | 468 +
1 file changed, 11 insertions(+), 457 deletions(-)
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index
This is now a simple wrapper for tcg_temp_new_i64.
Signed-off-by: Richard Henderson
---
target/arm/translate-a64.h | 1 -
target/arm/translate-a64.c | 45 +-
target/arm/translate-sve.c | 20 -
3 files changed, 30 insertions(+), 36 deletions(-)
Translators are no longer required to free tcg temporaries.
Signed-off-by: Richard Henderson
---
target/arm/translate-m-nocp.c | 20
1 file changed, 20 deletions(-)
diff --git a/target/arm/translate-m-nocp.c b/target/arm/translate-m-nocp.c
index 5df7d46120..9a89aab785 10064
Translators are no longer required to free tcg temporaries,
therefore there's no need to record for later freeing.
Signed-off-by: Richard Henderson
---
target/avr/translate.c | 19 ---
1 file changed, 19 deletions(-)
diff --git a/target/avr/translate.c b/target/avr/translate.c
i
Translators are no longer required to free tcg temporaries.
Remove the g1 and g2 members of DisasCompare, as they were
used to track which temps needed to be freed.
Signed-off-by: Richard Henderson
---
target/m68k/translate.c | 40
1 file changed, 40 dele
Translators are no longer required to free tcg temporaries,
therefore there's no need to record temps for later freeing.
Replace the few uses with tcg_temp_new.
Reviewed-by: Song Gao
Signed-off-by: Richard Henderson
---
target/loongarch/translate.h | 3 ---
target/loongarch/tr
Finish removing tcg temp free accounting interfaces.
Signed-off-by: Richard Henderson
---
include/exec/translator.h | 2 --
accel/tcg/translator.c | 4
target/alpha/translate.c | 1 -
target/arm/translate-a64.c | 2 --
target/arm/translate.c | 1 -
target/ppc/translate.c | 2
Translators are no longer required to free tcg temporaries.
Signed-off-by: Richard Henderson
---
target/arm/translate-mve.c | 52 --
1 file changed, 52 deletions(-)
diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c
index db7ea3f603..798b4fd
This field was only used to avoid freeing globals.
Since we no longer free any temps, this is dead.
Signed-off-by: Richard Henderson
---
target/arm/translate.h | 1 -
target/arm/translate.c | 5 -
2 files changed, 6 deletions(-)
diff --git a/target/arm/translate.h b/target/arm/translate.h
i
Translators are no longer required to free tcg temporaries.
Signed-off-by: Richard Henderson
---
target/mips/tcg/mips16e_translate.c.inc | 6 --
1 file changed, 6 deletions(-)
diff --git a/target/mips/tcg/mips16e_translate.c.inc
b/target/mips/tcg/mips16e_translate.c.inc
index 918b15d55c..6
Translators are no longer required to free tcg temporaries.
Signed-off-by: Richard Henderson
---
target/alpha/translate.c | 70
1 file changed, 70 deletions(-)
diff --git a/target/alpha/translate.c b/target/alpha/translate.c
index a0afdbb465..9d25e21164
Translators are no longer required to free tcg temporaries.
Signed-off-by: Richard Henderson
---
target/mips/tcg/msa_translate.c | 9 -
1 file changed, 9 deletions(-)
diff --git a/target/mips/tcg/msa_translate.c b/target/mips/tcg/msa_translate.c
index 1bcdbb1121..220cd3b048 100644
--- a
Translators are no longer required to free tcg temporaries,
therefore there's no need to record temps for later freeing.
Signed-off-by: Richard Henderson
---
target/m68k/translate.c | 55 ++---
1 file changed, 13 insertions(+), 42 deletions(-)
diff --git a/ta
Translators are no longer required to free tcg temporaries,
therefore there's no need to record temps for later freeing.
Signed-off-by: Richard Henderson
---
target/arm/translate.h | 3 ---
target/arm/translate-a64.c | 25 +
2 files changed, 1 insertion(+), 27 deleti
Only the use within cpu_reg requires a writable temp,
so inline new_tmp_a64_zero there. All other uses are
fine with a constant temp, so use tcg_constant_i64(0).
Signed-off-by: Richard Henderson
---
target/arm/translate-a64.h | 1 -
target/arm/translate-a64.c | 41 +
Translators are no longer required to free tcg temporaries.
Reviewed-by: Song Gao
Signed-off-by: Richard Henderson
---
target/loongarch/insn_trans/trans_arith.c.inc | 12 ---
.../loongarch/insn_trans/trans_atomic.c.inc | 3 --
target/loongarch/insn_trans/trans_bit.c.inc | 12 ---
t
Translators are no longer required to free tcg temporaries.
Signed-off-by: Richard Henderson
---
target/cris/translate.c | 70 -
target/cris/translate_v10.c.inc | 41 ---
2 files changed, 111 deletions(-)
diff --git a/target/cris/translate
Translators are no longer required to free tcg temporaries.
Signed-off-by: Richard Henderson
---
target/m68k/translate.c | 181
1 file changed, 181 deletions(-)
diff --git a/target/m68k/translate.c b/target/m68k/translate.c
index d7237b6a99..3055d2d246 1
Translators are no longer required to free tcg temporaries.
Signed-off-by: Richard Henderson
---
target/arm/translate.h | 1 -
target/arm/translate-a64.c | 17 -
target/arm/translate.c | 9 -
3 files changed, 4 insertions(+), 23 deletions(-)
diff --git a/target
1 - 100 of 174 matches
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