Re: [PATCH v2 6/7] CI: Stop building docs on centos8

Daniel P. Berrangé writes: > On Tue, Feb 14, 2023 at 09:52:44PM +0100, Paolo Bonzini wrote: >> Il mar 14 feb 2023, 18:26 Kevin Wolf ha scritto: >> >> > Am 14.02.2023 um 15:03 hat Paolo Bonzini geschrieben: >> > > In the case of Python the issue is not the interpreter per se, though >> > > there

Re: Does the page boundary check still necessary?

On Wed, Feb 15, 2023 at 07:27:19AM -1000, Richard Henderson wrote: > Date: Wed, 15 Feb 2023 07:27:19 -1000 > From: Richard Henderson > To: Kenneth Lee , qemu-devel@nongnu.org > Subject: Re: Does the page boundary check still necessary? > User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/

答复: [PATCH] usb/dev-wacom: fix OOB write in usb_mouse_poll()

Qemu cmd and guest poc /home/test/qemu/qemu-7.1.0/build/qemu-system-x86_64 -kernel /home/test/kernel/linux-5.10/arch/x86/boot/bzImage -initrd /home/test/rootfs/rootfs.cpio_root -append "root=/dev/ram rw console=tty console=ttyS0 nokaslr" -m 512M -nographic -monitor /dev/null -drive file=nul

Detecting qemu from guest on arm/hvf (apple arm)

Hello, I was wondering what the best way to detect that FreeBSD is running under qemu/hvf on Apple ARM? FreeBSD doesn't see the ACPI FADT table, so I'm wondering if keying off of something like the QEMU0002 device in ACPI is the best way? Or is there another option? Thanks for your help. --

Re: [PATCH v2 01/13] vdpa net: move iova tree creation from init to start

On 2/14/2023 11:07 AM, Eugenio Perez Martin wrote: On Tue, Feb 14, 2023 at 2:45 AM Si-Wei Liu wrote: On 2/13/2023 3:14 AM, Eugenio Perez Martin wrote: On Mon, Feb 13, 2023 at 7:51 AM Si-Wei Liu wrote: On 2/8/2023 1:42 AM, Eugenio Pérez wrote: Only create iova_tree if and when it is ne

Re: Does the page boundary check still necessary?

On 2/15/23 15:45, Kenneth Lee wrote: Now the chained TBs have been link with tb_link_page(), the chain will be rebuilt if it is invalidate on page. So why is this check still there? Even for a guest which doesn't use paging, and therefore does not need to worry about memory maps changing, we st

Re: Does the page boundary check still necessary?

On Wed, Feb 15, 2023 at 04:26:18PM -1000, Richard Henderson wrote: > Date: Wed, 15 Feb 2023 16:26:18 -1000 > From: Richard Henderson > To: Kenneth Lee > Cc: qemu-devel@nongnu.org > Subject: Re: Does the page boundary check still necessary? > User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) G

Re: [PATCH RESEND 07/18] i386: Support modules_per_die in X86CPUTopoInfo

Hi Zhao, 在 2023/2/13 17:36, Zhao Liu 写道: From: Zhuocheng Ding Support module level in i386 cpu topology structure "X86CPUTopoInfo". Before updating APIC ID parsing rule with module level, the apicid_core_width() temporarily combines the core and module levels together. If we dont merge this

Re: [PATCH v1 RFC Zisslpcfi 6/9] target/riscv: MMU changes for back cfi's shadow stack

On 2023/2/16 7:57, Deepak Gupta wrote: `On Wed, Feb 15, 2023 at 12:43 AM LIU Zhiwei wrote: On 2023/2/9 14:24, Deepak Gupta wrote: zisslpcfi protects returns(back cfi) using shadow stack. If compiled with enabled compiler, function prologs will have `sspush ra` instruction to push return add

Re: [PATCH RESEND 10/18] i386: Update APIC ID parsing rule to support module level

在 2023/2/15 23:03, Zhao Liu 写道: On Wed, Feb 15, 2023 at 07:06:32PM +0800, wangyanan (Y) wrote: Date: Wed, 15 Feb 2023 19:06:32 +0800 From: "wangyanan (Y)" Subject: Re: [PATCH RESEND 10/18] i386: Update APIC ID parsing rule to support module level Hi Zhao, 在 2023/2/13 17:36, Zhao Liu 写道: Fr

Re: [PATCH v1 RFC Zisslpcfi 3/9] target/riscv: implements CSRs and new bits in existing CSRs in zisslpcfi

On 2/15/23 15:38, Deepak Gupta wrote: Question: I'll basically need two bits (one for forward cfi and one for backward cfi). Are they separately enabled? It may also be possible to use a single bit and then perform a runtime check. I guess I should read the spec... But I need to throw awa

Re: [PATCH v1 RFC Zisslpcfi 7/9] target/riscv: Tracking indirect branches (fcfi) using TCG

On 2023/2/16 8:02, Deepak Gupta wrote: On Wed, Feb 15, 2023 at 12:55 AM LIU Zhiwei wrote: On 2023/2/9 14:24, Deepak Gupta wrote: zisslpcfi protects forward control flow (if enabled) by enforcing all indirect call and jmp must land on a landing pad instruction `lpcll` short for landing pad a

Re: Does the page boundary check still necessary?

On 2/15/23 16:28, Kenneth Lee wrote: On Wed, Feb 15, 2023 at 04:26:18PM -1000, Richard Henderson wrote: Date: Wed, 15 Feb 2023 16:26:18 -1000 From: Richard Henderson To: Kenneth Lee Cc: qemu-devel@nongnu.org Subject: Re: Does the page boundary check still necessary? User-Agent: Mozilla/5.0 (X1

[PATCH v2 00/30] tcg: Improve atomicity support

Version 1 was back in November: https://lore.kernel.org/qemu-devel/20221118094754.242910-1-richard.hender...@linaro.org/ Prerequisites, and there were many, are now upstream. Changes are too many to mention. But at least I've fixed the clang and darwin build problems Phil reported. The main obje

[PATCH v2 06/30] accel/tcg: Reorg system mode store helpers

Instead of trying to unify all operations on uint64_t, use mmu_lookup() to perform the basic tlb hit and resolution. Create individual functions to handle access by size. Signed-off-by: Richard Henderson --- accel/tcg/cputlb.c | 408 + 1 file changed,

[PATCH v2 16/30] accel/tcg: Add aarch64 specific support in ldst_atomicity

We have code in atomic128.h noting that through GCC 8, there was no support for atomic operations on __uint128. This has been fixed in GCC 10. But we can still improve over any basic compare-and-swap loop using the ldxp/stxp instructions. Signed-off-by: Richard Henderson --- accel/tcg/ldst_ato

[PATCH v2 02/30] include/exec/memop: Add bits describing atomicity

These bits may be used to describe the precise atomicity requirements of the guest, which may then be used to constrain the methods by which it may be emulated by the host. For instance, the AArch64 LDP (32-bit) instruction changes semantics with ARMv8.4 LSE2, from MO_64 | MO_ATMAX_4 | MO_ATOM_

[PATCH v2 24/30] tcg/i386: Use full load/store helpers in user-only mode

Instead of using helper_unaligned_{ld,st}, use the full load/store helpers. This will allow the fast path to increase alignment to implement atomicity while not immediately raising an alignment exception. Signed-off-by: Richard Henderson --- tcg/i386/tcg-target.c.inc | 332 -

[PATCH v2 05/30] accel/tcg: Reorg system mode load helpers

Instead of trying to unify all operations on uint64_t, pull out mmu_lookup() to perform the basic tlb hit and resolution. Create individual functions to handle access by size. Signed-off-by: Richard Henderson --- accel/tcg/cputlb.c | 612 +++-- 1 file chan

[PATCH v2 17/30] tcg/aarch64: Detect have_lse, have_lse2 for linux

Notice when the host has additional atomic instructions. The new variables will also be used in generated code. Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target.h | 3 +++ tcg/aarch64/tcg-target.c.inc | 12 2 files changed, 15 insertions(+) diff --git a/tcg/aarch64/

[PATCH v2 22/30] tcg/i386: Introduce tcg_out_mov2

Create a helper for data movement minding register overlap. Use the more general xchg instruction, which consumes one extra byte, but simplifies the more general function. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- tcg/i386/tcg-target.c.inc | 27 +++

[PATCH v2 15/30] accel/tcg: Use have_atomic16 in ldst_atomicity.c.inc

Hosts using Intel and AMD AVX cpus are quite common. Add fast paths through ldst_atomicity using this. Signed-off-by: Richard Henderson --- accel/tcg/ldst_atomicity.c.inc | 76 +++--- 1 file changed, 60 insertions(+), 16 deletions(-) diff --git a/accel/tcg/ldst_atomi

[PATCH v2 26/30] tcg/i386: Mark Win64 call-saved vector regs as reserved

While we do not include these in tcg_target_reg_alloc_order, and therefore they ought never be allocated, it seems safer to mark them reserved as well. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- tcg/i386/tcg-target.c.inc | 13 + 1 file changed, 13 inser

[PATCH v2 07/30] accel/tcg: Honor atomicity of loads

Create ldst_atomicity.c.inc. Not required for user-only code loads, because we've ensured that the page is read-only before beginning to translate code. Signed-off-by: Richard Henderson --- accel/tcg/cputlb.c | 170 +++--- accel/tcg/user-exec.c | 26 +- accel/tcg/ldst_

[PATCH v2 28/30] tcg/i386: Support 128-bit load/store with have_atomic16

Signed-off-by: Richard Henderson --- tcg/i386/tcg-target.h | 3 +- tcg/i386/tcg-target.c.inc | 325 +++--- 2 files changed, 304 insertions(+), 24 deletions(-) diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h index 6d8a536a32..37d8e70fdc 100644 ---

[PATCH v2 09/30] tcg/tci: Use cpu_{ld,st}_mmu

Unify the softmmu and the user-only paths by using the official memory interface. Avoid double logging of memory operations to plugins by relying on the ones within the cpu_*_mmu functions. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- tcg/tcg-op.c | 9 +++- tcg/tc

[PATCH v2 04/30] accel/tcg: Introduce tlb_read_idx

Instead of playing with offsetof in various places, use MMUAccessType to index an array. This is easily defined instead of the previous dummy padding array in the union. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- include/exec/cpu-defs.h | 7 ++- include/exec/cpu

[PATCH v2 03/30] accel/tcg: Add cpu_in_serial_context

Like cpu_in_exclusive_context, but also true if there is no other cpu against which we could race. Use it in tb_flush as a direct replacement. Use it in cpu_loop_exit_atomic to ensure that there is no loop against cpu_exec_step_atomic. Signed-off-by: Richard Henderson --- accel/tcg/internal.h

[PATCH v2 08/30] accel/tcg: Honor atomicity of stores

Signed-off-by: Richard Henderson --- accel/tcg/cputlb.c | 103 +++ accel/tcg/user-exec.c | 12 +- accel/tcg/ldst_atomicity.c.inc | 491 + 3 files changed, 540 insertions(+), 66 deletions(-) diff --git a/accel/tcg/cputlb.c b/accel/tcg/cput

[PATCH v2 20/30] tcg: Introduce TCG_OPF_TYPE_MASK

Reorg TCG_OPF_64BIT and TCG_OPF_VECTOR into a two-bit field so that we can add TCG_OPF_128BIT without requiring another bit. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- include/tcg/tcg.h| 22 -- tcg/optimize.c | 15 +

[PATCH v2 23/30] tcg/i386: Introduce tcg_out_testi

Split out a helper for choosing testb vs testl. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- tcg/i386/tcg-target.c.inc | 30 ++ 1 file changed, 18 insertions(+), 12 deletions(-) diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target

[PATCH v2 30/30] tcg/i386: Honor 64-bit atomicity in 32-bit mode

Use one of the coprocessors to perform 64-bit stores. Signed-off-by: Richard Henderson --- tcg/i386/tcg-target.c.inc | 119 +- 1 file changed, 106 insertions(+), 13 deletions(-) diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc index 834978f7

[PATCH v2 01/30] include/qemu/cpuid: Introduce xgetbv_low

Replace the two uses of asm to expand xgetbv with an inline function. Since one of the two has been using the mnemonic, assume that the comment about "older versions of the assember" is obsolete, as even that is 4 years old. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --

[PATCH v2 19/30] accel/tcg: Add have_lse2 support in ldst_atomicity

Add fast paths for FEAT_LSE2, using the detection in tcg. Signed-off-by: Richard Henderson --- accel/tcg/ldst_atomicity.c.inc | 37 ++ 1 file changed, 33 insertions(+), 4 deletions(-) diff --git a/accel/tcg/ldst_atomicity.c.inc b/accel/tcg/ldst_atomicity.c.inc in

[PATCH v2 14/30] tcg/i386: Add have_atomic16

Notice when Intel or AMD have guaranteed that vmovdqa is atomic. The new variable will also be used in generated code. Signed-off-by: Richard Henderson --- include/qemu/cpuid.h | 18 ++ tcg/i386/tcg-target.h | 1 + tcg/i386/tcg-target.c.inc | 27

[PATCH v2 18/30] tcg/aarch64: Detect have_lse, have_lse2 for darwin

These features are present for Apple M1. Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target.c.inc | 28 1 file changed, 28 insertions(+) diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc index d144d1a769..1a295791b4 100644 --- a/tcg/a

[PATCH v2 12/30] tcg: Add 128-bit guest memory primitives

Signed-off-by: Richard Henderson --- accel/tcg/tcg-runtime.h| 3 + include/tcg/tcg-ldst.h | 4 + accel/tcg/cputlb.c | 392 + accel/tcg/user-exec.c | 94 ++-- tcg/tcg-op.c | 178 ++- accel/t

[PATCH v2 13/30] meson: Detect atomic128 support with optimization

There is an edge condition prior to gcc13 for which optimization is required to generate 16-byte atomic sequences. Detect this. Signed-off-by: Richard Henderson --- meson.build| 52 ++ accel/tcg/ldst_atomicity.c.inc | 38 ++

[PATCH v2 29/30] tcg/i386: Add vex_v argument to tcg_out_vex_modrm_pool

Signed-off-by: Richard Henderson --- tcg/i386/tcg-target.c.inc | 16 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc index 6fdf79020f..834978f7a6 100644 --- a/tcg/i386/tcg-target.c.inc +++ b/tcg/i386/tcg-target.c

[PATCH v2 10/30] tcg: Unify helper_{be,le}_{ld,st}*

With the current structure of cputlb.c, there is no difference between the little-endian and big-endian entry points, aside from the assert. Unify the pairs of functions. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- docs/devel/loads-stores.rst | 36 ++ inc

[PATCH v2 25/30] tcg/i386: Replace is64 with type in qemu_ld/st routines

Prepare for TCG_TYPE_I128 by not using a boolean. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- tcg/i386/tcg-target.c.inc | 54 ++- 1 file changed, 36 insertions(+), 18 deletions(-) diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386

[PATCH v2 11/30] accel/tcg: Implement helper_{ld, st}*_mmu for user-only

TCG backends may need to defer to a helper to implement the atomicity required by a given operation. Mirror the interface used in system mode. Signed-off-by: Richard Henderson --- include/tcg/tcg-ldst.h | 6 +- accel/tcg/user-exec.c | 392 - 2 files ch

[PATCH v2 27/30] tcg/i386: Examine MemOp for atomicity and alignment

No change to the ultimate load/store routines yet, so some atomicity conditions not yet honored, but plumbs the change to alignment through the adjacent functions. Signed-off-by: Richard Henderson --- tcg/i386/tcg-target.c.inc | 128 ++ 1 file changed, 101 ins

[PATCH v2 21/30] tcg: Add INDEX_op_qemu_{ld,st}_i128

Add opcodes for backend support for 128-bit memory operations. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- docs/devel/tcg-ops.rst | 11 +++--- include/tcg/tcg-opc.h| 8 + tcg/aarch64/tcg-target.h | 2 ++ tcg/arm/tcg-target.h | 2 ++

[PATCH v1 16/19] target/arm: Relax ordered/atomic alignment checks for LSE2

FEAT_LSE2 only requires that atomic operations not cross a 16-byte boundary. Ordered operations may be completely unaligned if SCTLR.nAA is set. Because this alignment check is so special, do it by hand. Make sure not to keep TCG temps live across the branch. Signed-off-by: Richard Henderson --

[PATCH v1 08/19] target/arm: Add atom_data to DisasContext

Use this to record the default atomicity of memory operations. Set it to MO_ATOM_WITHIN16 if FEAT_LSE2 applies. Signed-off-by: Richard Henderson --- target/arm/translate.h | 14 +++--- target/arm/translate-a64.c | 4 target/arm/translate.c | 1 + 3 files changed, 16 insert

[PATCH v1 07/19] target/arm: Add feature test for FEAT_LSE2

Signed-off-by: Richard Henderson --- target/arm/cpu.h | 5 + 1 file changed, 5 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 7bc97fece9..2108caf753 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -4049,6 +4049,11 @@ static inline bool isar_feature_aa64_st(const

[PATCH v1 02/19] target/arm: Use tcg_gen_qemu_ld_i128 for LDXP

While we don't require 16-byte atomicity here, using a single larger load simplifies the code, and makes it a closer match to STXP. Signed-off-by: Richard Henderson --- target/arm/translate-a64.c | 33 +++-- 1 file changed, 15 insertions(+), 18 deletions(-) diff --gi

[PATCH v1 04/19] target/arm: Use tcg_gen_qemu_st_i128 for STZG, STZ2G

This fixes a bug in that these two insns should have been using atomic 16-byte stores, since MTE is ARMv8.5 and LSE2 is mandatory from ARMv8.4. Signed-off-by: Richard Henderson --- target/arm/translate-a64.c | 18 +++--- tests/tcg/aarch64/mte-7.c | 3 +-- 2 files changed, 12 insert

[PATCH v1 15/19] target/arm: Add SCTLR.nAA to TBFLAG_A64

Signed-off-by: Richard Henderson --- target/arm/cpu.h | 3 ++- target/arm/translate.h | 2 ++ target/arm/helper.c| 6 ++ target/arm/translate-a64.c | 1 + 4 files changed, 11 insertions(+), 1 deletion(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 2108caf753.

[PATCH v1 09/19] target/arm: Load/store integer pair with one tcg operation

This is required for LSE2, where the pair must be treated atomically if it does not cross a 16-byte boundary. But it simplifies the code to do this always, just use the unpaired atomicity without LSE2. Signed-off-by: Richard Henderson --- target/arm/translate-a64.c | 77

[PATCH v1 05/19] target/arm: Use tcg_gen_qemu_{ld, st}_i128 in gen_sve_{ld, st}r

Round len_align to 16 instead of 8, handling an odd 8-byte as part of the tail. Use MO_ATOM_NONE to indicate that all of these memory ops have only byte atomicity. Signed-off-by: Richard Henderson --- target/arm/translate-sve.c | 107 - 1 file changed, 81 ins

[PATCH v1 03/19] target/arm: Use tcg_gen_qemu_{st, ld}_i128 for do_fp_{st, ld}

While we don't require 16-byte atomicity here, using a single larger operation simplifies the code. Signed-off-by: Richard Henderson --- target/arm/translate-a64.c | 38 ++ 1 file changed, 14 insertions(+), 24 deletions(-) diff --git a/target/arm/translate-a6

[PATCH v1 13/19] target/arm: Pass single_memop to gen_mte_checkN

Pass the individual memop to gen_mte_checkN. For the moment, do nothing with it. Signed-off-by: Richard Henderson --- target/arm/translate-a64.h | 2 +- target/arm/translate-a64.c | 26 +++--- target/arm/translate-sve.c | 4 ++-- 3 files changed, 18 insertions(+), 14 deleti

[PATCH v1 14/19] target/arm: Check alignment in helper_mte_check

Fixes a bug in that with SCTLR.A set, we should raise any alignment fault before raising any MTE check fault. Signed-off-by: Richard Henderson --- target/arm/internals.h | 3 ++- target/arm/mte_helper.c| 18 ++ target/arm/translate-a64.c | 2 ++ 3 files changed, 22 inse

[PATCH v1 11/19] target/arm: Hoist finalize_memop out of do_fp_{ld, st}

We are going to need the complete memop beforehand, so let's not compute it twice. Signed-off-by: Richard Henderson --- target/arm/translate-a64.c | 42 +- 1 file changed, 19 insertions(+), 23 deletions(-) diff --git a/target/arm/translate-a64.c b/target/arm/

[PATCH v1 18/19] test/tcg/multiarch: Adjust sigbus.c

With -cpu max and FEAT_LSE2, the __aarch64__ section will only raise an alignment exception when the load crosses a 16-byte boundary. Signed-off-by: Richard Henderson --- tests/tcg/multiarch/sigbus.c | 13 + 1 file changed, 9 insertions(+), 4 deletions(-) diff --git a/tests/tcg/mult

[PATCH v1 19/19] target/arm: Enable FEAT_LSE2 for -cpu max

Signed-off-by: Richard Henderson --- docs/system/arm/emulation.rst | 1 + target/arm/cpu64.c| 1 + 2 files changed, 2 insertions(+) diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst index 2062d71261..a97e05e746 100644 --- a/docs/system/arm/emulation.rst +++ b

[PATCH v1 00/19] target/arm: Implement FEAT_LSE2

Based-on: 20230216025739.1211680-1-richard.hender...@linaro.org ("[PATCH v2 00/30] tcg: Improve atomicity support") Testing has not been extensive, but it does boot and run stuff. Suggestions for actually testing atomicity solicited. I would imagine it would have to involve -semihosting... r~

[PATCH v1 06/19] target/arm: Sink gen_mte_check1 into load/store_exclusive

No need to duplicate this check across multiple call sites. Signed-off-by: Richard Henderson --- target/arm/translate-a64.c | 44 ++ 1 file changed, 21 insertions(+), 23 deletions(-) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index b

[PATCH v1 12/19] target/arm: Pass memop to gen_mte_check1*

Pass the completed memop to gen_mte_check1_mmuidx. For the moment, do nothing more than extract the size. Signed-off-by: Richard Henderson --- target/arm/translate-a64.h | 2 +- target/arm/translate-a64.c | 80 -- target/arm/translate-sve.c | 7 ++-- 3 files

[PATCH v1 10/19] target/arm: Hoist finalize_memop out of do_gpr_{ld, st}

We are going to need the complete memop beforehand, so let's not compute it twice. Signed-off-by: Richard Henderson --- target/arm/translate-a64.c | 61 ++ 1 file changed, 35 insertions(+), 26 deletions(-) diff --git a/target/arm/translate-a64.c b/target/arm/

[PATCH v1 17/19] target/arm: Move mte check for store-exclusive

Push the mte check behind the exclusive_addr check. Document the several ways that we are still out of spec with this implementation. Signed-off-by: Richard Henderson --- target/arm/translate-a64.c | 42 -- 1 file changed, 36 insertions(+), 6 deletions(-) dif

[PATCH v1 01/19] target/arm: Make cpu_exclusive_high hold the high bits

We currently treat cpu_exclusive_high as containing the second word of LDXP, even though that word is not "high" in big-endian mode. Swap things around so that it is. Signed-off-by: Richard Henderson --- target/arm/translate-a64.c | 54 -- 1 file changed, 29

Re: [PATCH] Adding ability to change disassembler syntax in TCG plugins

ping patchew link: https://patchew.org/QEMU/7d17f0cbb5ed4c90bbadd39924290...@yadro.com/ 10.02.2023 18:24, Mikhail Tyutin wrote: This patch adds new function qemu_plugin_insn_disas_with_syntax() that allows TCG plugins to get disassembler string with non-default syntax if it wants to. Signed-o

Re: [PATCH v1 RFC Zisslpcfi 1/9] target/riscv: adding zimops and zisslpcfi extension to RISCV cpu config

On 2/15/23 15:46, LIU Zhiwei wrote: We can rearrange the patch set as follows: 1. Implement the zimop extension. 2. Implement the forward cfi only for system mode. 3. Implement the backward cfi only for system mode. 4. Carefully make the forward cfi can work on user mode. 5. Carefully make t

Re: [PATCH v2] memory: Optimize replay of guest mapping

On Wed, Feb 15, 2023 at 10:46 PM Peter Xu wrote: > > On Wed, Feb 15, 2023 at 02:52:38PM +0800, Zhenzhong Duan wrote: > > On x86, there are two notifiers registered due to vtd-ir memory region > > splitting the whole address space. During replay of the address space > > for each notifier, the whole

Re: [PATCH] Adding ability to change disassembler syntax in TCG plugins

On 2/15/23 18:17, Mikhail Tyutin wrote: ping patchew link: https://patchew.org/QEMU/7d17f0cbb5ed4c90bbadd39924290...@yadro.com/ 10.02.2023 18:24, Mikhail Tyutin wrote: This patch adds new function qemu_plugin_insn_disas_with_syntax() that allows TCG plugins to get disassembler string with non-

Re: [PATCH RESEND 07/18] i386: Support modules_per_die in X86CPUTopoInfo

On Thu, Feb 16, 2023 at 10:34:24AM +0800, wangyanan (Y) wrote: > Date: Thu, 16 Feb 2023 10:34:24 +0800 > From: "wangyanan (Y)" > Subject: Re: [PATCH RESEND 07/18] i386: Support modules_per_die in > X86CPUTopoInfo > > Hi Zhao, > > 在 2023/2/13 17:36, Zhao Liu 写道: > > From: Zhuocheng Ding > > >

Re: [PULL 00/10] Net patches

On Wed, Feb 15, 2023 at 10:39 PM Laurent Vivier wrote: > > On 2/14/23 15:30, Peter Maydell wrote: > > On Tue, 14 Feb 2023 at 14:29, Peter Maydell > > wrote: > >> > >> On Tue, 14 Feb 2023 at 06:11, Jason Wang wrote: > >>> > >>> The following changes since commit > >>> f670b3eec7f5d1ed8c4573ef24

RE: [PATCH] Adding ability to change disassembler syntax in TCG plugins

> On 2/15/23 18:17, Mikhail Tyutin wrote: > > ping > > > > patchew link: > > https://patchew.org/QEMU/7d17f0cbb5ed4c90bbadd39924290...@yadro.com/ > > > > 10.02.2023 18:24, Mikhail Tyutin wrote: > >> This patch adds new function qemu_plugin_insn_disas_with_syntax() that > >> allows TCG > >> plugins

Re: [PATCH v10 0/9] KVM: mm: fd-based approach for supporting KVM

Hi, On Fri, Dec 02, 2022 at 02:13:38PM +0800, Chao Peng wrote: > This patch series implements KVM guest private memory for confidential > computing scenarios like Intel TDX[1]. If a TDX host accesses > TDX-protected guest memory, machine check can happen which can further > crash the running host

[PATCH v2 0/4] target/mips: misc microMIPS fixes

v2: - add reviewed-by to patch 1 & 2 - add CP0.Config7.WII for P5600 - new patch: add CP0.Config[4,5] for M14K(c) Marcin Nowakowski (4): target/mips: fix JALS32/J32 instruction handling for microMIPS target/mips: fix SWM32 handling for micromips target/mips: implement CP0.Config7.WII b

[PATCH v2 1/4] target/mips: fix JALS32/J32 instruction handling for microMIPS

microMIPS J & JAL instructions perform a jump in a 128MB region and 5 top bits of the address need to be preserved. This is different behavior compared to standard mips systems, where the jump is executed within a 256MB region. Note that microMIPS32 instruction set documentation appears to have inc

[PATCH v2 3/4] target/mips: implement CP0.Config7.WII bit support

Some pre-release 6 cores use CP0.Config7.WII bit to indicate that a disabled interrupt should wake up a sleeping CPU. Enable this bit by default for M14K(c) and P5600. There are potentially other cores that support this feature, but I do not have a complete list. Signed-off-by: Marcin Nowakowski

[PATCH v2 2/4] target/mips: fix SWM32 handling for micromips

SWM32 should store a sequence of 32-bit words from the GPRs, but it was incorrectly coded to store 16-bit words only. As a result, an LWM32 that usually follows would restore invalid register values. Fixes: 7dd547e5ab ("target/mips: Use cpu_*_mmuidx_ra instead of MMU_MODE*_SUFFIX") Signed-off-by:

[PATCH v2 4/4] target/mips: set correct CP0.Config[4, 5] values for M14K(c)

Signed-off-by: Marcin Nowakowski Suggested-by: Philippe Mathieu-Daudé --- target/mips/cpu-defs.c.inc | 10 -- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/target/mips/cpu-defs.c.inc b/target/mips/cpu-defs.c.inc index fdde04dfb9..d45f245a67 100644 --- a/target/mips/cpu-de

Re: [PATCH v1 RFC Zisslpcfi 3/9] target/riscv: implements CSRs and new bits in existing CSRs in zisslpcfi

On Wed, Feb 15, 2023 at 6:44 PM Richard Henderson wrote: > > On 2/15/23 15:38, Deepak Gupta wrote: > > Question: > > I'll basically need two bits (one for forward cfi and one for backward cfi). > > Are they separately enabled? It may also be possible to use a single bit and > then perform > a ru

[PULL V2 01/10] net: Move the code to collect available NIC models to a separate function

From: Thomas Huth The code that collects the available NIC models is not really specific to PCI anymore and will be required in the next patch, too, so let's move this into a new separate function in net.c instead. Signed-off-by: Thomas Huth Signed-off-by: Jason Wang --- hw/pci/pci.c | 2

[PULL V2 00/10] Net patches

The following changes since commit 6a50f64ca01d0a7b97f14f069762bfd88160f31e: Merge tag 'pull-request-2023-02-14' of https://gitlab.com/thuth/qemu into staging (2023-02-14 14:46:10 +) are available in the git repository at: https://github.com/jasowang/qemu.git tags/net-pull-request for

[PULL V2 02/10] net: Restore printing of the help text with "-nic help"

From: Thomas Huth Running QEMU with "-nic help" used to work in QEMU 5.2 and earlier versions (it showed the available netdev backends), but this feature got broken during some refactoring in version 6.0. Let's restore the old behavior, and while we're at it, let's also print the available NIC mo

[PULL V2 08/10] hw/net/can/xlnx-zynqmp-can: fix assertion failures in transfer_fifo()

From: Qiang Liu Check fifos before poping data from and pushing data into it. Fixes: 98e5d7a2b726 ("hw/net/can: Introduce Xilinx ZynqMP CAN controller") Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1425 Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1427 Reported-by: Qiang Li

[PULL V2 04/10] hw/net/lan9118: log [read|write]b when mode_16bit is enabled rather than abort

From: Qiang Liu This patch replaces hw_error to guest error log for [read|write]b accesses when mode_16bit is enabled. This avoids aborting qemu. Fixes: 1248f8d4cbc3 ("hw/lan9118: Add basic 16-bit mode support.") Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1433 Reported-by: Qiang Liu

[PULL V2 03/10] net: Replace "Supported NIC models" with "Available NIC models"

From: Thomas Huth Just because a NIC model is compiled into the QEMU binary does not necessary mean that it can be used with each and every machine. So let's rather talk about "available" models instead of "supported" models, just to avoid confusion. Reviewed-by: Claudio Fontana Signed-off-by:

[PULL V2 07/10] vmnet: stop recieving events when VM is stopped

From: Joelle van Dyne When the VM is stopped using the HMP command "stop", soon the handler will stop reading from the vmnet interface. This causes a flood of `VMNET_INTERFACE_PACKETS_AVAILABLE` events to arrive and puts the host CPU at 100%. We fix this by removing the event handler from vmnet w

[PULL V2 09/10] net: stream: add a new option to automatically reconnect

From: Laurent Vivier In stream mode, if the server shuts down there is currently no way to reconnect the client to a new server without removing the NIC device and the netdev backend (or to reboot). This patch introduces a reconnect option that specifies a delay to try to reconnect with the same

[PULL V2 10/10] vdpa: fix VHOST_BACKEND_F_IOTLB_ASID flag check

From: Eugenio Pérez VHOST_BACKEND_F_IOTLB_ASID is the feature bit, not the bitmask. Since the device under test also provided VHOST_BACKEND_F_IOTLB_MSG_V2 and VHOST_BACKEND_F_IOTLB_BATCH, this went unnoticed. Fixes: c1a1008685 ("vdpa: always start CVQ in SVQ mode if possible") Signed-off-by: Eug

[PULL V2 05/10] hw/net/vmxnet3: allow VMXNET3_MAX_MTU itself as a value

From: Fiona Ebner Currently, VMXNET3_MAX_MTU itself (being 9000) is not considered a valid value for the MTU, but a guest running ESXi 7.0 might try to set it and fail the assert [0]. In the Linux kernel, dev->max_mtu itself is a valid value for the MTU and for the vmxnet3 driver it's 9000, so a

[PULL V2 06/10] net: Increase L2TPv3 buffer to fit jumboframes

From: Christian Svensson Increase the allocated buffer size to fit larger packets. Given that jumboframes can commonly be up to 9000 bytes the closest suitable value seems to be 16 KiB. Tested by running qemu towards a Linux L2TPv3 endpoint and pushing jumboframe traffic through the interfaces.

Re: [PATCH] ebpf: fix compatibility with libbpf 1.0+

On Wed, Feb 15, 2023 at 4:27 AM Andrew Melnichenko wrote: > > Hi, all. > In the future, there would be eBPF RSS + the helper for Libvirt interaction. > And those patches are required for future work. Technically they are > required for the current builds with linked libbpf 1.01. > Can we apply thi

Re: [PATCH v1 RFC Zisslpcfi 6/9] target/riscv: MMU changes for back cfi's shadow stack

On Wed, Feb 15, 2023 at 6:36 PM LIU Zhiwei wrote: > > > On 2023/2/16 7:57, Deepak Gupta wrote: > > `On Wed, Feb 15, 2023 at 12:43 AM LIU Zhiwei > wrote: > > On 2023/2/9 14:24, Deepak Gupta wrote: > > zisslpcfi protects returns(back cfi) using shadow stack. If compiled with > enabled compiler, fun

[PATCH v2 01/15] linux-user/sparc: Raise SIGILL for all unhandled software traps

The linux kernel's trap tables vector all unassigned trap numbers to BAD_TRAP, which then raises SIGILL. Tested-by: Ilya Leoshkevich Reported-by: Ilya Leoshkevich Signed-off-by: Richard Henderson --- linux-user/sparc/cpu_loop.c | 8 1 file changed, 8 insertions(+) diff --git a/linux-

[PATCH v2 00/15] linux-user/sparc: Handle missing traps

Lots of missing trap codes for cpu_loop(). Changes for v2: - Fix v8plus syscall trap. - New patch to unify syscall error return via C flag. r~ Richard Henderson (15): linux-user/sparc: Raise SIGILL for all unhandled software traps linux-user/sparc: Tidy syscall trap linux-user/sparc:

Re: [PATCH v1 RFC Zisslpcfi 7/9] target/riscv: Tracking indirect branches (fcfi) using TCG

On Wed, Feb 15, 2023 at 6:44 PM LIU Zhiwei wrote: > > > On 2023/2/16 8:02, Deepak Gupta wrote: > > On Wed, Feb 15, 2023 at 12:55 AM LIU Zhiwei > > wrote: > >> > >> On 2023/2/9 14:24, Deepak Gupta wrote: > >>> zisslpcfi protects forward control flow (if enabled) by enforcing all > >>> indirect cal

Re: [PATCH] Adding ability to change disassembler syntax in TCG plugins

On 2/15/23 19:04, Mikhail Tyutin wrote: On 2/15/23 18:17, Mikhail Tyutin wrote: ping patchew link: https://patchew.org/QEMU/7d17f0cbb5ed4c90bbadd39924290...@yadro.com/ 10.02.2023 18:24, Mikhail Tyutin wrote: This patch adds new function qemu_plugin_insn_disas_with_syntax() that allows TCG pl

[PATCH v2 02/15] linux-user/sparc: Tidy syscall trap

Use TT_TRAP. For sparc32, 0x88 is the "Slowaris" system call, currently BAD_TRAP in the kernel's ttable_32.S. For sparc64, 0x110 is tl0_linux32, the sparc32 trap, now folded into the TARGET_ABI32 case via TT_TRAP. For sparc64, there does still exist trap 0x111 as tl0_oldlinux64, which was replac

[PATCH v2 10/15] linux-user/sparc: Handle priviledged opcode trap

For the most part priviledged opcodes are ifdefed out of the user-only sparc translator, which will then incorrectly produce illegal opcode traps. But there are some code paths that properly raise TT_PRIV_INSN, so we must handle it. Signed-off-by: Richard Henderson --- linux-user/sparc/cpu_loop

[PATCH v2 11/15] linux-user/sparc: Handle privilidged action trap

This is raised by using an %asi < 0x80 in user-mode. Signed-off-by: Richard Henderson --- linux-user/sparc/cpu_loop.c | 6 ++ 1 file changed, 6 insertions(+) diff --git a/linux-user/sparc/cpu_loop.c b/linux-user/sparc/cpu_loop.c index 61b6e81459..43f19fbd91 100644 --- a/linux-user/sparc/cpu

[PATCH v2 06/15] linux-user/sparc: Fix sparc64_{get, set}_context traps

These traps are present for sparc64 with ilp32, aka sparc32plus. Enabling them means adjusting the defines over in signal.c, and fixing an incorrect usage of abi_ulong when we really meant the full register, target_ulong. Signed-off-by: Richard Henderson --- linux-user/sparc/cpu_loop.c | 23

[PATCH v2 08/15] linux-user/sparc: Handle division by zero traps

In addition to the hw trap vector, there is a software trap assigned for older sparc without hw division instructions. Signed-off-by: Richard Henderson --- linux-user/sparc/cpu_loop.c | 5 + 1 file changed, 5 insertions(+) diff --git a/linux-user/sparc/cpu_loop.c b/linux-user/sparc/cpu_loop

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