On Wed, Feb 08, 2023 at 04:12:56PM -0500, Michael S. Tsirkin wrote:
> This reverts commit 67f7e426e53833a5db75b0d813e8d537b8a75bd2.
>
> Fixes: 67f7e426e5 ("hw/i386: pass RNG seed via setup_data entry")
> Signed-off-by: Michael S. Tsirkin
> ---
> include/hw/i386/pc.h | 3 ---
> include/hw/i386/
On Mon, Feb 13, 2023 at 05:30:03PM +0100, Eric Auger wrote:
> Hi Jean,
>
> On 2/10/23 17:37, Jean-Philippe Brucker wrote:
> > Addresses targeting the second translation table (TTB1) in the SMMU have
> > all upper bits set (except for the top byte when TBI is enabled). Fix
> > the TTB1 check.
> >
>
On 14.02.23 17:29, Fiona Ebner wrote:
[..]
[0]: Is there a good way to peek the iterator without doing something
like the following (we do know the offset from last time in
mirror_iteration(), so that is not an issue)?
offset_from_last_time = bdrv_dirty_iter_next(s->dbi);
...other stuff...
pe
On Mon, Feb 13, 2023, 8:20 AM Markus Armbruster wrote:
> *** BLURB HERE ***
>
đ€«
> Markus Armbruster (2):
> docs/devel/qapi-code-gen: Belatedly update features documentation
> docs/devel/qapi-code-gen: Fix a missing 'may', clarify SchemaInfo
>
> docs/devel/qapi-code-gen.rst | 16 --
On Tue, Feb 14, 2023, 11:49 AM John Snow wrote:
>
>
> On Mon, Feb 13, 2023, 8:20 AM Markus Armbruster wrote:
>
>> *** BLURB HERE ***
>>
>
> đ€«
>
>
>> Markus Armbruster (2):
>> docs/devel/qapi-code-gen: Belatedly update features documentation
>> docs/devel/qapi-code-gen: Fix a missing 'may', c
On Tue, Feb 14, 2023 at 05:23:08PM +0100, Markus Armbruster wrote:
> Daniel P. Berrangé writes:
>
> > On Tue, Feb 14, 2023 at 05:36:32PM +0400, Marc-André Lureau wrote:
> >> Hi
> >>
> >> On Tue, Feb 14, 2023 at 5:34 PM Markus Armbruster
> >> wrote:
> >> >
> >> > marcandre.lur...@redhat.com wri
On Sat, Feb 11, 2023, 1:49 AM Markus Armbruster wrote:
> John Snow writes:
>
> > This patch creates a new type, QAPIExpression, which represents a parsed
> > expression complete with QAPIDoc and QAPISourceInfo.
> >
> > This patch turns parser.exprs into a list of QAPIExpression instead,
> > and
On 2/14/23 06:44, Peter Maydell wrote:
This will cause us to not use the generic aarch64 flush_idcache_range(),
which uses DC CVAU and IC IVAU. Does that not work on Windows?
If it doesn't then I think the ifdeffery would be more clearly
structured as
#elif defined(__aarch64__)
ifdef CONFIG_DA
On Sat, Feb 11, 2023, 5:06 AM Markus Armbruster wrote:
> John Snow writes:
>
> > --3b01fe05f45a096a
> > Content-Type: text/plain; charset="UTF-8"
> >
> > On Fri, Feb 10, 2023, 7:33 AM Markus Armbruster
> wrote:
> >
> >> Another observation...
> >>
> >> John Snow writes:
> >>
> >> >
On Mon, Feb 13, 2023 at 01:38:28PM +, Daniel P. Berrangé wrote:
> Date: Mon, 13 Feb 2023 13:38:28 +
> From: "Daniel P. Berrangé"
> Subject: Re: [RFC 00/52] Introduce hybrid CPU topology
>
> On Mon, Feb 13, 2023 at 05:49:43PM +0800, Zhao Liu wrote:
> > From: Zhao Liu
> > ## 3.3. "-hybrid"
On Fri, Feb 10, 2023, 11:26 AM John Snow wrote:
>
>
> On Fri, Feb 10, 2023, 10:44 AM Markus Armbruster
> wrote:
>
>> John Snow writes:
>>
>> > mypy can only narrow the type of `Mapping[str, ...].keys() & Set[str]`
>> > to `AbstractSet[str]` and not a `Set[str]`. As a result, if the type of
>> >
On 02.02.23 21:15, Andrey Zhadchenko via wrote:
The last return statement should return true, as we already evaluated that
start == next_dirty
Also, fix hbitmap_status() description in header
Cc: qemu-sta...@nongnu.org
Fixes: a6426475a75 ("block/dirty-bitmap: introduce bdrv_dirty_bitmap_status(
bdrv_append() is called with bs_top AioContext held, but
bdrv_attach_child_noperm() could change the AioContext of bs_top.
bdrv_replace_node_noperm() calls bdrv_drained_begin() starting from
commit 2398747128 ("block: Don't poll in bdrv_replace_child_noperm()").
bdrv_drained_begin() can call BDRV_
From: Klaus Jensen
Add an example I2C device to demonstrate how a slave may master the bus
and send data asynchronously to another slave.
The device will echo whatever it is sent to the device identified by the
first byte received.
Signed-off-by: Klaus Jensen
[ clg: - Changed to build to use C
It's cleaner and removes the curious '+ 1' required to skip the DMA
IRQ line of the controller.
Signed-off-by: CĂ©dric Le Goater
---
hw/arm/aspeed.c | 2 +-
hw/ssi/aspeed_smc.c | 5 +
2 files changed, 2 insertions(+), 5 deletions(-)
diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
index 27
From: Klaus Jensen
It is not given that the current master will release the bus after a
transfer ends. Only schedule a pending master if the bus is idle.
Fixes: 37fa5ca42623 ("hw/i2c: support multiple masters")
Signed-off-by: Klaus Jensen
Acked-by: Corey Minyard
Message-Id: <20221116084312.358
It has become difficult to define on the command line the flash
devices of the Aspeed machines and their file backend. Currently, a
set of default flash devices is created at machine init and drives are
associated to the FMC and SPI controller devices in sequence :
-drive file,format=raw,if=mtd
To avoid the SPI transactions fetching instructions from the FMC CE0
flash device and speed up boot, a ROM can be created if a drive is
available.
Reverse a bit the logic to allow a machine to boot without a drive,
using a block device instead :
-blockdev node-name=fmc0,driver=file,filename=/
Test extracted from :
https://lists.nongnu.org/archive/html/qemu-devel/2022-06/msg00183.html
Signed-off-by: CĂ©dric Le Goater
---
tests/avocado/machine_aspeed.py | 10 ++
1 file changed, 10 insertions(+)
diff --git a/tests/avocado/machine_aspeed.py b/tests/avocado/machine_aspeed.py
in
Currently, when a block backend is attached to a m25p80 device and the
associated file size does not match the flash model, QEMU complains
with the error message "failed to read the initial flash content".
This is confusing for the user.
Use blk_check_size_and_read_all() instead of blk_pread() to
On 2/2/23 6:54 PM, Peter Maydell wrote:
On Mon, 23 Jan 2023 at 16:23, Evgeny Iakovlev
wrote:
>
> v4:
> * Fixed post_load hook to be backwards-migratable
> * Refactored some code in 5/5 as per review comments
>
> v3:
> * Introduced a post_load hook for PL011State migration for
>backwards-
Addresses targeting the second translation table (TTB1) in the SMMU have
all upper bits set (except for the top byte when TBI is enabled). Fix
the TTB1 check.
Reported-by: Ola Hugosson
Reviewed-by: Eric Auger
Reviewed-by: Richard Henderson
Signed-off-by: Jean-Philippe Brucker
---
hw/arm/smmu-
Addresses targeting the second translation table (TTB1) in the SMMU have
all upper bits set. Ensure the IOMMU region covers all 64 bits.
Reviewed-by: Richard Henderson
Signed-off-by: Jean-Philippe Brucker
---
include/hw/arm/smmu-common.h | 2 --
hw/arm/smmu-common.c | 2 +-
2 files chan
The default boot of the Aspeed SoCs is address 0x0. For this reason,
the FMC flash device contents are remapped by HW on the first 256MB of
the address space. In QEMU, this is currently done in the machine init
with the setup of a region alias.
Move this code to the SoC and introduce an extra cont
Hello,
This series starts with a first set of patches fixing I2C slave mode
in the Aspeed I2C controller, a test device and its associated test in
avocado.
Follow some cleanups which allow the use of block devices instead of
drives. So that, instead of specifying :
-drive file=./flash-ast2600-
Two small changes to support TTB1. Since [v1] I removed the unused
SMMU_MAX_VA_BITS and added tags, thanks!
[v1]
https://lore.kernel.org/qemu-devel/20230210163731.970130-1-jean-phili...@linaro.org/
Jean-Philippe Brucker (2):
hw/arm/smmu-common: Support 64-bit addresses
hw/arm/smmu-common: Fi
Am 14.02.2023 um 15:03 hat Paolo Bonzini geschrieben:
> In the case of Python the issue is not the interpreter per se, though
> there are a couple new feature in Python 3.7 that are quite nice (for
> example improved data classes[1] or context variables[2]). The main
> problem as far as I understoo
On Tue, Feb 14, 2023 at 07:04:56AM +, Duan, Zhenzhong wrote:
> >> @@ -1936,7 +1935,7 @@ void
> >> memory_region_iommu_replay(IOMMUMemoryRegion *iommu_mr,
> >IOMMUNotifier
> >> *n)
> >>
> >> granularity = memory_region_iommu_get_min_page_size(iommu_mr);
> >>
> >> -for (addr = 0; addr <
The link to the Linear theme that provided the basis for the QEMU web site
is dead. Replace it with something that at least works.
Signed-off-by: Paolo Bonzini
---
LICENSE.md | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/LICENSE.md b/LICENSE.md
index 218e3c7..330ac2a
On 2/14/23 12:12, weiwei wrote:
On 2023/2/11 19:50, Daniel Henrique Barboza wrote:
On 2/10/23 23:43, weiwei wrote:
On 2023/2/10 21:36, Daniel Henrique Barboza wrote:
At this moment, and apparently since ever, we have no way of enabling
RISCV_FEATURE_MISA. This means that all the code fr
On 03.02.23 12:18, Alexander Ivanov wrote:
data_end field in BDRVParallelsState is set to the biggest offset present
in BAT. If this offset is outside of the image, any further write will
create the cluster at this offset and/or the image will be truncated to
this offset on close. This is definit
On 2/14/23 17:08, Philippe Mathieu-Daudé wrote:
On 14/2/23 16:38, Stefan Hajnoczi wrote:
On Sat, Feb 04, 2023 at 11:29:41PM -0500, Alexander Bulekov wrote:
Hello,
This series removes fork-based fuzzing.
How does fork-based fuzzing work?
 * A single parent process initializes QEMU
 * We identi
On 03.02.23 12:18, Alexander Ivanov wrote:
Don't let high_off be more than the file size even if we don't fix the
image.
Signed-off-by: Alexander Ivanov
Reviewed-by: Denis V. Lunev
Reviewed-by: Vladimir Sementsov-Ogievskiy
--
Best regards,
Vladimir
On Tue, Feb 14, 2023 at 04:45:57PM +, Daniel P. Berrangé wrote:
> On Wed, Feb 08, 2023 at 04:12:56PM -0500, Michael S. Tsirkin wrote:
> > This reverts commit 67f7e426e53833a5db75b0d813e8d537b8a75bd2.
> >
> > Fixes: 67f7e426e5 ("hw/i386: pass RNG seed via setup_data entry")
> > Signed-off-by: M
Markus Armbruster wrote:
> Juan Quintela writes:
>
>> We used to synchronize all channels at the end of each RAM section
>> sent. That is not needed, so preparing to only synchronize once every
>> full round in latests patches.
>>
>> Notice that we initialize the property as true. We will chang
On Mon, Feb 13, 2023 at 7:51 AM Si-Wei Liu wrote:
>
>
>
> On 2/8/2023 1:42 AM, Eugenio PĂ©rez wrote:
> > Devices with CVQ needs to migrate state beyond vq state. Leaving this
> > to future series.
> >
> > Signed-off-by: Eugenio PĂ©rez
> > ---
> > net/vhost-vdpa.c | 6 ++
> > 1 file changed,
On Thu, Feb 9, 2023 at 3:46 PM Stefan Hajnoczi wrote:
>
> Hi,
> For those using the https://github.com/stefanha/patches tool to work
> with QEMU patch series, please update your configuration file to the new
> patches.json URL:
>
> $ $EDITOR ~/.patchesrc
> [fetch]
> url=https://patches.qemu.
On Mon, Feb 13, 2023, Isaku Yamahata wrote:
> On Fri, Feb 10, 2023 at 12:35:30AM +,
> Sean Christopherson wrote:
>
> > On Wed, Feb 08, 2023, Isaku Yamahata wrote:
> > > On Fri, Dec 02, 2022 at 02:13:40PM +0800,
> > > Chao Peng wrote:
> > >
> > > > +static int kvm_vm_ioctl_set_mem_attributes
On 2/13/23 06:13, Pierrick Bouvier wrote:
When compiling for windows-arm64 using clang-15, it reports a sometimes
uninitialized variable. This seems to be a false positive, as a default
case guards switch expressions, preventing to return an uninitialized
value, but clang seems unhappy with asser
Vladimir Sementsov-Ogievskiy wrote:
> On 08.02.23 16:57, Juan Quintela wrote:
>> {
>> -uint64_t pend_pre, pend_compat, pend_post;
>> +uint64_t pend_pre, pend_post;
>> bool in_postcopy = s->state == MIGRATION_STATUS_POSTCOPY_ACTIVE;
>> -qemu_savevm_state_pending_estimate(&pend
Vladimir Sementsov-Ogievskiy wrote:
> On 08.02.23 16:57, Juan Quintela wrote:
>> Once that res_compatible is removed, they don't make sense anymore.
>> Signed-off-by: Juan Quintela
>> ---
>> include/migration/register.h | 18 --
>> migration/savevm.h | 8
On Thu, Feb 2, 2023 at 7:08 AM Fiona Ebner wrote:
>
> Hi,
> over the years we've got 1-2 dozen reports[0] about suddenly
> missing/corrupted MBR/partition tables. The issue seems to be very rare
> and there was no success in trying to reproduce it yet. I'm asking here
> in the hope that somebody h
I have to admit this is out of my scope now. Still feel free to Cc me
directly if my help is needed :)
Signed-off-by: Vladimir Sementsov-Ogievskiy
---
MAINTAINERS | 2 --
1 file changed, 2 deletions(-)
diff --git a/MAINTAINERS b/MAINTAINERS
index 96e25f62ac..12bc96f52a 100644
--- a/MAINTAINERS
On 14.02.23 21:22, Juan Quintela wrote:
Vladimir Sementsov-Ogievskiy wrote:
On 08.02.23 16:57, Juan Quintela wrote:
Once that res_compatible is removed, they don't make sense anymore.
Signed-off-by: Juan Quintela
---
include/migration/register.h | 18 --
migration/savev
On Thu, Feb 9, 2023 at 7:31 PM John Snow wrote:
>
> Howdy, this series increases our minimum python version to 3.7.
>
> CI: https://gitlab.com/jsnow/qemu/-/pipelines/771780626
> (All green!)
> GL: https://gitlab.com/jsnow/qemu/-/commits/python-require-37
>
> Patches 1 and 2 are loose pre-requi
On 2/14/23 17:46, Jean-Philippe Brucker wrote:
> On Mon, Feb 13, 2023 at 05:30:03PM +0100, Eric Auger wrote:
>> Hi Jean,
>>
>> On 2/10/23 17:37, Jean-Philippe Brucker wrote:
>>> Addresses targeting the second translation table (TTB1) in the SMMU have
>>> all upper bits set (except for the top by
Hi Jean,
On 2/14/23 18:19, Jean-Philippe Brucker wrote:
> Addresses targeting the second translation table (TTB1) in the SMMU have
> all upper bits set. Ensure the IOMMU region covers all 64 bits.
>
> Reviewed-by: Richard Henderson
> Signed-off-by: Jean-Philippe Brucker
Reviewed-by: Eric Auger
On Tue, 31 Jan 2023, Jonathan Cameron wrote:
From: Gregory Price
This commit enables each CXL Type-3 device to contain one volatile
memory region and one persistent region.
Two new properties have been added to cxl-type3 device initialization:
[volatile-memdev] and [persistent-memdev]
The
This extends the QAPI schema validation to permit unions inside unions,
provided the checks for clashing fields pass.
Signed-off-by: Daniel P. Berrangé
---
This patch comes out of the discussion on Het's migration series
starting at this patch:
https://lists.gnu.org/archive/html/qemu-devel/20
On Tue, 14 Feb 2023 at 12:59, Laurent Vivier wrote:
>
> On 2/14/23 17:08, Philippe Mathieu-Daudé wrote:
> > On 14/2/23 16:38, Stefan Hajnoczi wrote:
> >> On Sat, Feb 04, 2023 at 11:29:41PM -0500, Alexander Bulekov wrote:
> >>> Hello,
> >>> This series removes fork-based fuzzing.
> >>> How does for
On 2/14/23 00:18, Philippe Mathieu-Daudé wrote:
 __attribute__((nonnull)) void a1(void *ptr)
 {
  // can no use assert(ptr) because compiler warning
 }
I briefly glossed over that...
I realize we'd probably want to add -fno-delete-null-pointer-checks if we make too much
... here. The
On Mon, Feb 13, 2023 at 11:37 PM Si-Wei Liu wrote:
>
>
>
> On 2/13/2023 1:47 AM, Eugenio Perez Martin wrote:
> > On Sat, Feb 4, 2023 at 3:04 AM Si-Wei Liu wrote:
> >>
> >>
> >> On 2/2/2023 7:28 AM, Eugenio Perez Martin wrote:
> >>> On Thu, Feb 2, 2023 at 2:53 AM Si-Wei Liu wrote:
>
> O
Richard Henderson writes:
> Make the form of the function names between fp and sve the same:
> - arm_gdb_*_svereg -> aarch64_gdb_*_sve_reg.
> - aarch64_fpu_gdb_*_reg -> aarch64_gdb_*_fpu_reg.
>
> Signed-off-by: Richard Henderson
Reviewed-by: Fabiano Rosas
Richard Henderson writes:
> This function is not used outside gdbstub.c.
>
> Signed-off-by: Richard Henderson
Reviewed-by: Fabiano Rosas
On Tue, Feb 14, 2023 at 2:45 AM Si-Wei Liu wrote:
>
>
>
> On 2/13/2023 3:14 AM, Eugenio Perez Martin wrote:
> > On Mon, Feb 13, 2023 at 7:51 AM Si-Wei Liu wrote:
> >>
> >>
> >> On 2/8/2023 1:42 AM, Eugenio PĂ©rez wrote:
> >>> Only create iova_tree if and when it is needed.
> >>>
> >>> The cleanup
Richard Henderson writes:
> The function is only used for aarch64, so move it to the
> file that has the other aarch64 gdbstub stuff. Move the
> declaration to internals.h.
>
> Signed-off-by: Richard Henderson
Reviewed-by: Fabiano Rosas
On 14/02/2023 17.08, Philippe Mathieu-Daudé wrote:
On 14/2/23 16:38, Stefan Hajnoczi wrote:
On Sat, Feb 04, 2023 at 11:29:41PM -0500, Alexander Bulekov wrote:
Hello,
This series removes fork-based fuzzing.
How does fork-based fuzzing work?
 * A single parent process initializes QEMU
 * We ide
On 230214 2009, Thomas Huth wrote:
> On 14/02/2023 17.08, Philippe Mathieu-Daudé wrote:
> > On 14/2/23 16:38, Stefan Hajnoczi wrote:
> > > On Sat, Feb 04, 2023 at 11:29:41PM -0500, Alexander Bulekov wrote:
> > > > Hello,
> > > > This series removes fork-based fuzzing.
> > > > How does fork-based fu
This enum is no longer used after write_misa() started reading the value
from cpu->cfg.misa_w.
Reviewed-by: Weiwei Li
Signed-off-by: Daniel Henrique Barboza
---
target/riscv/cpu.h | 1 -
1 file changed, 1 deletion(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index fe572b83e9..00a464
Hi,
This new version contains suggestions made by Weiwei Li in v1. Most
notable change is patch 4 from v1, moving up to patch 2 now, to allow
the riscv_cpu_cfg() helper to be used in the MISA CSR patch.
Changes in v2:
- former patch 4 moved to patch 2
- patch 3 (former 2):
- use riscv_cpu_cfg
RISCV_FEATURE_EPMP is always set to the same value as the cpu->cfg.epmp
flag. Use the flag directly.
Reviewed-by: Weiwei Li
Signed-off-by: Daniel Henrique Barboza
---
target/riscv/cpu.c | 10 +++---
target/riscv/cpu.h | 1 -
target/riscv/csr.c | 2 +-
target/riscv/pmp.c | 4 ++--
4 files
The masking done using env->misa_ext_mask already filters any extension
that QEMU doesn't support. If the hart supports the extension then QEMU
supports it as well.
If the masking done by env->misa_ext_mask is somehow letting unsupported
QEMU extensions pass by, misa_ext_mask itself needs to be fi
RISCV_FEATURE_PMP is being set via riscv_set_feature() by mirroring the
cpu->cfg.pmp flag. Use the flag instead.
Reviewed-by: Weiwei Li
Signed-off-by: Daniel Henrique Barboza
---
target/riscv/cpu.c| 4
target/riscv/cpu.h| 1 -
target/riscv/cpu_helper.c | 2 +-
target/riscv/
Instead of silently ignoring the EPMP setting if there is no PMP
available, error out informing the user that EPMP depends on PMP
support:
$ ./qemu-system-riscv64 -cpu rv64,pmp=false,x-epmp=true
qemu-system-riscv64: Invalid configuration: EPMP requires PMP support
This will force users to pick sa
Read cpu_ptr->cfg.mmu directly. As a bonus, use cpu_ptr in
riscv_isa_string().
Reviewed-by: Weiwei Li
Signed-off-by: Daniel Henrique Barboza
---
hw/riscv/virt.c | 7 ---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index 86c4adc0c9..49f2c15
On 01.11.22 18:37, Denis Plotnikov wrote:
Add "start" & "end" time values to QMP command responses.
These time values are added to let the qemu management layer get the exact
command execution time without any other time variance which might be brought
by other parts of management layer or qemu
RISCV_FEATURE_DEBUG will always follow the value defined by
cpu->cfg.debug flag. Read the flag instead.
Reviewed-by: Weiwei Li
Signed-off-by: Daniel Henrique Barboza
---
target/riscv/cpu.c| 6 +-
target/riscv/cpu.h| 1 -
target/riscv/cpu_helper.c | 2 +-
target/riscv/csr.c
RISCV_FEATURE_MMU is set whether cpu->cfg.mmu is set, so let's just use
the flag directly instead.
With this change the enum is also removed. It is worth noticing that
this enum, and all the RISCV_FEATURES_* that were contained in it,
predates the existence of the cpu->cfg object. Today, using cpu
The attribute is no longer used since we can retrieve all the enabled
features in the hart by using cpu->cfg instead.
Remove env->feature, riscv_feature() and riscv_set_feature(). We also
need to bump vmstate_riscv_cpu version_id and minimal_version_id since
'features' is no longer being migrated.
At this moment, and apparently since ever, we have no way of enabling
RISCV_FEATURE_MISA. This means that all the code from write_misa(), all
the nuts and bolts that handles how to properly write this CSR, has
always been a no-op as well because write_misa() will always exit
earlier.
This seems to
We're going to do changes that requires accessing the RISCVCPUConfig
struct from the RISCVCPU, having access only to a CPURISCVState 'env'
pointer. Add a helper to make the code easier to read.
Reviewed-by: Weiwei Li
Signed-off-by: Daniel Henrique Barboza
---
target/riscv/cpu.h | 5 +
1 fil
On 13/02/2023 16:00, Vladimir Sementsov-Ogievskiy wrote:
0 is not a valid state for the led. Let's start with OFF.
Signed-off-by: Vladimir Sementsov-Ogievskiy
---
hw/pci/shpc.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/hw/pci/shpc.c b/hw/pci/shpc.c
index fca7f6691a..1b3f619dc9 1006
On 13/02/2023 16:00, Vladimir Sementsov-Ogievskiy wrote:
The result of the function is always one byte. The result is always
assigned to uint8_t variable. Also, shpc_get_status() should be
symmetric to shpc_set_status() which has uint8_t value argument.
Signed-off-by: Vladimir Sementsov-Ogievski
On 13/02/2023 16:00, Vladimir Sementsov-Ogievskiy wrote:
ENABLED -> PWRONLY transition is not allowed and we handle it by
shpc_invalid_command(). But PWRONLY -> ENABLED transition is silently
ignored, which seems wrong. Let's handle it as correct.
Signed-off-by: Vladimir Sementsov-Ogievskiy
---
On 13/02/2023 16:00, Vladimir Sementsov-Ogievskiy wrote:
Free slot if both conditions (power-led = OFF and state = DISABLED)
becomes true regardless of the sequence. It is similar to how PCIe
hotplug works.
Signed-off-by: Vladimir Sementsov-Ogievskiy
---
hw/pci/shpc.c | 52 +++
Richard Henderson writes:
> Create a subroutine for creating the union of unions
> of the various type sizes that a vector may contain.
>
> Signed-off-by: Richard Henderson
Reviewed-by: Fabiano Rosas
On 13/02/2023 16:00, Vladimir Sementsov-Ogievskiy wrote:
We'll need it in further patch to report bridge in QAPI event.
Signed-off-by: Vladimir Sementsov-Ogievskiy
---
hw/pci/shpc.c | 18 ++
1 file changed, 10 insertions(+), 8 deletions(-)
diff --git a/hw/pci/shpc.c b/hw/pci
On 13/02/2023 16:00, Vladimir Sementsov-Ogievskiy wrote:
Rename it to shpc_device_get_slot(), to mention what it does rather
than how it is used. It also helps to reuse it in further commit.
Also, add a return value and get rid of local_err.
Signed-off-by: Vladimir Sementsov-Ogievskiy
---
hw
On 13/02/2023 16:00, Vladimir Sementsov-Ogievskiy wrote:
PCI_EXP_SLTCTL_PIC_OFF is a value, and PCI_EXP_SLTCTL_PIC is a mask.
Happily PCI_EXP_SLTCTL_PIC_OFF is a maximum value for this mask and is
equal to the mask itself. Still the code looks like a bug. Let's make
it more reader-friendly.
Sign
On 13/02/2023 16:00, Vladimir Sementsov-Ogievskiy wrote:
We already have indicator values in
include/standard-headers/linux/pci_regs.h , no reason to reinvent them
in include/hw/pci/pcie_regs.h. (and we already have usage of
PCI_EXP_SLTCTL_PWR_IND_BLINK and PCI_EXP_SLTCTL_PWR_IND_OFF in
hw/pci/pc
On 13/02/2023 16:00, Vladimir Sementsov-Ogievskiy wrote:
The structure type is unused. Also, it's the only user of corresponding
macros, so drop them too.
Signed-off-by: Vladimir Sementsov-Ogievskiy
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Anton Kuchin
---
include/hw/pci/pcie.h
On 13/02/2023 16:00, Vladimir Sementsov-Ogievskiy wrote:
*_by_mask() helpers shouldn't be used here (and that's the only one).
*_by_mask() helpers do shift their value argument, but in pcie.c code
we use values that are already shifted appropriately.
Happily, PCI_EXP_SLTCTL_PWR_ON is zero, so shi
On 13/02/2023 16:00, Vladimir Sementsov-Ogievskiy wrote:
In pcie_cap_slot_write_config() we check for PCI_EXP_SLTCTL_PWR_OFF in
a bad form. We should distinguish PCI_EXP_SLTCTL_PWR which is a "mask"
and PCI_EXP_SLTCTL_PWR_OFF which is value for that mask.
Better code is in pcie_cap_slot_unplug_r
On 13/02/2023 16:00, Vladimir Sementsov-Ogievskiy wrote:
It should be zero, the only valid values are ON, OFF and BLINK.
Signed-off-by: Vladimir Sementsov-Ogievskiy
Reviewed-by: Anton Kuchin
---
hw/pci/pcie.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/hw/pci/pcie.c b/hw/pci/pcie.
Richard Henderson writes:
> Rather than increment base_reg and num, compute num
> from the change to base_reg at the end. Clean up some
> nearby comments.
>
> Signed-off-by: Richard Henderson
> ---
> target/arm/gdbstub64.c | 26 --
> 1 file changed, 16 insertions(+), 10
On 13/02/2023 16:01, Vladimir Sementsov-Ogievskiy wrote:
To be used in further patch to identify the device hot-plugged into
pcie-root-port.
Signed-off-by: Vladimir Sementsov-Ogievskiy
Reviewed-by: Anton Kuchin
---
include/hw/pci/pci.h | 1 +
hw/pci/pci.c | 33 +++
Richard Henderson writes:
> Signed-off-by: Richard Henderson
> ---
> target/arm/gdbstub64.c | 5 +++--
> 1 file changed, 3 insertions(+), 2 deletions(-)
>
> diff --git a/target/arm/gdbstub64.c b/target/arm/gdbstub64.c
> index 8d174ff6e0..02a0256c5c 100644
> --- a/target/arm/gdbstub64.c
> +++ b/
On 13.01.23 14:29, Kevin Wolf wrote:
Another thing that could be tried is making failure in .bdrv_close less
likely by doing things earlier. At least ENOSPC could probably be
avoided if dirty bitmaps clusters were allocated during the write
request that first sets a bit in them (I know too little
Hi, all.
In the future, there would be eBPF RSS + the helper for Libvirt interaction.
And those patches are required for future work. Technically they are
required for the current builds with linked libbpf 1.01.
Can we apply this patch?
On Wed, Dec 28, 2022 at 6:19 PM Andrew Melnichenko wrote:
>
On 2/13/23 14:27, Warner Losh wrote:
+#ifdef TARGET_ABI32
+/*
+ * Limit the amount of available memory to be most of the 32-bit address
+ * space. 0x100c000 was arrived at through trial and error as a good
+ * definition of 'most'.
+ */
+static const abi_ulong target_max_mem = UINT32_MAX - 0x100c
On 2/13/23 14:27, Warner Losh wrote:
From: Stacey Son
oidfmt uses undocumented system call to get the type of the sysctl.
Co-Authored-by: Sean Bruno
Signed-off-by: Sean Bruno
Co-Authored-by: Juergen Lock
Signed-off-by: Juergen Lock
Co-Authored-by: Raphael Kubo da Costa
Signed-off-by: Raphael Ku
Il mar 14 feb 2023, 18:26 Kevin Wolf ha scritto:
> Am 14.02.2023 um 15:03 hat Paolo Bonzini geschrieben:
> > In the case of Python the issue is not the interpreter per se, though
> > there are a couple new feature in Python 3.7 that are quite nice (for
> > example improved data classes[1] or cont
On 14/02/2023 20.14, Alexander Bulekov wrote:
On 230214 2009, Thomas Huth wrote:
On 14/02/2023 17.08, Philippe Mathieu-Daudé wrote:
On 14/2/23 16:38, Stefan Hajnoczi wrote:
On Sat, Feb 04, 2023 at 11:29:41PM -0500, Alexander Bulekov wrote:
Hello,
This series removes fork-based fuzzing.
How do
On 2/13/23 14:27, Warner Losh wrote:
+/*
+ * Convert the old value from host to target.
host vs guest is clearer language; "target" gets overloaded, even though still present in
the code base.
+ *
+ * For LONG and ULONG on ABI32, we need to 'down convert' the 8 byte quantities
+ * to 4 byte
On 2/13/23 14:27, Warner Losh wrote:
From: Juergen Lock
Helper functions for sysctl implementations. sysctl_name2oid and
sysctl_oidfmt convert oids between host and targets
Signed-off-by: Juergen Lock
Reviewed-by: Warner Losh
Signed-off-by: Warner Losh
---
bsd-user/freebsd/os-sys.c | 18 +
On 2/13/23 14:27, Warner Losh wrote:
From: Juergen Lock
do_freebsd_sysctl_oid filters out some of the binary and special sysctls
where host != target. None of the sysctls that have to be translated from
host to target are handled here.
Signed-off-by: Juergen Lock
Co-Authored-by: Stacey Son
S
On Sun, 12 Feb 2023 17:36:49 +0200
Avihai Horon wrote:
> On 27/01/2023 23:11, Alex Williamson wrote:
> > External email: Use caution opening links or attachments
> >
> >
> > On Thu, 26 Jan 2023 20:49:35 +0200
> > Avihai Horon wrote:
> >
> >> There are already two places where dirty page bitmap
On Tue, Feb 14, 2023 at 1:52 PM Richard Henderson <
richard.hender...@linaro.org> wrote:
> On 2/13/23 14:27, Warner Losh wrote:
> > +#ifdef TARGET_ABI32
> > +/*
> > + * Limit the amount of available memory to be most of the 32-bit address
> > + * space. 0x100c000 was arrived at through trial and e
On 2/13/23 14:27, Warner Losh wrote:
+case HW_NCPU:
+if (oldlen) {
+(*(int32_t *)holdp) = tswap32(bsd_get_ncpu());
+}
+holdlen = sizeof(int32_t);
+ret = 0;
+goto out;
Anything using SYSCTL_INT should use abi_int
On 2/14/23 11:31, Warner Losh wrote:
Right now they aren't used at all for ABI64... But that's in later patches...Â
We only do
special things for LONG or ULONG on ABI32... Otherwise, the normal paths
wouldn't
call these at all.
Yes, I've just seen patch 9, and agree they aren't needed for a
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