On Wed, 2023-02-01 at 21:13 -0500, Kevin O'Connor wrote:
> On Fri, Jan 20, 2023 at 11:33:19AM +, David Woodhouse wrote:
> > From: David Woodhouse
> >
> > When running under Xen, hvmloader places a table at 0x1000 with the e820
> > information and BIOS tables. If this isn't present, SeaBIOS wi
Following kernel crash noticed on qemu-x86_64 intermittently with Linux next.
qemu-system-x86, installed at version: 7.2
Reported-by: Linux Kernel Functional Testing
Boot log:
---
<5>[0.00] Linux version 6.2.0-rc6-next-20230202
(tuxmake@tuxmake) (Debian clang version
On 2023/02/02 16:26, Sriram Yagnaraman wrote:
Also introduce:
- Checks for RXDCTL/TXDCTL queue enable bits
- IGB_NUM_VM_POOLS enum (Sec 1.5: Table 1-7)
Signed-off-by: Sriram Yagnaraman
---
hw/net/igb_core.c | 39 +++
hw/net/igb_core.h | 1 +
hw/net/igb_r
Juan Quintela writes:
> Markus Armbruster wrote:
>> Juan Quintela writes:
>>
>>> Markus Armbruster wrote:
Juan Quintela writes:
> Markus Armbruster wrote:
>> The script drops #include "qemu/osdep.h" from headers. Mention it in
>> the commit message it uses for --git.
>
Based-on: <20230201042615.34706-1-akihiko.od...@daynix.com>
([PATCH v7 0/9] Introduce igb)
Rebased on latest changes from Akihiko, and merged changes from my
original patchset:
https://lists.gnu.org/archive/html/qemu-devel/2022-12/msg04670.html
Changes since v5:
- Added back an unecessarily remov
I would like to review and be informed on changes to igb device
Signed-off-by: Sriram Yagnaraman
---
MAINTAINERS | 1 +
1 file changed, 1 insertion(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index ece23b2b15..7d0e84ce37 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -2224,6 +2224,7 @@ F: tests/qt
Use PFRSTD to reset RSTI bit for VFs, and raise VFLRE interrupt when VF
is reset.
Signed-off-by: Sriram Yagnaraman
---
hw/net/igb_core.c | 33 +
hw/net/igb_regs.h | 3 +++
hw/net/trace-events | 2 ++
3 files changed, 26 insertions(+), 12 deletions(-)
diff -
Add support for stripping/inserting VLAN for VFs.
Had to move CSUM calculation back into the for loop, since packet data
is pulled inside the loop based on strip VLAN decision for every VF.
net_rx_pkt_fix_l4_csum should be extended to accept a buffer instead for
igb. Work for a future patch.
Sig
Signed-off-by: Sriram Yagnaraman
---
hw/net/igb_core.c | 41 -
1 file changed, 36 insertions(+), 5 deletions(-)
diff --git a/hw/net/igb_core.c b/hw/net/igb_core.c
index c4a2bff4c1..03139c76f7 100644
--- a/hw/net/igb_core.c
+++ b/hw/net/igb_core.c
@@ -915,1
RSS for VFs is only enabled if VMOLR[n].RSSE is set.
Signed-off-by: Sriram Yagnaraman
---
hw/net/igb_core.c | 9 -
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/hw/net/igb_core.c b/hw/net/igb_core.c
index 03139c76f7..9994724a39 100644
--- a/hw/net/igb_core.c
+++ b/hw/net/i
Please note that loopback counters for VM to VM traffic is not
implemented yet: VFGOTLBC, VFGPTLBC, VFGORLBC and VFGPRLBC.
Signed-off-by: Sriram Yagnaraman
---
hw/net/igb_core.c | 26 ++
1 file changed, 22 insertions(+), 4 deletions(-)
diff --git a/hw/net/igb_core.c b/hw
Also introduce:
- Checks for RXDCTL/TXDCTL queue enable bits
- IGB_NUM_VM_POOLS enum (Sec 1.5: Table 1-7)
Signed-off-by: Sriram Yagnaraman
---
hw/net/igb_core.c | 38 +++---
hw/net/igb_core.h | 1 +
hw/net/igb_regs.h | 3 +++
3 files changed, 35 insertions(+), 7
> Thanks, Kevin.
>
> I'd like to get the rest of the Xen platform support in to qemu 8.0 if
> possible. Which is currently scheduled for March.
>
> Is there likely to be a SeaBIOS release before then which Gerd would
> pull into qemu anyway, or should I submit a submodule update to a
> snapshot o
On Wed, Feb 01, 2023 at 04:12:32PM -0500, Stefan Hajnoczi wrote:
> Modernize the description and document the size=/offset= runtime
> options.
>
> Signed-off-by: Stefan Hajnoczi
> ---
> docs/system/qemu-block-drivers.rst.inc | 32 ++
> 1 file changed, 27 insertions(+), 5
On Wed, 1 Feb 2023 11:50:50 -1000
Richard Henderson wrote:
> On 2/1/23 05:24, Jørgen Hansen wrote:
> > Hello Richard,
> >
> > We are using x86 qemu to test some CXL stuff, and in that process we are
> > running into an issue with tcg. In qemu, CXL memory is mapped as an MMIO
> > region, so when
From: Zhao Liu
For function comments in this file, keep the comment style consistent
with other places.
Signed-off-by: Zhao Liu
---
include/hw/i386/topology.h | 33 +
1 file changed, 17 insertions(+), 16 deletions(-)
diff --git a/include/hw/i386/topology.h b/in
From: Zhao Liu
Hi list,
This series is based on 13356ed (Merge tag 'block-pull-request' of
https://gitlab.com/stefanha/qemu into staging), and adds the cluster
support for x86 PC machine, which allows x86 can use smp.clusters
to configure the modlue level CPU topology of x86.
And since the comp
From: Zhuocheng Ding
Support module level in i386 cpu topology structure "X86CPUTopoInfo".
Before updating APIC ID parsing rule with module level, the
apicid_core_width() temporarily combines the core and module levels
together.
At present, we don't expose module level in CPUID.1FH because curr
From: Zhuocheng Ding
>From CPUState.nr_cores' comment, it represents "number of cores within
this CPU package".
After 003f230 (machine: Tweak the order of topology members in struct
CpuTopology), the meaning of smp.cores changed to "the number of cores
in one die", but this commit missed to chan
From: Zhuocheng Ding
smp command has the "clusters" parameter but x86 hasn't supported that
level. Though "clusters" was introduced to help define L2 cache topology
[1], using cluster to define x86's L2 cache topology will cause the
compatibility problem:
Currently, x86 defaults that the L2 cach
From: Zhuocheng Ding
We introduce cluster-id other than module-id to be consistent with
CpuInstanceProperties.cluster-id, and this avoids the confusion
of parameter names when hotplugging.
Following the legacy smp check rules, also add the cluster_id validity
into x86_cpu_pre_plug().
Signed-off
From: Zhao Liu
CPUID[0x801D].EAX[bits 25:14] is used to represent the cache
topology for amd CPUs.
After cache models have topology information, we can use
CPUCacheInfo.share_level to decide which topology level to be encoded
into CPUID[0x801D].EAX[bits 25:14].
Signed-off-by: Zhao Liu
From: Zhao Liu
Currently, by default, the cache topology is encoded as:
1. i/d cache is shared in one core.
2. L2 cache is shared in one core.
3. L3 cache is shared in one die.
This default general setting has caused a misunderstanding, that is, the
cache topology is completely equated with a sp
From: Zhao Liu
In fact, this unit tests APIC ID other than CPUID.
Rename to test-x86-apicid.c to make its name more in line with its
actual content.
Signed-off-by: Zhao Liu
---
MAINTAINERS| 2 +-
tests/unit/meson.build | 4 ++-
From: Zhao Liu
The property x-l2-cache-topo will be used to change the L2 cache
topology in CPUID.04H.
Now it allows user to set the L2 cache is shared in core level or
cluster level.
If user passes "-cpu x-l2-cache-topo=[core|cluster]" then older L2 cache
topology will be overrided by the new
From: Zhuocheng Ding
Add the module level parsing support for APIC ID.
With this support, now the conversion between X86CPUTopoIDs,
X86CPUTopoInfo and APIC ID is completed.
Signed-off-by: Zhuocheng Ding
Co-developed-by: Zhao Liu
Signed-off-by: Zhao Liu
---
hw/i386/x86.c | 19 ++
From: Zhao Liu
In cpu_x86_cpuid(), there are many variables in representing the cpu
topology, e.g., topo_info, cs->nr_cores/cs->nr_threads.
Since the names of cs->nr_cores/cs->nr_threads does not accurately
represent its meaning, the use of cs->nr_cores/cs->nr_threads is prone
to confusion and m
From: Zhuocheng Ding
As module-level topology support is added to X86CPU, now we can enable
the support for the cluster parameter on PC machines. With this support,
we can define a 5-level x86 CPU topology with "-smp":
-smp cpus=*,maxcpus=*,sockets=*,dies=*,clusters=*,cores=*,threads=*.
Additio
From: Zhao Liu
Now smp supports dies and clusters, so add description about these 2
levels in the comment of machine_parse_smp_config().
Fixes: 864c3b5 (hw/core/machine: Introduce CPU cluster topology support)
Suggested-by: Robert Hoo
Signed-off-by: Zhao Liu
---
hw/core/machine-smp.c | 7
From: Zhao Liu
>From AMD's APM, NumSharingCache (CPUID[0x801D].EAX[bits 25:14])
means [1]:
The number of logical processors sharing this cache is the value of
this field incremented by 1. To determine which logical processors are
sharing a cache, determine a Share Id for each processor as fo
From: Zhuocheng Ding
Add module_id member in X86CPUTopoIDs.
module_id can be parsed from APIC ID, so before updating the parsing
rule of APIC ID, temporarily set the module_id generated in this way to
0.
module_id can be also generated from cpu topology, and before i386
supports "clusters" in s
From: Zhuocheng Ding
After i386 supports module level, it's time to add the test for module
level's parsing.
Signed-off-by: Zhuocheng Ding
Co-developed-by: Zhao Liu
Signed-off-by: Zhao Liu
---
tests/unit/test-x86-apicid.c | 19 +++
1 file changed, 15 insertions(+), 4 deletion
From: Zhao Liu
For i-cache and d-cache, the maximum IDs for CPUs sharing cache (
CPUID.04H.00H:EAX[bits 25:14] and CPUID.04H.01H:EAX[bits 25:14]) are
both 0, and this means i-cache and d-cache are shared in the SMT level.
This is correct if there's single thread per core, but is wrong for the
hyp
From: Zhao Liu
CPUID[4].EAX[bits 25:14] is used to represent the cache topology for
intel CPUs.
After cache models have topology information, we can use
CPUCacheInfo.share_level to decide which topology level to be encoded
into CPUID[4].EAX[bits 25:14].
Additionally, since maximum_processor_id
Anton Kuchin wrote:
> On 01/02/2023 16:26, Juan Quintela wrote:
>> Anton Kuchin wrote:
>>> On 19/01/2023 18:02, Stefan Hajnoczi wrote:
On Thu, 19 Jan 2023 at 10:29, Anton Kuchin
wrote:
> On 19/01/2023 16:30, Stefan Hajnoczi wrote:
>> On Thu, 19 Jan 2023 at 07:43, Anton Kuchin
> Are you running the Linux guest on multiple cores? If yes, could you
> check if the issue persists also when using a single core?
Yes, I was running with 2 cores. I just tested with 1 and 2 several times. I
haven't reproduced the bug with 1 core, but happens around 70% of the time with
2 cores
On Wed, 25 Jan 2023 at 02:34, John Snow wrote:
>
> The following changes since commit 13356edb87506c148b163b8c7eb0695647d00c2a:
>
> Merge tag 'block-pull-request' of https://gitlab.com/stefanha/qemu into
> staging (2023-01-24 09:45:33 +)
>
> are available in the Git repository at:
>
> htt
Vladimir Sementsov-Ogievskiy wrote:
> On 1/30/23 11:06, Juan Quintela wrote:
>> It was only used for RAM, and in that case, it means that this amount
>> of data was sent for memory. Just delete the field in all callers.
>
> Could you describe, why it's safe to change the behavior for RAM?
I will
Am 31.01.23 um 19:18 schrieb Denis V. Lunev:
> On 1/31/23 18:44, Vladimir Sementsov-Ogievskiy wrote:
>> + Den
>>
>> Den, I remember we thought about that, and probably had a solution?
>>
>> Another possible approach to get benefits from both modes is to switch
>> to blocking mode after first loop o
Am 31.01.23 um 18:44 schrieb Vladimir Sementsov-Ogievskiy:
>> @@ -1035,10 +1036,31 @@ static int coroutine_fn mirror_run(Job *job,
>> Error **errp)
>> if (s->in_flight == 0 && cnt == 0) {
>> trace_mirror_before_flush(s);
>> if (!job_is_ready(&s->common.job)) {
Vladimir Sementsov-Ogievskiy wrote:
> On 30.01.23 11:03, Juan Quintela wrote:
>> Signed-off-by: Juan Quintela
>> Reviewed-by: Dr. David Alan Gilbert
>> ---
>> migration/migration.c | 24
>> 1 file changed, 12 insertions(+), 12 deletions(-)
>> diff --git a/migration/mi
Peter Xu wrote:
> Add a helper to create the uffd handle.
>
> Reviewed-by: Philippe Mathieu-Daudé
> Signed-off-by: Peter Xu
Reviewed-by: Juan Quintela
I can get this one through migration tree.
On Fri, 6 Jan 2023 00:38:26 -0800
Lei Wang wrote:
> The new CPU model mostly inherits features from Icelake-Server, while
> adding new features:
> - AMX (Advance Matrix eXtensions)
> - Bus Lock Debug Exception
> and new instructions:
> - AVX VNNI (Vector Neural Network Instruction):
> - V
On 01/02/2023 14.20, Pierre Morel wrote:
S390 adds two new SMP levels, drawers and books to the CPU
topology.
The S390 CPU have specific toplogy features like dedication
Nit: s/toplogy/topology/
and polarity to give to the guest indications on the host
vCPUs scheduling and help the guest take
Hi Eric,
On 3/7/20 17:53, Peter Maydell wrote:
From: Eric Auger
At the moment the virtio-iommu translates MSI transactions.
This behavior is inherited from ARM SMMU. The virt machine
code knows where the guest MSI doorbells are so we can easily
declare those regions as VIRTIO_IOMMU_RESV_MEM_T_
On Wed, 1 Feb 2023 at 18:07, Alex Bennée wrote:
> Peter Maydell writes:
> > I think this is "you can't put labels in qemu-options.hx,
> > because it gets included in two .rst files (invocation.rst
> > and qemu-manpage.rst), and Sphinx complains about the
> > duplicate labels, even though one of t
On 2/2/23 11:47, Philippe Mathieu-Daudé wrote:
Hi Eric,
On 3/7/20 17:53, Peter Maydell wrote:
From: Eric Auger
At the moment the virtio-iommu translates MSI transactions.
This behavior is inherited from ARM SMMU. The virt machine
code knows where the guest MSI doorbells are so we can easily
d
Peter Xu wrote:
> Teach QEMU to use /dev/userfaultfd when it existed and fallback to the
> system call if either it's not there or doesn't have enough permission.
>
> Firstly, as long as the app has permission to access /dev/userfaultfd, it
> always have the ability to trap kernel faults which QEM
Peter Xu wrote:
> Signed-off-by: Peter Xu
How does this change gets into the tree?
I know that it is "automagically" generated, but who decides when that
goes into the tree?
As we need that for the following patch?
Later, Juan.
On Wed, 1 Feb 2023 at 20:37, Richard Henderson
wrote:
>
> On 2/1/23 04:20, Eric Auger wrote:
> > What I fail to understand is why this code is called with a kvm
> > accelerated qemu (the test runs by default with kvm).
> ...
> > #2 0x02aaab1500f0 in vmsa_ttbr_write
> > (env=0x2aaac393850, ri=
On Tue, 31 Jan 2023, BALATON Zoltan wrote:
On Tue, 31 Jan 2023, Akihiko Odaki wrote:
[...]
To summarise previous discussion:
- There's a problem on Apple M1 Macs with sm501 and ati-vga 2d accel
functions drawing from device model into the video memory of the emulated
card which is not shown o
Markus Armbruster wrote:
> It's less terse. Fine with me. The mix of passive and active voice
> feels a bit awkward, though. Another try:
>
> All .c should include qemu/osdep.h first. This script performs three
> related cleanups:
>
> * Ensure .c files include qemu/osdep.h first.
> *
On 2/1/23 23:39, Jonathan Cameron wrote:
Not sure - if we can do the handling above then sure we could make that change.
I can see there is a path to register the callbacks but I'd kind of assumed
ROM meant read only...
I think "romd" means "read mostly".
In the case of flash, I believe that a
On Thu, 2 Feb 2023 at 10:47, Philippe Mathieu-Daudé wrote:
> Where is "len-reserved-regions" declared?
DEFINE_PROP_ARRAY("reserved-regions", ...)
does this. For an array property "foo" the machinery creates an integer
property "foo-len", which must be set first. Setting that
then creates prope
Chuang Xu wrote:
> add rcu_read_is_locked() to detect holding of rcu lock.
>
> Signed-off-by: Chuang Xu
Reviewed-by: Juan Quintela
Althought I think that petting a review from Paolo or anyone that knows
more than RCU could be a good idea.
> ---
> include/qemu/rcu.h | 7 +++
> 1 file chan
Chuang Xu wrote:
> The duration of loading non-iterable vmstate accounts for a significant
> portion of downtime (starting with the timestamp of source qemu stop and
> ending with the timestamp of target qemu start). Most of the time is spent
> committing memory region changes repeatedly.
>
> This
David Hildenbrand wrote:
> On 17.01.23 12:22, David Hildenbrand wrote:
>> While playing with migration of virtio-mem with an ordinary file backing,
>> I realized that migration and prealloc doesn't currently work as expected
>> for virtio-mem. Further, Jing Qi reported that setup issues (insuffici
On Fri, 6 Jan 2023 00:38:20 -0800
Lei Wang wrote:
> This series aims to add a new CPU model SapphireRapids, and tries to
> address the problem stated in
> https://lore.kernel.org/all/20220812055751.14553-1-lei4.w...@intel.com/T/#mcf67dbd1ad37c65d7988c36a2b267be9afd2fb30,
> so that named CPU mode
Chuang Xu wrote:
> In this version:
>
> - rename rcu_read_locked() to rcu_read_is_locked().
> - adjust the sanity check in address_space_to_flatview().
> - improve some comments.
>
> The duration of loading non-iterable vmstate accounts for a significant
> portion of downtime (starting with the ti
On 2/2/23 11:58, Peter Maydell wrote:
On Thu, 2 Feb 2023 at 10:47, Philippe Mathieu-Daudé wrote:
Where is "len-reserved-regions" declared?
DEFINE_PROP_ARRAY("reserved-regions", ...)
does this. For an array property "foo" the machinery creates an integer
property "foo-len", which must be s
On 2/2/23 11:19, Fiona Ebner wrote:
Am 31.01.23 um 19:18 schrieb Denis V. Lunev:
On 1/31/23 18:44, Vladimir Sementsov-Ogievskiy wrote:
+ Den
Den, I remember we thought about that, and probably had a solution?
Another possible approach to get benefits from both modes is to switch
to blocking m
On Tue, Jan 17, 2023 at 12:22:41PM +0100, David Hildenbrand wrote:
> While playing with migration of virtio-mem with an ordinary file backing,
> I realized that migration and prealloc doesn't currently work as expected
> for virtio-mem. Further, Jing Qi reported that setup issues (insufficient
> hu
David Hildenbrand wrote:
> Unfortunately, commit f7b9dcfbcf44 broke populate_read_range(): the loop
> end condition is very wrong, resulting in that function not populating the
> full range. Lets' fix that.
>
> Fixes: f7b9dcfbcf44 ("migration/ram: Factor out populating pages readable in
> ram_blo
David Hildenbrand wrote:
> If something goes wrong during uffd_change_protection(), we would miss
> to unregister uffd-wp and not release our reference. Fix it by
> performing the uffd_change_protection(true) last.
>
> Note that a uffd_change_protection(false) on the recovery path without a
> prio
David Hildenbrand wrote:
> When unregistering uffd-wp, older kernels before commit f369b07c86143
> ("mm/uffd:reset write protection when unregister with wp-mode") won't
> clear the uffd-wp PTE bit. When re-registering uffd-wp, the previous
> uffd-wp PTE bits would trigger again. With above commit,
David Hildenbrand wrote:
> ram_mig_ram_block_resized() will abort migration (including background
> snapshots) when resizing a RAMBlock. ram_block_populate_read() will only
> populate RAM up to used_length, so at least for anonymous memory
> protecting everything between used_length and max_length
David Hildenbrand wrote:
> On 05.01.23 13:45, David Hildenbrand wrote:
>> Playing with background snapshots in combination with hugetlb and
>> virtio-mem, I found two issues and some reasonable optimizations (skip
>> unprotecting when unregistering).
>> With virtio-mem (RamDiscardManager), we now
David Hildenbrand wrote:
> ram_block_populate_read() already optimizes for RamDiscardManager.
> However, ram_write_tracking_start() will still try protecting discarded
> memory ranges.
>
> Let's optimize, because discarded ranges don't map any pages and
>
> (1) For anonymous memory, trying to prot
IGB uses RXDW ICR bit to indicate that rx descriptor has been written
back. This is the same as RXT0 bit in older HW.
Signed-off-by: Sriram Yagnaraman
---
hw/net/e1000x_regs.h | 4
hw/net/igb_core.c| 2 +-
2 files changed, 5 insertions(+), 1 deletion(-)
diff --git a/hw/net/e1000x_regs.
On Thu, Feb 2, 2023 at 2:00 AM Si-Wei Liu wrote:
>
>
>
> On 1/12/2023 9:24 AM, Eugenio Pérez wrote:
> > It's possible to migrate vdpa net devices if they are shadowed from the
> >
> > start. But to always shadow the dataplane is effectively break its host
> >
> > passthrough, so its not convenien
On 30/1/23 11:44, Thomas Huth wrote:
We're currently facing the problem that the gitlab-CI jobs for the
shared runners take too much of the limited CI minutes on gitlab.com.
Here are now some patches that optimize some of the jobs a little bit
to take less runtime. We slightly lose some test cove
Am 02.02.2023 um 11:19 hat Fiona Ebner geschrieben:
> Am 31.01.23 um 19:18 schrieb Denis V. Lunev:
> > Frankly speaking I would say that this switch could be considered
> > NOT QEMU job and we should just send a notification (event) for the
> > completion of the each iteration and management softwa
On Thu, 2 Feb 2023 at 10:56, Richard Henderson
wrote:
>
> On 2/1/23 23:39, Jonathan Cameron wrote:
> > Not sure - if we can do the handling above then sure we could make that
> > change.
> > I can see there is a path to register the callbacks but I'd kind of assumed
> > ROM meant read only...
>
>
On Tue, 24 Jan 2023 at 23:21, Richard Henderson
wrote:
>
> Use the macro instead of two explicit string literals.
>
> Signed-off-by: Richard Henderson
> ---
> hw/arm/sbsa-ref.c | 3 ++-
> hw/arm/virt.c | 2 +-
> 2 files changed, 3 insertions(+), 2 deletions(-)
Applied to target-arm.next,
On Thu, 26 Jan 2023 at 23:32, Richard Henderson
wrote:
>
> Conversion to probe_access_full missed applying the page offset.
>
> Cc: qemu-sta...@nongnu.org
> Reported-by: Sid Manning
> Fixes: f3639a64f602 ("target/arm: Use softmmu tlbs for page table walking")
> Signed-off-by: Richard Henderson
>
David Hildenbrand wrote:
> Let's move more code into vmstate_save(), reducing code duplication and
> preparing for reuse of vmstate_save() in qemu_savevm_state_setup(). We
> have to move vmstate_save() to make the compiler happy.
>
> We'll now also trace from qemu_save_device_state(), triggering t
David Hildenbrand wrote:
> ... and store it in the migration state. This is a preparation for
> storing selected vmds's already in qemu_savevm_state_setup().
>
> Reviewed-by: Dr. David Alan Gilbert
> Signed-off-by: David Hildenbrand
Reviewed-by: Juan Quintela
David Hildenbrand wrote:
> For virtio-mem, we want to have the plugged/unplugged state of memory
> blocks available before migrating any actual RAM content, and perform
> sanity checks before touching anything on the destination. This
> information is immutable on the migration source while migrat
David Hildenbrand wrote:
> We'll make use of both next in the context of virtio-mem.
>
> Reviewed-by: Dr. David Alan Gilbert
> Signed-off-by: David Hildenbrand
Reviewed-by: Juan Quintela
David Hildenbrand wrote:
> Let's factor out this check, to be used in virtio-mem context next.
>
> While at it, fix a spelling error in a related comment.
>
> Signed-off-by: David Hildenbrand
Reviewed-by: Juan Quintela
David Hildenbrand wrote:
> "prealloc=on" for the memory backend does not work as expected, as
> virtio-mem will simply discard all preallocated memory immediately again.
> In the best case, it's an expensive NOP. In the worst case, it's an
> unexpected allocation error.
>
> Instead, "prealloc=on"
David Hildenbrand wrote:
> The bitmap and the size are immutable while migration is active: see
> virtio_mem_is_busy(). We can migrate this information early, before
> migrating any actual RAM content. Further, all information we need for
> sanity checks is immutable as well.
>
> Having this infor
David Hildenbrand wrote:
> Ordinary memory preallocation runs when QEMU starts up and creates the
> memory backends, before processing the incoming migration stream. With
> virtio-mem, we don't know which memory blocks to preallocate before
> migration started. Now that we migrate the virtio-mem b
On Wed, 2023-02-01 at 14:51 -1000, Richard Henderson wrote:
> The linux kernel's trap tables vector all unassigned trap
> numbers to BAD_TRAP, which then raises SIGILL.
>
> Reported-by: Ilya Leoshkevich
> Signed-off-by: Richard Henderson
> ---
> linux-user/sparc/cpu_loop.c | 8
> 1 fil
Hi,
while resolving [1], I noticed a few more bugs in DEXTR and LD_BU_PREINC which
this patch series fixes.
I also included the solo patch [2] into this series.
For v2 I added testcases in tests/tcg/tricore that exercise the errors
that these patches fix.
Cheers,
Bastian
[1] https://gitlab.com
DREG_RS2 and DREG_CALC_RESULT were mapped to the same register which
would not trigger https://gitlab.com/qemu-project/qemu/-/issues/653. So
let's make each register unique.
Signed-off-by: Bastian Koppelmann
---
tests/tcg/tricore/Makefile.softmmu-target | 1 +
tests/tcg/tricore/macros.h
we were mixing up the "c" and "d" registers. We used "d" as a
destination register und "c" as the source. According to the TriCore ISA
manual 1.6 vol 2 it is the other way round.
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
Resolves: https://gitlab.com/qemu-project/qemu/-/iss
if cpu_gpr_d[r3] == 0 then we were shifting the lower register to the
right by 32 which is undefined behaviour. In this case the TriCore would
do nothing an just return the higher register cpu_reg_d[r1]. We fixed
that by detecting whether cpu_gpr_d[r3] was zero and cleared the lower
register.
Revi
we were sign extending the result of the load, while the instruction
clearly states that the result should be unsigned.
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
---
target/tricore/translate.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/tric
On 1/20/23 19:14, Fabiano Rosas wrote:
We currently never pass parameters to the avocado process via
Makefile. To start doing so we need to invert the precedence between
command line parameters and tags, otherwise a command line parameter
would override values for all the tests, which is unlik
Signed-off-by: Bastian Koppelmann
---
tests/tcg/tricore/macros.h | 9 +
tests/tcg/tricore/test_dextr.S | 35 ++
2 files changed, 44 insertions(+)
diff --git a/tests/tcg/tricore/macros.h b/tests/tcg/tricore/macros.h
index 8bc0faf1e4..06bdbf83cb 100644
Signed-off-by: Bastian Koppelmann
---
tests/tcg/tricore/Makefile.softmmu-target | 1 +
tests/tcg/tricore/macros.h| 8 +
tests/tcg/tricore/test_dextr.S| 40 +++
3 files changed, 49 insertions(+)
create mode 100644 tests/tcg/tricore/test_dextr.
we were mixing up the "c" and "d" registers. We used "d" as a
destination register und "c" as the source. According to the TriCore ISA
manual 1.6 vol 2 it is the other way round.
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
Resolves: https://gitlab.com/qemu-project/qemu/-/iss
if we used const16 == 0 we would crash qemu with the error:
../tcg/tcg-op.c:196: tcg_gen_shri_i32: Assertion `arg2 >= 0 && arg2 < 32' failed
This whole instruction can be handled by 'tcg_gen_extract2_tl' which
takes care of this special case as well.
Signed-off-by: Bastian Koppelmann
---
v1 -> v
Signed-off-by: Bastian Koppelmann
---
tests/tcg/tricore/Makefile.softmmu-target | 1 +
tests/tcg/tricore/macros.h| 23 +++
tests/tcg/tricore/test_ld_bu.S| 15 +++
3 files changed, 39 insertions(+)
create mode 100644 tests/tcg/tricore/t
On 1/20/23 19:15, Fabiano Rosas wrote:
Add support for the 'avocado run' "-p" option, which allows us to pass
parameters in the form key=value to be applied to all tests selected
for a given run. This is useful to force generic tests to use a
specific machine, cpu or qemu-binary where otherwis
Signed-off-by: Bastian Koppelmann
---
tests/tcg/tricore/Makefile.softmmu-target | 1 +
tests/tcg/tricore/macros.h| 7 +++
tests/tcg/tricore/test_imask.S| 10 ++
3 files changed, 18 insertions(+)
create mode 100644 tests/tcg/tricore/test_imask.S
diff --g
Hi,
over the years we've got 1-2 dozen reports[0] about suddenly
missing/corrupted MBR/partition tables. The issue seems to be very rare
and there was no success in trying to reproduce it yet. I'm asking here
in the hope that somebody has seen something similar.
The only commonality seems to be th
"manish.mishra" wrote:
> MSG_PEEK peeks at the channel, The data is treated as unread and
> the next read shall still return this data. This support is
> currently added only for socket class. Extra parameter 'flags'
> is added to io_readv calls to pass extra read flags like MSG_PEEK.
>
> Reviewed
On Thu, Feb 02, 2023 at 01:22:12PM +0100, Juan Quintela wrote:
> "manish.mishra" wrote:
> > MSG_PEEK peeks at the channel, The data is treated as unread and
> > the next read shall still return this data. This support is
> > currently added only for socket class. Extra parameter 'flags'
> > is add
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