Hi,
On 1/25/23 00:20, Richard Henderson wrote:
> Use the macro instead of two explicit string literals.
>
> Signed-off-by: Richard Henderson
Reviewed-by: Eric Auger
Thanks
Eric
> ---
> hw/arm/sbsa-ref.c | 3 ++-
> hw/arm/virt.c | 2 +-
> 2 files changed, 3 insertions(+), 2 deletions(-)
>
Richard Henderson writes:
> Implement the function for arm, i386, and s390x, which will use it.
> Add stubs for all other backends.
>
> Reviewed-by: Daniel Henrique Barboza
> Signed-off-by: Richard Henderson
Reviewed-by: Alex Bennée
--
Alex Bennée
Virtualisation Tech Lead @ Linaro
This introduces new properties to allow the user to set the satp mode,
see patch 3 for full syntax. In addition, it prevents cpus to boot in a
satp mode they do not support (see patch 5).
v7:
- Expand map to contain all valid modes, Andrew
- Fix commit log for patch 3, Andrew
- Remove is_32_bit ar
One can extract the DeviceState pointer from the Object pointer, so pass
the Object for future commits to access other fields of Object.
No functional changes intended.
Signed-off-by: Alexandre Ghiti
Reviewed-by: Alistair Francis
Reviewed-by: Frank Chang
Reviewed-by: Andrew Jones
---
target/
This array is actually used as a boolean so swap its current char type
to a boolean and at the same time, change the type of validate_vm to
bool since it returns valid_vm_1_10_[32|64].
Suggested-by: Andrew Jones
Signed-off-by: Alexandre Ghiti
Reviewed-by: Andrew Jones
Reviewed-by: Alistair Fran
RISC-V specifies multiple sizes for addressable memory and Linux probes for
the machine's support at startup via the satp CSR register (done in
csr.c:validate_vm).
As per the specification, sv64 must support sv57, which in turn must
support sv48...etc. So we can restrict machine support by simply
xen-mapcache.c contains common functions which can be used for enabling Xen on
aarch64 with IOREQ handling. Moving it out from hw/i386/xen to hw/xen to make it
accessible for both aarch64 and x86.
Signed-off-by: Vikram Garhwal
Signed-off-by: Stefano Stabellini
---
hw/i386/meson.build
From: Stefano Stabellini
This is done to prepare for enabling xenpv support for ARM architecture.
On ARM it is possible to have a functioning xenpv machine with only the
PV backends and no IOREQ server. If the IOREQ server creation fails,
continue to the PV backends initialization.
Signed-off-by
From: Stefano Stabellini
have_xen_pci_passthrough is only used for Xen x86 VMs.
Signed-off-by: Stefano Stabellini
Reviewed-by: Alex Bennée
---
meson.build | 2 ++
1 file changed, 2 insertions(+)
diff --git a/meson.build b/meson.build
index 6d3b665629..693802adb2 100644
--- a/meson.build
+++
Currently, the max satp mode is set with the only constraint that it must be
implemented in qemu, i.e. set in valid_vm_1_10_[32|64].
But we actually need to add another level of constraint: what the hw is
actually capable of, because currently, a linux booting on a sifive-u54
boots in sv57 mode wh
In preparation to moving most of xen-hvm code to an arch-neutral location,
move non IOREQ references to:
- xen_get_vmport_regs_pfn
- xen_suspend_notifier
- xen_wakeup_notifier
- xen_ram_init
towards the end of the xen_hvm_init_pc() function.
This is done to keep the common ioreq functions in one
In order to use virtio backends we need to make sure that Xen accelerator
is enabled (xen_enabled() returns true) as the memory/cache systems
check for xen_enabled() to perform specific actions. Without that
the xen-mapcache (which is needed for mapping guest memory) is not in use.
Also drop extra
From: Stefano Stabellini
On ARM it is possible to have a functioning xenpv machine with only the
PV backends and no IOREQ server. If the IOREQ server creation fails continue
to the PV backends initialization.
Also, moved the IOREQ registration and mapping subroutine to new function
xen_do_ioreq_
Add a new machine xenpvh which creates a IOREQ server to register/connect with
Xen Hypervisor.
Optional: When CONFIG_TPM is enabled, it also creates a tpm-tis-device, adds a
TPM emulator and connects to swtpm running on host machine via chardev socket
and support TPM functionalities for a guest do
Replace g_malloc with g_new and perror with error_setg_errno.
Signed-off-by: Vikram Garhwal
---
hw/xen/xen-hvm-common.c | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/hw/xen/xen-hvm-common.c b/hw/xen/xen-hvm-common.c
index 94dbbe97ed..01c8ec1956 100644
--- a/hw/
From: Stefano Stabellini
This patch does following:
1. creates arch_handle_ioreq() and arch_xen_set_memory(). This is done in
preparation for moving most of xen-hvm code to an arch-neutral location,
move the x86-specific portion of xen_set_memory to arch_xen_set_memory.
Also, move han
From: Stefano Stabellini
In preparation to moving most of xen-hvm code to an arch-neutral location, move:
- shared_vmport_page
- log_for_dirtybit
- dirty_bitmap
- suspend
- wakeup
out of XenIOState struct as these are only used on x86, especially the ones
related to dirty logging.
Updated XenIOS
The 'mmu-type' should reflect what the hardware is capable of so use the
new satp_mode field in RISCVCPUConfig to do that.
Signed-off-by: Alexandre Ghiti
Reviewed-by: Andrew Jones
Reviewed-by: Alistair Francis
---
hw/riscv/virt.c | 19 ++-
1 file changed, 10 insertions(+), 9 de
Add CONFIG_XEN for aarch64 device to support build for ARM targets.
Signed-off-by: Vikram Garhwal
Signed-off-by: Stefano Stabellini
Reviewed-by: Alex Bennée
---
meson.build | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/meson.build b/meson.build
index 693802adb2..13c4ad101
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
Hi,
This series add xenpvh machine for aarch64. Motivation behind creating xenpvh
machine with IOREQ and TPM was to enable each guest on Xen aarch64 to have it's
own unique and emulated TPM.
This series does
In preparation to moving most of xen-hvm code to an arch-neutral location,
move non IOREQ references to:
- xen_get_vmport_regs_pfn
- xen_suspend_notifier
- xen_wakeup_notifier
- xen_ram_init
towards the end of the xen_hvm_init_pc() function.
This is done to keep the common ioreq functions in one
From: Stefano Stabellini
On ARM it is possible to have a functioning xenpv machine with only the
PV backends and no IOREQ server. If the IOREQ server creation fails continue
to the PV backends initialization.
Also, moved the IOREQ registration and mapping subroutine to new function
xen_do_ioreq_
xen-mapcache.c contains common functions which can be used for enabling Xen on
aarch64 with IOREQ handling. Moving it out from hw/i386/xen to hw/xen to make it
accessible for both aarch64 and x86.
Signed-off-by: Vikram Garhwal
Signed-off-by: Stefano Stabellini
---
hw/i386/meson.build
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
Hi,
This series add xenpvh machine for aarch64. Motivation behind creating xenpvh
machine with IOREQ and TPM was to enable each guest on Xen aarch64 to have it's
own unique and emulated TPM.
This series does
From: Stefano Stabellini
have_xen_pci_passthrough is only used for Xen x86 VMs.
Signed-off-by: Stefano Stabellini
Reviewed-by: Alex Bennée
---
meson.build | 2 ++
1 file changed, 2 insertions(+)
diff --git a/meson.build b/meson.build
index 6d3b665629..693802adb2 100644
--- a/meson.build
+++
From: Stefano Stabellini
In preparation to moving most of xen-hvm code to an arch-neutral location, move:
- shared_vmport_page
- log_for_dirtybit
- dirty_bitmap
- suspend
- wakeup
out of XenIOState struct as these are only used on x86, especially the ones
related to dirty logging.
Updated XenIOS
From: Stefano Stabellini
This is done to prepare for enabling xenpv support for ARM architecture.
On ARM it is possible to have a functioning xenpv machine with only the
PV backends and no IOREQ server. If the IOREQ server creation fails,
continue to the PV backends initialization.
Signed-off-by
Replace g_malloc with g_new and perror with error_setg_errno.
Signed-off-by: Vikram Garhwal
---
hw/xen/xen-hvm-common.c | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/hw/xen/xen-hvm-common.c b/hw/xen/xen-hvm-common.c
index 94dbbe97ed..01c8ec1956 100644
--- a/hw/
Add CONFIG_XEN for aarch64 device to support build for ARM targets.
Signed-off-by: Vikram Garhwal
Signed-off-by: Stefano Stabellini
Reviewed-by: Alex Bennée
---
meson.build | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/meson.build b/meson.build
index 693802adb2..13c4ad101
Add a new machine xenpvh which creates a IOREQ server to register/connect with
Xen Hypervisor.
Optional: When CONFIG_TPM is enabled, it also creates a tpm-tis-device, adds a
TPM emulator and connects to swtpm running on host machine via chardev socket
and support TPM functionalities for a guest do
From: Stefano Stabellini
This patch does following:
1. creates arch_handle_ioreq() and arch_xen_set_memory(). This is done in
preparation for moving most of xen-hvm code to an arch-neutral location,
move the x86-specific portion of xen_set_memory to arch_xen_set_memory.
Also, move han
Le 04/11/2022 à 18:36, Philippe Mathieu-Daudé a écrit :
print_flags() takes a const pointer.
Signed-off-by: Philippe Mathieu-Daudé
---
linux-user/strace.c | 40
1 file changed, 20 insertions(+), 20 deletions(-)
Reviewed-by: Laurent Vivier
* Peter Xu (pet...@redhat.com) wrote:
> On Tue, Jan 24, 2023 at 10:06:48AM +, Dr. David Alan Gilbert wrote:
> > * Peter Xu (pet...@redhat.com) wrote:
> > > Add a helper to do mmap() for a ramblock based on the cached informations.
> > >
> > > A trivial thing to mention is we need to move rambl
Le 04/11/2022 à 18:36, Philippe Mathieu-Daudé a écrit :
From: Drew DeVault
In order to add print_execveat() which re-use common code from
print_execve(), extract print_execve_argv() from it.
Signed-off-by: Drew DeVault
Message-Id: <20221104081015.706009-1-...@cmpwn.com>
[PMD: Split of bigger
Le 04/11/2022 à 18:36, Philippe Mathieu-Daudé a écrit :
From: Drew DeVault
Signed-off-by: Drew DeVault
Message-Id: <20221104081015.706009-1-...@cmpwn.com>
Suggested-by: Helge Deller
[PMD: Split of bigger patch]
Signed-off-by: Philippe Mathieu-Daudé
---
linux-user/strace.c| 23 +
Le 04/11/2022 à 18:36, Philippe Mathieu-Daudé a écrit :
From: Drew DeVault
execve() is a particular case of execveat(). In order
to add do_execveat(), first factor do_execve() out.
Signed-off-by: Drew DeVault
Message-Id: <20221104081015.706009-1-...@cmpwn.com>
[PMD: Split of bigger patch, fil
Le 04/11/2022 à 18:36, Philippe Mathieu-Daudé a écrit :
As I was reviewing this patch from Drew:
https://lore.kernel.org/qemu-devel/20221104081015.706009-1-...@cmpwn.com/
and it was too big for my review standards, I split it into smaller
steps. Since the result can help the other reviewers, post
On Wed Jan 25, 2023 at 10:46 AM CET, Laurent Vivier wrote:
> Applied to my linux-user-for-8.0 branch.
Thanks!
The HAXM project has been retired (see https://github.com/intel/haxm#status),
so we should mark the code in QEMU as deprecated (and finally remove it
unless somebody else picks the project up again - which is quite unlikely
since there are now whpx and hvf on these operating systems, too).
Signed-
On 24/01/2023 20.10, Marc-André Lureau wrote:
Hi
On Tue, Jan 24, 2023 at 7:08 PM Daniel P. Berrangé wrote:
On Tue, Jan 24, 2023 at 03:43:25PM +0100, Thomas Huth wrote:
On 23/01/2023 17.23, Daniel P. Berrangé wrote:
On Fri, Jan 20, 2023 at 05:57:29PM +0400, Marc-André Lureau wrote:
...
On
Il giorno lun 23 gen 2023 alle ore 08:37 Vivek Kasireddy
ha scritto:
>
> Giving users an option to choose a particular codec will enable
> them to make an appropriate decision based on their hardware and
> use-case.
>
> Cc: Gerd Hoffmann
> Cc: Marc-André Lureau
> Cc: Dongwon Kim
> Signed-off-by
On 23/01/2023 13.09, Daniel P. Berrangé wrote:
On Mon, Jan 23, 2023 at 01:05:45PM +0100, Philippe Mathieu-Daudé wrote:
On 23/1/23 12:11, Daniel P. Berrangé wrote:
On Mon, Jan 23, 2023 at 10:20:29AM +0100, Philippe Mathieu-Daudé wrote:
On 23/1/23 09:39, Thomas Huth wrote:
From: Daniel P. Berra
Il giorno mar 24 gen 2023 alle ore 06:41 Kasireddy, Vivek
ha scritto:
>
> + Frediano
>
> Hi Gerd,
>
> >
> > Hi,
> >
> > > Here is the flow of things from the Qemu side:
> > > - Call gl_scanout (to update the fd) and gl_draw_async just like
> > > in the local display case.
> >
> > Ok.
> >
> > >
On 25/1/23 11:20, Thomas Huth wrote:
The HAXM project has been retired (see https://github.com/intel/haxm#status),
so we should mark the code in QEMU as deprecated (and finally remove it
unless somebody else picks the project up again - which is quite unlikely
since there are now whpx and hvf on
hi,
On 24/01/2023 11:27, Thomas Huth wrote:
On 24/01/2023 10.20, Thomas Huth wrote:
[...]
On Thu, Jan 19, 2023 at 12:31 PM Thomas Huth
wrote:
Hi all,
in some spare minutes, I started playing with a patch to try to
remove the
dtc submodule from the QEMU git repository - according to
ht
On Tue, Jan 10, 2023 at 02:32:01AM -0500, Chuck Zmudzinski wrote:
> I call attention to the commit message of the first patch which points
> out that using the "pc" machine and adding the xen platform device on
> the qemu upstream command line is not functionally equivalent to using
> the "xenfv" m
On 25/01/2023 12.36, Nick Hudson wrote:
hi,
On 24/01/2023 11:27, Thomas Huth wrote:
On 24/01/2023 10.20, Thomas Huth wrote:
[...]
On Thu, Jan 19, 2023 at 12:31 PM Thomas Huth wrote:
Hi all,
in some spare minutes, I started playing with a patch to try to
remove the
dtc submodule from
On Wed, Jan 25, 2023 at 09:41:05AM +0100, Alexandre Ghiti wrote:
> RISC-V specifies multiple sizes for addressable memory and Linux probes for
> the machine's support at startup via the satp CSR register (done in
> csr.c:validate_vm).
>
> As per the specification, sv64 must support sv57, which in
On 23/1/23 13:09, Daniel P. Berrangé wrote:
On Mon, Jan 23, 2023 at 01:05:45PM +0100, Philippe Mathieu-Daudé wrote:
On 23/1/23 12:11, Daniel P. Berrangé wrote:
On Mon, Jan 23, 2023 at 10:20:29AM +0100, Philippe Mathieu-Daudé wrote:
On 23/1/23 09:39, Thomas Huth wrote:
From: Daniel P. Berrangé
On Wed, Jan 25, 2023 at 12:06:40PM +0100, Thomas Huth wrote:
> On 23/01/2023 13.09, Daniel P. Berrangé wrote:
> > On Mon, Jan 23, 2023 at 01:05:45PM +0100, Philippe Mathieu-Daudé wrote:
> > > On 23/1/23 12:11, Daniel P. Berrangé wrote:
> > > > On Mon, Jan 23, 2023 at 10:20:29AM +0100, Philippe Math
On Wed, Jan 25, 2023 at 09:41:06AM +0100, Alexandre Ghiti wrote:
> Currently, the max satp mode is set with the only constraint that it must be
> implemented in qemu, i.e. set in valid_vm_1_10_[32|64].
>
> But we actually need to add another level of constraint: what the hw is
> actually capable o
On 25/01/2023 13.09, Daniel P. Berrangé wrote:
On Wed, Jan 25, 2023 at 11:20:53AM +0100, Thomas Huth wrote:
The HAXM project has been retired (see https://github.com/intel/haxm#status),
so we should mark the code in QEMU as deprecated (and finally remove it
unless somebody else picks the project
On Tue, Jan 24, 2023 at 06:00:54PM +, Alex Bennée wrote:
> From: Mark Cave-Ayland
>
> Suggested-by: Mark Cave-Ayland
> Signed-off-by: Alex Bennée
> Reviewed-by: Thomas Huth
> ---
> .gitlab-ci.d/base.yml | 5 +
> 1 file changed, 5 insertions(+)
>
> diff --git a/.gitlab-ci.d/base.yml b
On 24/1/23 19:00, Alex Bennée wrote:
From: Mark Cave-Ayland
Suggested-by: Mark Cave-Ayland
Signed-off-by: Alex Bennée
Reviewed-by: Thomas Huth
---
.gitlab-ci.d/base.yml | 5 +
1 file changed, 5 insertions(+)
Nice!
Reviewed-by: Philippe Mathieu-Daudé
On Wed, Jan 25, 2023 at 12:20:26AM +, Sean Christopherson wrote:
> On Tue, Jan 24, 2023, Liam Merwick wrote:
> > On 14/01/2023 00:37, Sean Christopherson wrote:
> > > On Fri, Dec 02, 2022, Chao Peng wrote:
> > > > This patch series implements KVM guest private memory for confidential
> > > > co
On 25/1/23 08:58, Thomas Huth wrote:
On 24/01/2023 19.01, Alex Bennée wrote:
This affects both system and user mode emulation so we should probably
list it up front.
Acked-by: Richard Henderson
Signed-off-by: Alex Bennée
---
v2
- HPs -> HP's
- MIPs-like -> MIPS-like
---
docs/about/em
Makes the unimplemented region move together with the CCSR address space
if moved by a bootloader. Moving the CCSR address space isn't
implemented yet but this patch is a preparation for it.
Signed-off-by: Bernhard Beschow
---
hw/ppc/e500.c | 10 +++---
1 file changed, 7 insertions(+), 3 del
This is a follow-up on commit 47a0b1dff7e9 'hw/ppc/mpc8544ds: Add
platform bus': Both mpc85xx boards now have a platform bus
unconditionally.
Signed-off-by: Bernhard Beschow
---
hw/ppc/e500.c | 5 ++---
hw/ppc/e500plat.c | 9 +++--
2 files changed, 5 insertions(+), 9 deletions(-)
diff -
The "platform" node is available through data->node, so use that instead
of making assumptions about the parent device.
Signed-off-by: Bernhard Beschow
---
hw/ppc/e500.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/ppc/e500.c b/hw/ppc/e500.c
index 48288c0b41..e3b29d1d97
This series includes some cleanups I came across when working on the ppce500
machine. Furthermore, it enables support for the 'dumpdtb' QMP/HMP command
which was missing so far.
Bernhard Beschow (4):
hw/ppc: Set machine->fdt in e500 machines
hw/ppc/e500{,plat}: Drop redundant checks for presen
This enables support for the 'dumpdtb' QMP/HMP command for all
e500 machines.
Signed-off-by: Bernhard Beschow
---
hw/ppc/e500.c | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/hw/ppc/e500.c b/hw/ppc/e500.c
index 9fa1f8e6cf..7239993acc 100644
--- a/hw/ppc/e500.c
+++ b/hw
On 24/1/23 19:01, Alex Bennée wrote:
The up-coming upgrade to Fedora 37 will bring in libtcmalloc as a
dependency of libglusterfs which confuses our fuzz run. Rather than
disable the build lets use LSAN's suppression mechanism to prevent the
job from failing.
Signed-off-by: Alex Bennée
Cc: Dani
Peter Maydell writes:
> On Tue, 10 Jan 2023 at 16:45, Philippe Mathieu-Daudé
> wrote:
>>
>> Replace the ARMCPU field in DigicState by a reference to
>> an allocated ARMCPU. Instead of initializing the field
>> with object_initialize(), allocate it with object_new().
>>
>> As we don't access A
On Wed, Jan 25, 2023 at 11:20:53AM +0100, Thomas Huth wrote:
> The HAXM project has been retired (see https://github.com/intel/haxm#status),
> so we should mark the code in QEMU as deprecated (and finally remove it
> unless somebody else picks the project up again - which is quite unlikely
> since
On Wed, Jan 25, 2023 at 1:01 PM Andrew Jones wrote:
>
> On Wed, Jan 25, 2023 at 09:41:05AM +0100, Alexandre Ghiti wrote:
> > RISC-V specifies multiple sizes for addressable memory and Linux probes for
> > the machine's support at startup via the satp CSR register (done in
> > csr.c:validate_vm).
>
Le 13/12/2022 à 17:02, Helge Deller a écrit :
Add two missing mmap flags.
Signed-off-by: Helge Deller
diff --git a/linux-user/strace.c b/linux-user/strace.c
index 8fa5c1ec3d..3ea91084fb 100644
--- a/linux-user/strace.c
+++ b/linux-user/strace.c
@@ -1089,6 +1089,8 @@ UNUSED static struct flags
On 24/1/23 19:01, Alex Bennée wrote:
From: Richard Henderson
linux-user blocks all signals while attempting to handle guest
signals (e.g. ABRT), which means that the default TERM sent by timeout
has no effect -- KILL instead.
Signed-off-by: Richard Henderson
Message-Id: <20230117035701.168514
Le 17/12/2022 à 10:31, Michael Tokarev a écrit :
linux-user getgroups(), setgroups(), getgroups32() and setgroups32()
used alloca() to allocate grouplist arrays, with unchecked gidsetsize
coming from the "guest". With NGROUPS_MAX being 65536 (linux, and it
is common for an application to allocat
Le 13/12/2022 à 17:02, Helge Deller a écrit :
Add two missing mmap flags.
Signed-off-by: Helge Deller
diff --git a/linux-user/strace.c b/linux-user/strace.c
index 8fa5c1ec3d..3ea91084fb 100644
--- a/linux-user/strace.c
+++ b/linux-user/strace.c
@@ -1089,6 +1089,8 @@ UNUSED static struct flags
On 24/1/23 19:01, Alex Bennée wrote:
Make it easier to navigate the documentation.
Reviewed-by: Peter Maydell
Acked-by: Richard Henderson
Signed-off-by: Alex Bennée
---
docs/about/index.rst | 16
docs/system/index.rst | 2 ++
docs/tools/index.rst | 2 ++
docs/user/in
Le 24/01/2023 à 21:10, Richard Henderson a écrit :
This reinstates commit 52f0c1607671293afcdb2acc2f83e9bccbfa74bb:
While forcing the CPU to unrealize by hand does trigger the clean-up
code we never fully free resources because refcount never reaches
zero. This is because QOM automatically added
Le 18/01/2023 à 10:01, Mike Frysinger a écrit :
Signed-off-by: Mike Frysinger
Reviewed-by: Philippe Mathieu-Daudé
---
linux-user/strace.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/linux-user/strace.c b/linux-user/strace.c
index 9ae5a812cd71..11a7c3df9498 100644
-
Le 01/01/2023 à 15:11, Letu Ren a écrit :
Currently, qemu strace only prints four protocol contants. This patch
adds others listed in "linux/netlink.h".
Signed-off-by: Letu Ren
---
I found this issue when running networkmanager using qemu-user.
`socket(PF_NETLINK,SOCK_RAW,16) = -1 errno=93 (Pro
Le 10/01/2023 à 18:48, Daniel P. Berrangé a écrit :
It didn't appear that glibc was going to fix the problem
breaking includes of linux/mount.h vs sys/mount.h, so
QEMU applied a workaround copying the symbols/structs we
need into a local header.
Since then Linux modified linux/btrfs.h to pull in
When stracing a program, show up the SIGCHLD value the same
way as it's done when running strace natively, e.g.:
clone(child_stack=0xf7af0040, flags=CLONE_VM|CLONE_VFORK|SIGCHLD, ...
Signed-off-by: Helge Deller
---
linux-user/strace.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/linux-use
Add output for the missing 4th parameter (size_t sigsetsize).
Signed-off-by: Helge Deller
---
linux-user/strace.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/linux-user/strace.c b/linux-user/strace.c
index 3157e4b420..e3aa994678 100644
--- a/linux-user/strace.c
+++ b/li
On 1/25/23 14:57, Helge Deller wrote:
When stracing a program, show up the SIGCHLD value the same
way as it's done when running strace natively, e.g.:
clone(child_stack=0xf7af0040, flags=CLONE_VM|CLONE_VFORK|SIGCHLD, ...
Signed-off-by: Helge Deller
---
linux-user/strace.c | 1 +
1 file chang
* Peter Xu (pet...@redhat.com) wrote:
> Add a RAMBlock.host_mirror for all the hugetlbfs backed guest memories.
> It'll be used to remap the same region twice and it'll be used to service
> page faults using UFFDIO_CONTINUE.
>
> To make sure all accesses to these ranges will generate minor page fa
On Wed, Jan 25, 2023 at 09:24:24AM +, Dr. David Alan Gilbert wrote:
> > > > static void *file_ram_alloc(RAMBlock *block,
> > > > int fd,
> > > > bool truncate,
> > > > off_t offset,
> > > >
On 1/23/2023 17:41, Philippe Mathieu-Daudé wrote:
On 23/1/23 17:23, Peter Maydell wrote:
On Mon, 23 Jan 2023 at 15:21, Philippe Mathieu-Daudé
wrote:
pl011_can_receive() returns the number of bytes that pl011_receive()
can
accept, pl011_can_transmit() returns a boolean.
I was thinking of:
On Wed, Jan 25, 2023 at 01:23:45PM +0100, Alexandre Ghiti wrote:
> On Wed, Jan 25, 2023 at 1:01 PM Andrew Jones wrote:
> >
> > On Wed, Jan 25, 2023 at 09:41:05AM +0100, Alexandre Ghiti wrote:
...
> > > +if (!rv32) {
> > > +for (int i = satp_mode_max - 1; i >= 0; --i) {
> >
> > satp_mod
On 19/01/2023 13.40, Wang, Wenchao wrote:
Hi, Daniel,
Thanks for your reply. Could you please help to merge below attached patch to
update the status of HAXM in QEMU? Thanks a lot.
I can add the patch to my next pull request.
Thanks for your contribution!
Thomas
--
From d88ba9a
On Tuesday, 2023-01-24 at 17:11:59 +01, Eugenio Pérez wrote:
> Since GUEST_ANNOUNCE is emulated the feature bit could be set without
> backend support. This happens in the vDPA case.
>
> However, backend vDPA parent may not have CVQ support. This causes an
> incoherent feature set, and the driver
Changes since RFC: (Thanks to Fan Ni)
- Fix trivial whitespace and long line issues.
Until now, testing using CXL has relied up always using two root ports
below a host bridge, to work around a current assumption in the Linux
kernel support that, in the single root port case, the implementation wi
These two helpers enable host bridges to operate differently depending on
the number of downstream ports, in particular if there is only a single
port.
Useful for CXL where HDM address decoders are allowed to be implicit in
the host bridge if there is only a single root port.
Signed-off-by: Jonat
The CXL r3.0 specification allows for there to be no HDM decoders on CXL
Host Bridges if they have only a single root port. Instead, all accesses
directed to the host bridge (as specified in CXL Fixed Memory Windows)
are assumed to be routed to the single root port.
Linux currently assumes this im
On Wed, Jan 25, 2023 at 4:20 PM David Edmondson
wrote:
>
> On Tuesday, 2023-01-24 at 17:11:59 +01, Eugenio Pérez wrote:
> > Since GUEST_ANNOUNCE is emulated the feature bit could be set without
> > backend support. This happens in the vDPA case.
> >
> > However, backend vDPA parent may not have C
On Sun, 22 Jan 2023 18:07:22 +0100
Bernhard Beschow wrote:
> The PIIX4 datasheet defines the GPSTS register to be at offset 0x0c of the
> power management I/O register block. This register block is represented
> in the device model by the io attribute. So make io_gpe a child memory
> region of io
On Wed, Jan 11, 2023 at 12:34:29PM +, Daniel P. Berrangé wrote:
> On Tue, Jan 10, 2023 at 10:55:36PM -0500, Emilio Cota wrote:
> > qemu-user can hang in a multi-threaded fork. One common
> > reason is that when creating a TB, between fork and exec
> > we manipulate a GTree whose memory allocato
On 25/01/2023 12:53, Kirill A. Shutemov wrote:
On Wed, Jan 25, 2023 at 12:20:26AM +, Sean Christopherson wrote:
On Tue, Jan 24, 2023, Liam Merwick wrote:
On 14/01/2023 00:37, Sean Christopherson wrote:
On Fri, Dec 02, 2022, Chao Peng wrote:
...
When running LTP (https://github.com/linux
On Sun, 22 Jan 2023 18:07:23 +0100
Bernhard Beschow wrote:
> Signed-off-by: Bernhard Beschow
Reviewed-by: Igor Mammedov
> ---
> hw/acpi/core.c | 5 +
> hw/acpi/piix4.c | 3 ---
> hw/acpi/trace-events | 8
> 3 files changed, 9 insertions(+), 7 deletions(-)
>
> diff --
On Sun, 22 Jan 2023 18:07:24 +0100
Bernhard Beschow wrote:
> The bit positions of both registers are related. Tracing the registers
> independently results in the same offsets across these registers which
> eases debugging.
>
> Signed-off-by: Bernhard Beschow
Acked-by: Igor Mammedov
> ---
>
When qemu-keymap is not available on the host, and enable-xkbcommon
is specified, parallel make fails with:
% make clean
...
% make -j 32
...
FAILED: pc-bios/keymaps/is
./qemu-keymap -f pc-bios/keymaps/is -l is
/bin/sh: ./qemu-keymap: No such file or directory
... many similar mess
This introduces new properties to allow the user to set the satp mode,
see patch 3 for full syntax. In addition, it prevents cpus to boot in a
satp mode they do not support (see patch 4).
v8:
- Remove useless !map check, Andrew
- Add RB from Andrew
v7:
- Expand map to contain all valid modes, And
One can extract the DeviceState pointer from the Object pointer, so pass
the Object for future commits to access other fields of Object.
No functional changes intended.
Signed-off-by: Alexandre Ghiti
Reviewed-by: Alistair Francis
Reviewed-by: Frank Chang
Reviewed-by: Andrew Jones
---
target/
This array is actually used as a boolean so swap its current char type
to a boolean and at the same time, change the type of validate_vm to
bool since it returns valid_vm_1_10_[32|64].
Suggested-by: Andrew Jones
Signed-off-by: Alexandre Ghiti
Reviewed-by: Andrew Jones
Reviewed-by: Alistair Fran
RISC-V specifies multiple sizes for addressable memory and Linux probes for
the machine's support at startup via the satp CSR register (done in
csr.c:validate_vm).
As per the specification, sv64 must support sv57, which in turn must
support sv48...etc. So we can restrict machine support by simply
Currently, the max satp mode is set with the only constraint that it must be
implemented in qemu, i.e. set in valid_vm_1_10_[32|64].
But we actually need to add another level of constraint: what the hw is
actually capable of, because currently, a linux booting on a sifive-u54
boots in sv57 mode wh
The 'mmu-type' should reflect what the hardware is capable of so use the
new satp_mode field in RISCVCPUConfig to do that.
Signed-off-by: Alexandre Ghiti
Reviewed-by: Andrew Jones
Reviewed-by: Alistair Francis
---
hw/riscv/virt.c | 19 ++-
1 file changed, 10 insertions(+), 9 de
On Sat, 21 Jan 2023 16:19:39 +0100
Bernhard Beschow wrote:
> This class attribute was always set to pc_madt_cpu_entry().
> pc_madt_cpu_entry() is architecture dependent and was assigned to the
> attribute even in architecture agnostic code such as in hw/acpi/piix4.c
> and hw/isa/lpc_ich9. Not hav
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