[PATCH 03/22] target/arm: Add isar_feature_aa64_rme

Add the missing field for ID_AA64PFR0, and the predicate. Disable it if EL3 is forced off by the board or command-line. Signed-off-by: Richard Henderson --- target/arm/cpu.h | 6 ++ target/arm/cpu.c | 4 2 files changed, 10 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h

[PATCH 02/22] target/arm: Rewrite check_s2_mmu_setup

Integrate neighboring code from get_phys_addr_lpae which computed starting level, as it is easier to validate when doing both at the same time. Mirror the checks at the start of AArch{64,32}.S2Walk, especially S2InvalidESL and S2InconsistentSL. This reverts 49ba115bb74, which was incorrect -- the

[PATCH 12/22] target/arm: NSTable is RES0 for the RME EL3 regime

Test in_space instead of in_secure so that we don't switch out of Root space. Handle the output space change immediately, rather than try and combine the NSTable and NS bits later. Signed-off-by: Richard Henderson --- target/arm/ptw.c | 31 ++- 1 file changed, 14 ins

[PATCH 01/22] target/arm: Fix pmsav8 stage2 secure parameter

We have computed the security state for the stage2 lookup into s2walk_secure -- use it. Fixes: fca45e3467f ("target/arm: Add PMSAv8r functionality") Signed-off-by: Richard Henderson --- target/arm/ptw.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/arm/ptw.c b/target

[PATCH 16/22] target/arm: Move s1_is_El0 into S1Translate

Instead of passing this to get_phys_addr_lpae, stash it in the S1Translate structure. Signed-off-by: Richard Henderson --- target/arm/ptw.c | 21 +++-- 1 file changed, 7 insertions(+), 14 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 37f5ff220c..eaa47f6b62

[PATCH 05/22] target/arm: SCR_EL3.NS may be RES1

With RME, SEL2 must also be present to support secure state. The NS bit is RES1 if SEL2 is not present. Signed-off-by: Richard Henderson --- target/arm/helper.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/target/arm/helper.c b/target/arm/helper.c index 293f8eda8c..783b675bd1 100644 --

[PATCH 06/22] target/arm: Add RME cpregs

This includes GPCCR, GPTBR, MFAR, the TLB flush insns PAALL, PAALLOS, RPALOS, RPAOS, and the cache flush insn CIPAPA. Signed-off-by: Richard Henderson --- target/arm/cpu.h| 19 target/arm/helper.c | 74 + 2 files changed, 93 insertions

[PATCH 20/22] target/arm: Implement the granule protection check

Place the check at the end of get_phys_addr_with_struct, so that we check all physical results. Signed-off-by: Richard Henderson --- target/arm/ptw.c | 253 +++ 1 file changed, 234 insertions(+), 19 deletions(-) diff --git a/target/arm/ptw.c b/target/

[PATCH 08/22] include/exec/memattrs: Add two bits of space to MemTxAttrs

We will need 2 bits to represent ARMSecurityState. Do not attempt to replace or widen secure, even though it logically overlaps the new field -- there are uses within e.g. hw/block/pflash_cfi01.c, which don't know anything specific about ARM. Signed-off-by: Richard Henderson --- include/exec/me

[RFC PATCH 22/22] hw/arm/virt: Add some memory for Realm Management Monitor

This is arbitrary, but used by the Huawei TF-A test code. Signed-off-by: Richard Henderson --- include/hw/arm/virt.h | 2 ++ hw/arm/virt.c | 43 +++ 2 files changed, 45 insertions(+) diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h inde

[PATCH 07/22] target/arm: Introduce ARMSecuritySpace

Introduce both the enumeration and functions to retrieve the current state, and state outside of EL3. Signed-off-by: Richard Henderson --- target/arm/cpu.h| 87 +++-- target/arm/helper.c | 46 2 files changed, 115 insertions(+)

[PATCH 17/22] target/arm: Use get_phys_addr_with_struct for stage2

This fixes a bug in which we failed to initialize the result attributes properly after the memset. Signed-off-by: Richard Henderson --- target/arm/ptw.c | 13 + 1 file changed, 1 insertion(+), 12 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index eaa47f6b62..3205339

[PATCH 04/22] target/arm: Update SCR and HCR for RME

Define the missing SCR and HCR bits, allow SCR_NSE and {SCR,HCR}_GPF to be set, and invalidate TLBs when NSE changes. Signed-off-by: Richard Henderson --- target/arm/cpu.h| 5 +++-- target/arm/helper.c | 10 -- 2 files changed, 11 insertions(+), 4 deletions(-) diff --git a/target/a

[PATCH 19/22] target/arm: Implement GPC exceptions

Handle GPC Fault types in arm_deliver_fault, reporting as either a GPC exception at EL3, or falling through to insn or data aborts at various exception levels. Signed-off-by: Richard Henderson --- target/arm/cpu.h| 1 + target/arm/internals.h | 27 target/arm/helper.c

[PATCH 15/22] target/arm: Use get_phys_addr_with_struct in S1_ptw_translate

Do not provide a fast-path for physical addresses, as those will need to be validated for GPC. Signed-off-by: Richard Henderson --- target/arm/ptw.c | 35 ++- 1 file changed, 14 insertions(+), 21 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index

[PATCH 14/22] target/arm: Handle no-execute for Realm and Root regimes

While Root and Realm may read and write data from other spaces, neither may execute from other pa spaces. This happens for Stage1 EL3, EL2, EL2&0, but stage2 EL1&0. Signed-off-by: Richard Henderson --- target/arm/ptw.c | 66 ++-- 1 file changed, 58 in

[PATCH 18/22] target/arm: Add GPC syndrome

The function takes the fields as filled in by the Arm ARM pseudocode for TakeGPCException. Signed-off-by: Richard Henderson --- target/arm/syndrome.h | 9 + 1 file changed, 9 insertions(+) diff --git a/target/arm/syndrome.h b/target/arm/syndrome.h index 73df5e3793..3fa926d115 100644 ---

[PATCH 21/22] target/arm: Enable RME for -cpu max

Add a cpu property to set GPCCR_EL3.L0GPTSZ, for testing various possible configurations. Signed-off-by: Richard Henderson --- target/arm/cpu64.c | 37 + 1 file changed, 37 insertions(+) diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 0e021960fb..b

Re: [PATCH v3 4/4] target/riscv: Ensure opcode is saved for all relevant instructions

On Fri, Jan 20, 2023 at 11:01 PM Anup Patel wrote: > > We should call decode_save_opc() for all relevant instructions which > can potentially generate a virtual instruction fault or a guest page > fault because generating transformed instruction upon guest page fault > expects opcode to be availab

Re: [PATCH v6 2/5] riscv: Change type of valid_vm_1_10_[32|64] to bool

On Mon, Jan 23, 2023 at 7:06 PM Alexandre Ghiti wrote: > > This array is actually used as a boolean so swap its current char type > to a boolean and at the same time, change the type of validate_vm to > bool since it returns valid_vm_1_10_[32|64]. > > Signed-off-by: Alexandre Ghiti Reviewed-by:

[PATCH 13/22] target/arm: Handle Block and Page bits for security space

With Realm security state, bit 55 of a block or page descriptor during the stage2 walk becomes the NS bit; during the stage1 walk the bit 5 NS bit is RES0. With Root security state, bit 11 of the block or page descriptor during the stage1 walk becomes the NSE bit. Rather than collecting an NS bit

[PATCH 11/22] target/arm: Pipe ARMSecuritySpace through ptw.c

Add input and output space members to S1Translate. Set and adjust them in S1_ptw_translate, and the various points at which we drop secure state. Initialize the space in get_phys_addr; for now leave get_phys_addr_with_secure considering only secure vs non-secure spaces. Signed-off-by: Richard Hend

[PATCH 09/22] target/arm: Adjust the order of Phys and Stage2 ARMMMUIdx

It will be helpful to have ARMMMUIdx_Phys_* to be in the same relative order as ARMSecuritySpace enumerators. This requires the adjustment to the nstable check. While there, check for being in secure state rather than rely on clearing the low bit making no change to non-secure state. Signed-off-by

[PATCH 10/22] target/arm: Introduce ARMMMUIdx_Phys_{Realm,Root}

With FEAT_RME, there are four physical address spaces. For now, just define the symbols, and mention them in the same spots as the other Phys indexes in ptw.c. Signed-off-by: Richard Henderson --- target/arm/cpu-param.h | 2 +- target/arm/cpu.h | 17 +++-- target/arm/ptw.c

Re: [PATCH v7 3/7] mac_{old,new}world: Pass MacOS VGA NDRV in card ROM instead of fw_cfg

On Mon, 23 Jan 2023, Mark Cave-Ayland wrote: On 22/01/2023 22:16, BALATON Zoltan wrote: The problem you are ultimately trying to solve though is that OpenBIOS is loading the NDRV for all VGA PCI devices, so why not just fix drivers/vga.fs so that the NDRV is loaded only for the QEMU VGA device?

Re: [PATCH 2/2] target/arm: Look up ARMCPRegInfo at runtime

On 1/23/23 02:53, Peter Maydell wrote: On Fri, 6 Jan 2023 at 19:45, Richard Henderson wrote: Do not encode the pointer as a constant in the opcode stream. This pointer is specific to the cpu that first generated the translation, which runs into problems with both hot-pluggable cpus and user-on

Re: [PATCH v3 3/3] python/qemu/machine: use socketpair() for QMP by default

On Wed, Jan 18, 2023 at 3:03 AM Marc-André Lureau wrote: > > Hi > > On Wed, Jan 18, 2023 at 2:36 AM John Snow wrote: > > > > On Wed, Jan 11, 2023 at 3:01 AM wrote: > > > > > > From: Marc-André Lureau > > > > > > When no monitor address is given, establish the QMP communication through > > > a s

Re: [PATCH v6 4/5] riscv: Correctly set the device-tree entry 'mmu-type'

On Mon, Jan 23, 2023 at 7:08 PM Alexandre Ghiti wrote: > > The 'mmu-type' should reflect what the hardware is capable of so use the > new satp_mode field in RISCVCPUConfig to do that. > > Signed-off-by: Alexandre Ghiti Reviewed-by: Alistair Francis Alistair > --- > hw/riscv/virt.c | 19 +

Re: [PATCH v7 4/7] mac_newworld: Add machine types for different mac99 configs

On Mon, 23 Jan 2023, Mark Cave-Ayland wrote: On 22/01/2023 21:48, BALATON Zoltan wrote: On Sun, 22 Jan 2023, Mark Cave-Ayland wrote: On 11/01/2023 00:36, BALATON Zoltan wrote: On Tue, 10 Jan 2023, Mark Cave-Ayland wrote: On 04/01/2023 21:59, BALATON Zoltan wrote: Secondly it's not clear to me

Re: [PATCH v6 5/5] riscv: Introduce satp mode hw capabilities

On Mon, Jan 23, 2023 at 7:09 PM Alexandre Ghiti wrote: > > Currently, the max satp mode is set with the only constraint that it must be > implemented in qemu, i.e. set in valid_vm_1_10_[32|64]. > > But we actually need to add another level of constraint: what the hw is > actually capable of, becau

Re: [PATCH v3 0/4] Nested virtualization fixes for QEMU

On Fri, Jan 20, 2023 at 11:01 PM Anup Patel wrote: > > This series mainly includes fixes discovered while developing nested > virtualization running on QEMU. > > These patches can also be found in the riscv_nested_fixes_v3 branch at: > https://github.com/avpatel/qemu.git > > Changes since v2: > -

Re: [PATCH] hw/riscv: boot: Don't use CSRs if they are disabled

On Mon, Jan 23, 2023 at 11:58 AM Alistair Francis wrote: > > From: Alistair Francis > > If the CSRs and CSR instructions are disabled because the Zicsr > extension isn't enabled then we want to make sure we don't run any CSR > instructions in the boot ROM. > > This patches removes the CSR instruc

Re: [PATCH v7 6/7] mac_newworld: Deprecate mac99 "via" option

On Mon, 23 Jan 2023, Mark Cave-Ayland wrote: On 22/01/2023 22:07, BALATON Zoltan wrote: On Sun, 22 Jan 2023, Mark Cave-Ayland wrote: On 12/01/2023 23:51, BALATON Zoltan wrote: On Thu, 12 Jan 2023, Howard Spoelstra wrote: On Wed, Jan 11, 2023 at 1:15 AM BALATON Zoltan wrote: On Tue, 10 Jan 2

Re: [PATCH v10 0/9] KVM: mm: fd-based approach for supporting KVM

On Thu, Jan 19, 2023, Isaku Yamahata wrote: > On Thu, Jan 19, 2023 at 03:25:08PM +, > Sean Christopherson wrote: > > > On Thu, Jan 19, 2023, Isaku Yamahata wrote: > > > On Sat, Jan 14, 2023 at 12:37:59AM +, > > > Sean Christopherson wrote: > > > > > > > On Fri, Dec 02, 2022, Chao Peng w

Re: [PATCH] hw/riscv: boot: Don't use CSRs if they are disabled

On Tue, Jan 24, 2023 at 11:24 AM Bin Meng wrote: > > On Mon, Jan 23, 2023 at 11:58 AM Alistair Francis > wrote: > > > > From: Alistair Francis > > > > If the CSRs and CSR instructions are disabled because the Zicsr > > extension isn't enabled then we want to make sure we don't run any CSR > > in

Re: [PATCH] vhost-user-fs: add capability to allow migration

On Mon, 23 Jan 2023 at 14:54, Stefan Hajnoczi wrote: > > On Mon, Jan 23, 2023 at 06:27:23PM +, Dr. David Alan Gilbert wrote: > > * Michael S. Tsirkin (m...@redhat.com) wrote: > > > On Sun, Jan 22, 2023 at 06:09:40PM +0200, Anton Kuchin wrote: > > > > > > > > On 22/01/2023 16:46, Michael S. Tsi

Re: [PATCH v7 6/7] mac_newworld: Deprecate mac99 "via" option

On Tue, 24 Jan 2023, Howard Spoelstra wrote: From a Mac OS guest perspective, via=cuda is needed for Mac OS 9.0.4 due to the 2 usb devices (mouse/kbd) issue. And for 10.0/10.1 (my guess would be that these suffer the same usb issue) The real powermac3,1 AGP has no adb. And do these OSes run on

Re: [PATCH] hw/riscv: boot: Don't use CSRs if they are disabled

> From: Alistair Francis > > If the CSRs and CSR instructions are disabled because the Zicsr > extension isn't enabled then we want to make sure we don't run any CSR > instructions in the boot ROM. > > This patches removes the CSR instructions from the reset-vec if the > extension isn't enabled.

[PULL v2 13/15] tcg/loongarch64: Implement movcond

Reviewed-by: WANG Xuerui Signed-off-by: Richard Henderson --- tcg/loongarch64/tcg-target-con-set.h | 1 + tcg/loongarch64/tcg-target.h | 4 ++-- tcg/loongarch64/tcg-target.c.inc | 33 3 files changed, 36 insertions(+), 2 deletions(-) diff --git a/tcg/l

[PULL v2 07/15] target/loongarch: Disassemble jirl properly

While jirl shares the same instruction format as bne etc, it is not assembled the same. In particular, rd is printed first not second and the immediate is not pc-relative. Decode into the arg_rr_i structure, which prints correctly. This changes the "offs" member to "imm", to update translate. Re

[PULL v2 06/15] target/loongarch: Enable the disassembler for host tcg

Reuse the decodetree based disassembler from target/loongarch/ for tcg/loongarch64/. The generation of decode-insns.c.inc into ./libcommon.fa.p/ could eventually result in conflict, if any other host requires the same trick, but this is good enough for now. Reviewed-by: WANG Xuerui Reviewed-by:

[PULL v2 01/15] tcg: Avoid recursion in tcg_gen_mulu2_i32

We have a test for one of TCG_TARGET_HAS_mulu2_i32 or TCG_TARGET_HAS_muluh_i32 being defined, but the test became non-functional when we changed to always define all of these macros. Replace this with a build-time test in tcg_gen_mulu2_i32. Fixes: 25c4d9cc845 ("tcg: Always define all of the TCGOp

[PULL v2 05/15] tcg: Mark tcg helpers noinline to avoid an issue with LTO

Marking helpers __attribute__((noinline)) prevents an issue with GCC's ipa-split pass under --enable-lto. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1454 Reviewed-by: Philippe Mathieu-Daudé Tested-by: Idan Horowitz Signed-off-by: Richard Henderson --- include/exec/helper-proto.h |

[PULL v2 12/15] tcg/loongarch64: Improve setcond expansion

Split out a helper function, tcg_out_setcond_int, which does not always produce the complete boolean result, but returns a set of flags to do so. Accept all int32_t as constant input, so that LE/GT can adjust the constant to LT. Reviewed-by: WANG Xuerui Signed-off-by: Richard Henderson --- tcg

[PULL v2 08/15] target/loongarch: Disassemble pcadd* addresses

Print both the raw field and the resolved pc-relative address, as we do for branches. Reviewed-by: WANG Xuerui Signed-off-by: Richard Henderson --- target/loongarch/disas.c | 37 + 1 file changed, 33 insertions(+), 4 deletions(-) diff --git a/target/loongarc

[PULL v2 14/15] tcg/loongarch64: Use tcg_pcrel_diff in tcg_out_ldst

Take the w^x split into account when computing the pc-relative distance to an absolute pointer. Reviewed-by: WANG Xuerui Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- tcg/loongarch64/tcg-target.c.inc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a

[PULL v2 02/15] tcg/arm: Use register pair allocation for qemu_{ld, st}_i64

Although we still can't use ldrd and strd for all operations, increase the chances by getting the register allocation correct. Signed-off-by: Richard Henderson --- tcg/arm/tcg-target-con-set.h | 7 --- tcg/arm/tcg-target-con-str.h | 2 ++ tcg/arm/tcg-target.c.inc | 28 +

[PULL v2 04/15] linux-user: Implment host/ppc/host-signal.h

This commit re-enables ppc32 as a linux-user host, as existance of the directory is noted by configure. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1097 Signed-off-by: Richard Henderson Reviewed-by: Daniel Henrique Barboza Message-Id: <20220729172141.1789105-3-richard.hender...@linar

[PULL v2 15/15] tcg/loongarch64: Reorg goto_tb implementation

The old implementation replaces two insns, swapping between b nop and pcaddu18i tmp, jirl zero, tmp, & 0x There is a race condition in which a thread could be stopped at the jirl, i.e. with the top of the address loaded, and when restarted we have

[PULL v2 00/15] tcg patch queue

Second try's the charm today, right? r~ The following changes since commit 00b1faea41d283e931256aa78aa975a369ec3ae6: Merge tag 'pull-target-arm-20230123' of https://git.linaro.org/people/pmaydell/qemu-arm into staging (2023-01-23 13:40:28 +) are available in the Gi

[PULL v2 03/15] common-user/host/ppc: Implement safe-syscall.inc.S

Signed-off-by: Richard Henderson Reviewed-by: Daniel Henrique Barboza Message-Id: <20220729172141.1789105-2-richard.hender...@linaro.org> --- common-user/host/ppc/safe-syscall.inc.S | 107 1 file changed, 107 insertions(+) create mode 100644 common-user/host/ppc/safe-sy

[PULL v2 11/15] tcg/loongarch64: Introduce tcg_out_addi

Adjust the constraints to allow any int32_t for immediate addition. Split immediate adds into addu16i + addi, which covers quite a lot of the immediate space. For the hole in the middle, load the constant into TMP0 instead. Reviewed-by: WANG Xuerui Signed-off-by: Richard Henderson --- tcg/loo

[PULL v2 10/15] tcg/loongarch64: Update tcg-insn-defs.c.inc

Regenerate with ADDU16I included: $ cd loongarch-opcodes/scripts/go $ go run ./genqemutcgdefs > $QEMU/tcg/loongarch64/tcg-insn-defs.c.inc Reviewed-by: WANG Xuerui Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- tcg/loongarch64/tcg-insn-defs.c.inc | 10 +-

[PULL v2 09/15] tcg/loongarch64: Optimize immediate loading

From: Rui Wang diff: Imm Before After addi.w rd, zero, 0 addi.w rd, zero, 0 lu52i.d rd, zero, 0 f800lu12i.w rd, -1 addi.w rd, zero, -2048 ori rd, rd, 2048

Re: [PATCH 5/6] hw/mips/gt64xxx_pci: Endian-swap using PCI_HOST_BRIDGE MemoryRegionOps

0e81299554/images/mips Cheers, Nathan # bad: [00b1faea41d283e931256aa78aa975a369ec3ae6] Merge tag 'pull-target-arm-20230123' of https://git.linaro.org/people/pmaydell/qemu-arm into staging # good: [886fb67020e32ce6a2cf7049c6f017acf1f0d69a] Merge tag 'pull-target-arm-20230113' of https:/

[PATCH] po/meson: make i18n module optional

This is necessary for Muon build system compatibility and prevents the following error: meson.build:4:8: error module 'i18n' is unimplemented, If you would like to make your build files portable to muon, use `import('i18n', required: false)`, and then check the .found() method before use.

[PATCH v2 14/26] e1000e: Configure ResettableClass

This is part of recent efforts of refactoring e1000 and e1000e. DeviceClass's reset member is deprecated so migrate to ResettableClass. There is no behavioral difference. Signed-off-by: Akihiko Odaki Reviewed-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé --- hw/net/e1000e.c | 10 +

[PATCH v2 16/26] e1000e: Set MII_ANER_NWAY

This keeps Windows driver 12.18.9.23 from generating an event with ID 30. The description of the event is as follows: > Intel(R) 82574L Gigabit Network Connection > PROBLEM: The network adapter is configured for auto-negotiation but > the link partner is not. This may result in a duplex mismatch.

[PATCH v2 02/26] hw/net: Add more MII definitions

The definitions will be used by igb. Signed-off-by: Akihiko Odaki --- include/hw/net/mii.h | 13 - 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/include/hw/net/mii.h b/include/hw/net/mii.h index 4ae4dcce7e..c6a767a49a 100644 --- a/include/hw/net/mii.h +++ b/include/hw

[PATCH v2 18/26] net: Check L4 header size

net_tx_pkt_build_vheader() inspects TCP header but had no check for the header size, resulting in an undefined behavior. Check the header size and drop the packet if the header is too small. Signed-off-by: Akihiko Odaki --- hw/net/e1000e_core.c | 19 ++- hw/net/net_tx_pkt.c | 13

[PATCH v2 00/26] e1000x cleanups (preliminary for IGB)

We are adding a new device named igb, yet another Intel NIC. As the new implementation derives from e1000e, overhaul e1000e implementation first. e1000 has many commonalities with e1000e so we also apply the corresponding changes to the device if possible. This was spun off from: https://patchew.o

[PATCH v2 03/26] fsl_etsec: Use hw/net/mii.h

hw/net/mii.h provides common definitions for MII. Signed-off-by: Akihiko Odaki Reviewed-by: Philippe Mathieu-Daudé --- hw/net/fsl_etsec/etsec.c | 11 ++- hw/net/fsl_etsec/etsec.h | 17 - hw/net/fsl_etsec/miim.c | 5 +++-- include/hw/net/mii.h | 1 + 4 files change

[PATCH v2 10/26] e1000e: Use memcpy to intialize registers

Use memcpy instead of memmove to initialize registers. The initial register templates and register table instances will never overlap. Signed-off-by: Akihiko Odaki --- hw/net/e1000e_core.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/hw/net/e1000e_core.c b/hw/net/e1000

[PATCH v2 12/26] e1000e: Improve software reset

This change makes e1000e reset more things when software reset was triggered. Some registers are exempted from software reset in the datasheet and this change also implements the behavior accordingly. Signed-off-by: Akihiko Odaki --- hw/net/e1000e_core.c | 24 +++- 1 file cha

[PATCH v2 17/26] e1000e: Remove extra pointer indirection

e1000e_write_packet_to_guest() passes the reference of variable ba as a pointer to an array, and that pointer indirection is just unnecessary; all functions which uses the passed reference performs no pointer operation on the pointer and they simply dereference the passed pointer. Remove the extra

[PATCH v2 09/26] e1000: Use memcpy to intialize registers

Use memcpy instead of memmove to initialize registers. The initial register templates and register table instances will never overlap. Signed-off-by: Akihiko Odaki --- hw/net/e1000.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/hw/net/e1000.c b/hw/net/e1000.c index d9d

[PATCH v2 11/26] e1000e: Remove pending interrupt flags

They are duplicate of running throttling timer flags and incomplete as the flags are not cleared when the interrupts are fired or the device is reset. Signed-off-by: Akihiko Odaki --- hw/net/e1000e.c | 5 ++--- hw/net/e1000e_core.c | 19 +++ hw/net/e1000e_core.h | 2 -- hw

[PATCH v2 05/26] e1000: Mask registers when writing

When a register has effective bits fewer than their width, the old code inconsistently masked when writing or reading. Make the code consistent by always masking when writing, and remove some code duplication. Signed-off-by: Akihiko Odaki --- hw/net/e1000.c | 84 +++--

[PATCH v2 24/26] hw/net/net_tx_pkt: Implement TCP segmentation

There was no proper implementation of TCP segmentation before this change, and net_tx_pkt relied solely on IPv4 fragmentation. Not only this is not aligned with the specification, but it also resulted in corrupted IPv6 packets. This is particularly problematic for the igb, a new proposed device im

[PATCH v2 23/26] e1000e: Perform software segmentation for loopback

e1000e didn't perform software segmentation for loopback if virtio-net header is enabled, which is wrong. To fix the problem, introduce net_tx_pkt_send_custom(), which allows the caller to specify whether offloading should be assumed or not. net_tx_pkt_send_custom() also allows the caller to prov

[PATCH v2 06/26] e1000e: Mask registers when writing

When a register has effective bits fewer than their width, the old code inconsistently masked when writing or reading. Make the code consistent by always masking when writing, and remove some code duplication. Signed-off-by: Akihiko Odaki --- hw/net/e1000e_core.c | 94 +++

[PATCH v2 22/26] hw/net/net_rx_pkt: Remove net_rx_pkt_has_virt_hdr

When virtio-net header is not set, net_rx_pkt_get_vhdr() returns zero-filled virtio_net_hdr, which is actually valid. In fact, tap device uses zero-filled virtio_net_hdr when virtio-net header is not provided by the peer. Therefore, we can just remove net_rx_pkt_has_virt_hdr() and always assume Net

[PATCH v2 26/26] MAINTAINERS: Add e1000e test files

Signed-off-by: Akihiko Odaki --- MAINTAINERS | 2 ++ 1 file changed, 2 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 958915f227..3b648a89d7 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2218,6 +2218,8 @@ R: Akihiko Odaki S: Maintained F: hw/net/e1000e* F: tests/qtest/fuzz-e1000

[PATCH v2 20/26] net: Strip virtio-net header when dumping

filter-dump specifiees Ethernet as PCAP LinkType, which does not expect virtio-net header. Having virtio-net header in such PCAP file breaks PCAP unconsumable. Unfortunately currently there is no LinkType for virtio-net so for now strip virtio-net header to convert the output to Ethernet. Signed-o

[PATCH v2 01/26] e1000e: Fix the code style

igb implementation first starts off by copying e1000e code. Correct the code style before that. Signed-off-by: Akihiko Odaki Reviewed-by: Philippe Mathieu-Daudé --- hw/net/e1000.c | 41 hw/net/e1000e.c| 72 ++-- hw/net/e1000e_core.c |

[PATCH v2 07/26] e1000: Use more constant definitions

The definitions for E1000_VFTA_ENTRY_SHIFT, E1000_VFTA_ENTRY_MASK, and E1000_VFTA_ENTRY_BIT_SHIFT_MASK were copied from: https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/tree/drivers/net/ethernet/intel/e1000/e1000_hw.h?h=v6.0.9#n306 The definitions for E1000_NUM_UNICAST, E1000_MC_T

[PATCH v2 15/26] e1000e: Introduce e1000_rx_desc_union

Before this change, e1000e_write_packet_to_guest() allocated the receive descriptor buffer as an array of uint8_t. This does not ensure the buffer is sufficiently aligned. Introduce e1000_rx_desc_union type, a union type of all receive descriptor types to correct this. Signed-off-by: Akihiko Odak

[PATCH v2 25/26] MAINTAINERS: Add Akihiko Odaki as a e1000e reviewer

I want to know to be notified when there is a new change for e1000e as e1000e is similar to igb and such a change may also be applicable for igb. Signed-off-by: Akihiko Odaki --- MAINTAINERS | 2 ++ 1 file changed, 2 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 08ad1e5341..958915f

[PATCH v2 04/26] e1000: Use hw/net/mii.h

hw/net/mii.h provides common definitions for MII. Signed-off-by: Akihiko Odaki Reviewed-by: Philippe Mathieu-Daudé --- hw/net/e1000.c | 86 ++-- hw/net/e1000_regs.h| 46 hw/net/e1000e.c| 1 + hw/net/e1000e_core.c | 99 +

[PATCH v2 21/26] hw/net/net_tx_pkt: Automatically determine if virtio-net header is used

The new function qemu_get_using_vnet_hdr() allows to automatically determine if virtio-net header is used. Signed-off-by: Akihiko Odaki --- hw/net/e1000e_core.c | 3 +-- hw/net/net_tx_pkt.c | 19 ++- hw/net/net_tx_pkt.h | 3 +-- hw/net/vmxnet3.c | 6 ++ 4 files chang

[PATCH v2 19/26] e1000x: Alter the signature of e1000x_is_vlan_packet

e1000x_is_vlan_packet() had a pointer to uint8_t as a parameter, but it does not have to be uint8_t. Change the type to void *. Signed-off-by: Akihiko Odaki --- hw/net/e1000x_common.c | 2 +- hw/net/e1000x_common.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/hw/net/e10

[PATCH v2 13/26] e1000: Configure ResettableClass

This is part of recent efforts of refactoring e1000 and e1000e. DeviceClass's reset member is deprecated so migrate to ResettableClass. There is no behavioral difference. Signed-off-by: Akihiko Odaki Reviewed-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé --- hw/net/e1000.c | 13 --

[PATCH v2 08/26] e1000e: Use more constant definitions

The definitions of SW Semaphore Register were copied from: https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/tree/drivers/net/ethernet/intel/e1000e/defines.h?h=v6.0.9#n374 Signed-off-by: Akihiko Odaki --- hw/net/e1000_regs.h | 7 +++ hw/net/e1000e_core.c | 49 +++

[PATCH v3 01/13] hw/net/net_tx_pkt: Introduce net_tx_pkt_get_eth_hdr

Expose the ethernet header so that igb can utilize it to perform the internal routing among its SR-IOV functions. Signed-off-by: Gal Hammer Signed-off-by: Marcel Apfelbaum Signed-off-by: Akihiko Odaki --- hw/net/net_tx_pkt.c | 6 ++ hw/net/net_tx_pkt.h | 8 2 files changed, 14 ins

[PATCH v3 02/13] pcie: Introduce pcie_sriov_num_vfs

igb can use this function to change its behavior depending on the number of virtual functions currently enabled. Signed-off-by: Gal Hammer Signed-off-by: Marcel Apfelbaum Signed-off-by: Akihiko Odaki Reviewed-by: Philippe Mathieu-Daudé --- hw/pci/pcie_sriov.c | 5 + include/hw/pci

[PATCH v3 04/13] igb: Copy e1000e code

Start off igb implementation by copying e1000e code first as igb resembles e1000e. Signed-off-by: Gal Hammer Signed-off-by: Marcel Apfelbaum Signed-off-by: Akihiko Odaki --- MAINTAINERS |5 + hw/net/igb.c| 727 + hw/net/igb_common.h | 102 ++ hw/net/igb_core.c |

[PATCH v3 00/13] Introduce igb

Based-on: <20230124043143.5515-1-akihiko.od...@daynix.com> ([PATCH v2 00/26] e1000x cleanups (preliminary for IGB)) igb is a family of Intel's gigabit ethernet controllers. This series implements 82576 emulation in particular. You can see the last patch for the documentation. Note that there is a

[PATCH v3 05/13] igb: Rename identifiers

Rename identifiers of definitions which will be modified later for igb. This will also allow to build igb along with e1000e. Signed-off-by: Gal Hammer Signed-off-by: Marcel Apfelbaum Signed-off-by: Akihiko Odaki --- hw/net/igb.c| 368 +- hw/net/igb_common.h |6 +- hw/net/i

[PATCH v3 09/13] tests/qtest/libqos/e1000e: Export macreg functions

They will be useful for igb testing. Signed-off-by: Akihiko Odaki --- tests/qtest/libqos/e1000e.c | 12 tests/qtest/libqos/e1000e.h | 12 2 files changed, 12 insertions(+), 12 deletions(-) diff --git a/tests/qtest/libqos/e1000e.c b/tests/qtest/libqos/e1000e.c index 28f

[PATCH v3 11/13] tests/qtest/libqos/igb: Transform to igb tests

Signed-off-by: Akihiko Odaki --- tests/qtest/fuzz/generic_fuzz_configs.h | 5 + tests/qtest/igb-test.c | 67 ++-- tests/qtest/libqos/igb.c| 139 +--- tests/qtest/libqos/meson.build | 1 + tests/qtest/meson.build

[PATCH v3 03/13] e1000: Split header files

Some definitions in the header files are invalid for igb so extract them to new header files to keep igb from referring to them. Signed-off-by: Gal Hammer Signed-off-by: Marcel Apfelbaum Signed-off-by: Akihiko Odaki Reviewed-by: Philippe Mathieu-Daudé --- hw/net/e1000.c | 1 + hw/ne

[PATCH v3 10/13] tests/qtest/libqos/igb: Copy e1000e code

Start off igb test implementation by copying e1000e code first as igb resembles e1000e. Signed-off-by: Akihiko Odaki --- MAINTAINERS | 2 + tests/qtest/igb-test.c | 242 +++ tests/qtest/libqos/igb.c | 226

[PATCH v3 13/13] docs/system/devices/igb: Add igb documentation

Signed-off-by: Akihiko Odaki --- MAINTAINERS | 1 + docs/system/device-emulation.rst | 1 + docs/system/devices/igb.rst | 71 3 files changed, 73 insertions(+) create mode 100644 docs/system/devices/igb.rst diff --git a/MAINTAINERS b/

[PATCH v3 08/13] tests/qtest/e1000e-test: Fabricate ethernet header

e1000e understands ethernet header so fabricate something convincing. Signed-off-by: Akihiko Odaki --- tests/qtest/e1000e-test.c | 17 +++-- tests/qtest/libqos/e1000e.h | 2 ++ 2 files changed, 13 insertions(+), 6 deletions(-) diff --git a/tests/qtest/e1000e-test.c b/tests/qtest/

[PATCH v3 06/13] igb: Build igb

Currently igb functions identically with e1000e. Signed-off-by: Gal Hammer Signed-off-by: Marcel Apfelbaum Signed-off-by: Akihiko Odaki --- hw/net/Kconfig | 5 + hw/net/meson.build | 2 ++ 2 files changed, 7 insertions(+) diff --git a/hw/net/Kconfig b/hw/net/Kconfig index 1cc1c5775e..

[PATCH v3 12/13] tests/avocado: Add igb test

This automates ethtool tests for igb registers, interrupts, etc. Signed-off-by: Akihiko Odaki --- MAINTAINERS | 1 + .../org.centos/stream/8/x86_64/test-avocado | 1 + tests/avocado/igb.py | 38 +++ 3 files changed, 4

Re: [PATCH v2 00/13] Introduce igb

On 2023/01/16 17:01, Jason Wang wrote: On Sat, Jan 14, 2023 at 12:10 PM Akihiko Odaki wrote: Based-on: <20230114035919.35251-1-akihiko.od...@daynix.com> ([PATCH 00/19] e1000x cleanups (preliminary for IGB)) igb is a family of Intel's gigabit ethernet controllers. This series implements 82576

[PATCH] aspeed/sdmc: Drop unnecessary scu include

The model includes aspeed_scu.h but doesn't appear to require it. Signed-off-by: Joel Stanley --- hw/misc/aspeed_sdmc.c | 1 - 1 file changed, 1 deletion(-) diff --git a/hw/misc/aspeed_sdmc.c b/hw/misc/aspeed_sdmc.c index d2a3931033b3..abb272793393 100644 --- a/hw/misc/aspeed_sdmc.c +++ b/hw/mi

RE: [RFC v2 2/2] spice: Add an option to forward the dmabuf directly to the encoder (v2)

+ Frediano Hi Gerd, > > Hi, > > > Here is the flow of things from the Qemu side: > > - Call gl_scanout (to update the fd) and gl_draw_async just like > > in the local display case. > > Ok. > > > - Additionally, create an update with the cmd set to QXL_CMD_DRAW > > to trigger the creatio

Re: [PATCH v2 26/26] MAINTAINERS: Add e1000e test files

On 24/01/2023 05.31, Akihiko Odaki wrote: Signed-off-by: Akihiko Odaki --- MAINTAINERS | 2 ++ 1 file changed, 2 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 958915f227..3b648a89d7 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2218,6 +2218,8 @@ R: Akihiko Odaki S: Maintaine

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