On Fri, Jan 20, 2023 at 07:37:18PM +0200, Anton Kuchin wrote:
> On 20/01/2023 15:58, Michael S. Tsirkin wrote:
> > On Thu, Jan 19, 2023 at 03:45:06PM +0200, Anton Kuchin wrote:
> > > On 19/01/2023 14:51, Michael S. Tsirkin wrote:
> > > > On Sun, Jan 15, 2023 at 07:09:03PM +0200, Anton Kuchin wrote:
On 1/18/23 09:11, Richard Henderson wrote:
Print both the raw field and the resolved pc-relative
address, as we do for branches.
Signed-off-by: Richard Henderson
---
target/loongarch/disas.c | 37 +
1 file changed, 33 insertions(+), 4 deletions(-)
Review
On 1/18/23 09:11, Richard Henderson wrote:
Take the w^x split into account when computing the
pc-relative distance to an absolute pointer.
Signed-off-by: Richard Henderson
---
tcg/loongarch64/tcg-target.c.inc | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/tcg/loongarch64
On 1/18/23 09:11, Richard Henderson wrote:
While jirl shares the same instruction format as bne etc,
it is not assembled the same. In particular, rd is printed
first not second and the immediate is not pc-relative.
Decode into the arg_rr_i structure, which prints correctly.
This changes the "of
On 1/18/23 09:11, Richard Henderson wrote:
From: Rui Wang
diff:
Imm Before After
addi.w rd, zero, 0 addi.w rd, zero, 0
lu52i.d rd, zero, 0
f800lu12i.w rd, -1 addi.w rd, zero, -20
On 1/18/23 09:11, Richard Henderson wrote:
Signed-off-by: Richard Henderson
---
tcg/loongarch64/tcg-target-con-set.h | 1 +
tcg/loongarch64/tcg-target.h | 4 ++--
tcg/loongarch64/tcg-target.c.inc | 33
3 files changed, 36 insertions(+), 2 deletions
On 1/18/23 09:11, Richard Henderson wrote:
Regenerate with ADDU16I included:
$ cd loongarch-opcodes/scripts/go
$ go run ./genqemutcgdefs > $QEMU/tcg/loongarch64/tcg-insn-defs.c.inc
Signed-off-by: Richard Henderson
---
tcg/loongarch64/tcg-insn-defs.c.inc | 10 +-
1 file chang
Hi,
On 1/18/23 09:11, Richard Henderson wrote:
Based-on: 20230117231051.35-1-richard.hender...@linaro.org
("[PULL 00/22] tcg patch queue")
Includes:
* Disassembler from target/loongarch/.
* Improvements to movi by Rui Wang, with minor tweaks.
* Improvements to setcond.
* Impleme
On 1/18/23 09:11, Richard Henderson wrote:
Reuse the decodetree based disassembler from
target/loongarch/ for tcg/loongarch64/.
The generation of decode-insns.c.inc into ./libcommon.fa.p/ could
eventually result in conflict, if any other host requires the same
trick, but this is good enough for
On Sat, Jan 21, 2023 at 07:57:02PM -0500, Chuck Zmudzinski wrote:
> Intel specifies that the Intel IGD must occupy slot 2 on the PCI bus,
> as noted in docs/igd-assign.txt in the Qemu source code.
>
> Currently, when the xl toolstack is used to configure a Xen HVM guest with
> Intel IGD passthroug
On 21/01/2023 1:06, Alex Williamson wrote:
External email: Use caution opening links or attachments
On Mon, 16 Jan 2023 16:11:26 +0200
Avihai Horon wrote:
Currently, if IOMMU of a VFIO container doesn't support dirty page
tracking, migration is blocked. This is because a DMA-able VFIO devi
On 21/01/2023 1:07, Alex Williamson wrote:
External email: Use caution opening links or attachments
On Mon, 16 Jan 2023 16:11:31 +0200
Avihai Horon wrote:
Implement the basic mandatory part of VFIO migration protocol v2.
This includes all functionality that is necessary to support
VFIO_MIG
On 22/01/2023 10:16, Michael S. Tsirkin wrote:
On Fri, Jan 20, 2023 at 07:37:18PM +0200, Anton Kuchin wrote:
On 20/01/2023 15:58, Michael S. Tsirkin wrote:
On Thu, Jan 19, 2023 at 03:45:06PM +0200, Anton Kuchin wrote:
On 19/01/2023 14:51, Michael S. Tsirkin wrote:
On Sun, Jan 15, 2023 at 07:0
On Sun, Jan 22, 2023 at 02:36:04PM +0200, Anton Kuchin wrote:
> > > This flag should be set when qemu don't need to worry about any
> > > external state stored in vhost-user daemons during migration:
> > > don't fail migration, just pack generic virtio device states to
> > > migration stream and or
---
qga/commands-posix.c | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/qga/commands-posix.c b/qga/commands-posix.c
index ebd33a643c..aab9d3bd50 100644
--- a/qga/commands-posix.c
+++ b/qga/commands-posix.c
@@ -880,7 +880,9 @@ static bool build_guest_fsinfo_for_pci_dev(cha
On 1/22/23 3:40 AM, Michael S. Tsirkin wrote:
> On Sat, Jan 21, 2023 at 07:57:02PM -0500, Chuck Zmudzinski wrote:
>> Intel specifies that the Intel IGD must occupy slot 2 on the PCI bus,
>> as noted in docs/igd-assign.txt in the Qemu source code.
>>
>> Currently, when the xl toolstack is used to c
On Mon, 29 Jun 2020, BALATON Zoltan wrote:
This is now a minimal set of patches needed to make it possible to
experiment with a firmware ROM from real hardware. After finding out
that the board firmware does not probe PCI devices but expects them at
known fixed addresses we only need to change th
On Fri, 20 Jan 2023, Cédric Le Goater wrote:
On 1/19/23 23:28, BALATON Zoltan wrote:
Add a way to set a backing store for the mac_nvram similar to what
spapr_nvram or mac_via PRAM already does to allow to save its contents
between runs. Use -drive file=nvram.img,format=raw,if=mtd to specify
back
On Sun, 22 Jan 2023, BALATON Zoltan wrote:
On Mon, 29 Jun 2020, BALATON Zoltan wrote:
This is now a minimal set of patches needed to make it possible to
experiment with a firmware ROM from real hardware. After finding out
that the board firmware does not probe PCI devices but expects them at
kno
On 22/01/2023 16:46, Michael S. Tsirkin wrote:
On Sun, Jan 22, 2023 at 02:36:04PM +0200, Anton Kuchin wrote:
This flag should be set when qemu don't need to worry about any
external state stored in vhost-user daemons during migration:
don't fail migration, just pack generic virtio device state
On Sun, Jan 22, 2023 at 06:09:40PM +0200, Anton Kuchin wrote:
>
> On 22/01/2023 16:46, Michael S. Tsirkin wrote:
> > On Sun, Jan 22, 2023 at 02:36:04PM +0200, Anton Kuchin wrote:
> > > > > This flag should be set when qemu don't need to worry about any
> > > > > external state stored in vhost-user
This series brings the PIIX4 PM device closer to reality and resolves some
redundant code along the way.
Testing done:
- `make check`
- Starting a live CD under pc and q35 machines and check that the GPE accesses
are traced
Bernhard Beschow (7):
hw/acpi/{ich9,piix4}: Reuse existing attributes
The bit positions of both registers are related. Tracing the registers
independently results in the same offsets across these registers which
eases debugging.
Signed-off-by: Bernhard Beschow
---
hw/acpi/core.c | 10 +++---
hw/acpi/trace-events | 6 --
2 files changed, 11 insertion
Cosmetic change emphasizing that always the actual address of the gpe0
block is returned.
Signed-off-by: Bernhard Beschow
---
hw/acpi/ich9.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/hw/acpi/ich9.c b/hw/acpi/ich9.c
index f8af238974..40a20e01ea 100644
--- a/hw/acpi/ic
The QOM properties are accessed after the device models have been
realized. This means that the constants are redundant. Remove them.
Signed-off-by: Bernhard Beschow
---
hw/acpi/ich9.c | 5 ++---
hw/acpi/piix4.c | 10 --
2 files changed, 6 insertions(+), 9 deletions(-)
diff --git a/hw
A MemoryRegion has an addr attribute which gets set to the same values
as the redundant io_addr attributes.
Signed-off-by: Bernhard Beschow
---
include/hw/acpi/ich9.h | 1 -
include/hw/acpi/piix4.h | 2 --
hw/acpi/ich9.c | 17 -
hw/acpi/piix4.c | 11 ++
The first thing ich9_pm_iospace_update() does is to set pm->pm_io_base to
the pm_io_base parameter. The pm_io_base parameter's value is the old
one of pm->pm_io_base.
Signed-off-by: Bernhard Beschow
---
hw/acpi/ich9.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/hw/acpi
The PIIX4 datasheet defines the GPSTS register to be at offset 0x0c of the
power management I/O register block. This register block is represented
in the device model by the io attribute. So make io_gpe a child memory
region of io at offset 0x0c.
Note that SeaBIOS sets the base address of the regi
Signed-off-by: Bernhard Beschow
---
hw/acpi/core.c | 5 +
hw/acpi/piix4.c | 3 ---
hw/acpi/trace-events | 8
3 files changed, 9 insertions(+), 7 deletions(-)
diff --git a/hw/acpi/core.c b/hw/acpi/core.c
index 6da275c599..a33e410e69 100644
--- a/hw/acpi/core.c
+++ b/hw/acp
On 11/01/2023 00:36, BALATON Zoltan wrote:
On Tue, 10 Jan 2023, Mark Cave-Ayland wrote:
On 04/01/2023 21:59, BALATON Zoltan wrote:
The mac99 machine emulates different machines depending on machine
properties or even if it is run as qemu-system-ppc64 or
qemu-system-ppc. This is very confusing
On 11/01/2023 00:54, BALATON Zoltan wrote:
On Tue, 10 Jan 2023, Mark Cave-Ayland wrote:
On 04/01/2023 21:59, BALATON Zoltan wrote:
OpenBIOS cannot run FCode ROMs yet but it can detect NDRV in VGA card
ROM and add it to the device tree for MacOS. Pass the NDRV this way
instead of via fw_cfg. Th
On 12/01/2023 23:51, BALATON Zoltan wrote:
On Thu, 12 Jan 2023, Howard Spoelstra wrote:
On Wed, Jan 11, 2023 at 1:15 AM BALATON Zoltan wrote:
On Tue, 10 Jan 2023, Mark Cave-Ayland wrote:
On 04/01/2023 21:59, BALATON Zoltan wrote:
Setting emulated machine type with a property called "via"
On 14/01/2023 14:38, Henrik Carlqvist wrote:
https://patchew.org/QEMU/20230114125029.7395a547.hc...@poolhem.se/
complains that "patch is empty", so here is my fifth attempt...
regards Henrik
SUN Type 4, 5 and 5c keyboards have dip switches to choose the language
layout of the keyboard. Solaris
On 15/01/2023 13:45, Volker Rümelin wrote:
Am 15.01.23 um 14:08 schrieb Volker Rümelin:
Ccing a few more people who might be interested in this patch series.
@Mark:
After this patch series, the code in your out of tree ASC audio device (and a few in
tree audio devices) could be simplified. wr
On 18/01/2023 00:32, BALATON Zoltan wrote:
At several places we already have the object pointer with the right
type so we don't need to cast it back and forth. Avoiding these casts
improves readability.
Signed-off-by: BALATON Zoltan
---
hw/misc/macio/macio.c | 14 +++---
1 file chan
On 18/01/2023 00:32, BALATON Zoltan wrote:
Some functions use sysbus_dev while others sbd name for local variable
storing a sysbus device pointer. Standardise on the shorter name to be
consistent and make the code easier to read as short name is less
distracting and needs less line breaks.
Sign
On 18/01/2023 00:32, BALATON Zoltan wrote:
Drop some local variables that could just be substituted at the single
place they were used. This makes the code shorter and simpler.
Signed-off-by: BALATON Zoltan
---
hw/misc/macio/macio.c | 13 +
1 file changed, 5 insertions(+), 8 del
On Sun, 22 Jan 2023, Mark Cave-Ayland wrote:
On 11/01/2023 00:36, BALATON Zoltan wrote:
On Tue, 10 Jan 2023, Mark Cave-Ayland wrote:
On 04/01/2023 21:59, BALATON Zoltan wrote:
The mac99 machine emulates different machines depending on machine
properties or even if it is run as qemu-system-ppc6
On Sun, 22 Jan 2023, Mark Cave-Ayland wrote:
On 12/01/2023 23:51, BALATON Zoltan wrote:
On Thu, 12 Jan 2023, Howard Spoelstra wrote:
On Wed, Jan 11, 2023 at 1:15 AM BALATON Zoltan wrote:
On Tue, 10 Jan 2023, Mark Cave-Ayland wrote:
On 04/01/2023 21:59, BALATON Zoltan wrote:
Setting emulated
On Sun, 22 Jan 2023, Mark Cave-Ayland wrote:
On 11/01/2023 00:54, BALATON Zoltan wrote:
On Tue, 10 Jan 2023, Mark Cave-Ayland wrote:
On 04/01/2023 21:59, BALATON Zoltan wrote:
OpenBIOS cannot run FCode ROMs yet but it can detect NDRV in VGA card
ROM and add it to the device tree for MacOS. Pas
On Sun, Jan 22, 2023 at 5:16 AM Daniel Henrique Barboza
wrote:
>
> Conor,
>
> Thanks for the Icicle-kit walk-through! I'll not claim that I fully
> understood it,
> but I understood enough to handle the situation ATM.
>
> Without this change, this is where the FDT is being installed in the board
On Thu, 19 Jan 2023, Akihiko Odaki wrote:
On 2023/01/15 3:11, BALATON Zoltan wrote:
On Sat, 14 Jan 2023, Akihiko Odaki wrote:
On 2023/01/13 22:43, BALATON Zoltan wrote:
On Thu, 5 Jan 2023, BALATON Zoltan wrote:
Hello,
I got reports from several users trying to run AmigaOS4 on sam460ex on
Ap
On Sat, Jan 21, 2023 at 1:16 AM Philipp Tomsich
wrote:
>
> The decoding of the following instructions from Zb[abcs] currently
> contains decoding/printing errors:
> * xnor,orn,andn: the rs2 operand is not being printed
> * slli.uw: decodes and prints the immediate shift-amount as a
>
On Fri, Jan 20, 2023 at 7:38 AM Daniel Henrique Barboza
wrote:
>
> load_elf_ram_sym() will sign-extend 32 bit addresses. If a 32 bit
> QEMU guest happens to be running in a hypervisor that are using 64
> bits to encode its address, kernel_entry can be padded with '1's
> and create problems [1].
>
From: Wilfred Mallawa
Updates the opentitan IRQs to match the latest supported commit of
Opentitan from TockOS.
OPENTITAN_SUPPORTED_SHA := 565e4af39760a123c59a184aa2f5812a961fde47
Signed-off-by: Wilfred Mallawa
---
include/hw/riscv/opentitan.h | 10 +-
1 file changed, 5 insertions(+),
On Sat, Jan 21, 2023 at 1:16 AM Philipp Tomsich
wrote:
>
> The decoding of the following instructions from Zb[abcs] currently
> contains decoding/printing errors:
> * xnor,orn,andn: the rs2 operand is not being printed
> * slli.uw: decodes and prints the immediate shift-amount as a
>
On Fri, Jan 20, 2023 at 7:38 AM Daniel Henrique Barboza
wrote:
>
> Hi,
>
> In this version I changed the patch order to avoid having a patch that
> would trigger the 32 bit regression Alistair observed. Patch 3 is now
> the first patch.
>
> I've also addressed the comments from Bin and Phil.
>
> P
On Jan 22, 2023, at 4:48 PM, BALATON Zoltan wrote:
> It would be tough to come up with a name for the powerbook3_2 though as these
> were called Early 2001 Titanium PowerBook G4 or code name Mercury but even
> Mac fanatics probably couldn't tell that was a powerbook if you call it
> g4mercury
On Sat, Jan 21, 2023 at 12:36 PM Philipp Tomsich
wrote:
>
> This implements the Zicond (conditional integer operations) extension,
> as of version 1.0-draft-20230120 as an experimental extension in QEMU
> ("x-zicond").
>
> The Zicond extension acts as a building block for branchless sequences
> in
On Sat, Jan 21, 2023 at 12:36 PM Philipp Tomsich
wrote:
>
> The Zicond standard extension implements the same instruction
> semantics as XVentanaCondOps, although using different mnemonics and
> opcodes.
>
> Point XVentanaCondOps to the (newly implemented) Zicond implementation
> to reduce the fut
On Mon, 23 Jan 2023 at 02:28, Alistair Francis wrote:
>
> On Sat, Jan 21, 2023 at 12:36 PM Philipp Tomsich
> wrote:
> >
> > This implements the Zicond (conditional integer operations) extension,
> > as of version 1.0-draft-20230120 as an experimental extension in QEMU
> > ("x-zicond").
> >
> > Th
On Mon, 23 Jan 2023 at 02:29, Alistair Francis wrote:
>
> On Sat, Jan 21, 2023 at 12:36 PM Philipp Tomsich
> wrote:
> >
> > The Zicond standard extension implements the same instruction
> > semantics as XVentanaCondOps, although using different mnemonics and
> > opcodes.
> >
> > Point XVentanaCon
On Mon, Jan 23, 2023 at 10:06 AM Wilfred Mallawa
wrote:
>
> From: Wilfred Mallawa
>
> Updates the opentitan IRQs to match the latest supported commit of
> Opentitan from TockOS.
>
> OPENTITAN_SUPPORTED_SHA := 565e4af39760a123c59a184aa2f5812a961fde47
>
> Signed-off-by: Wilfred Mallawa
Reviewed-b
From: Alistair Francis
If the CSRs and CSR instructions are disabled because the Zicsr
extension isn't enabled then we want to make sure we don't run any CSR
instructions in the boot ROM.
This patches removes the CSR instructions from the reset-vec if the
extension isn't enabled. We replace the
Hi Michael,
On Tue, Jan 10, 2023 at 12:50:42PM -0500, Michael S. Tsirkin wrote:
> On Tue, Jan 10, 2023 at 04:34:49PM +0100, Jason A. Donenfeld wrote:
> > Hi Michael,
> >
> > Could you queue up this patch and mark it as a fix for 7.2.1? It is a
> > straight-up bug fix for a 7.2 regression that's n
From: Wilfred Mallawa
Updates the opentitan IRQs to match the latest supported commit of
Opentitan from TockOS.
OPENTITAN_SUPPORTED_SHA := 565e4af39760a123c59a184aa2f5812a961fde47
Memory layout as per [1]
[1]
https://github.com/lowRISC/opentitan/blob/565e4af39760a123c59a184aa2f5812a961fde47/h
On 20/1/23 16:54, Evgeny Iakovlev wrote:
PL011 currently lacks a reset method. Implement it.
Signed-off-by: Evgeny Iakovlev
---
hw/char/pl011.c | 26 +-
1 file changed, 21 insertions(+), 5 deletions(-)
static void pl011_class_init(ObjectClass *oc, void *data)
{
On 20/1/23 16:54, Evgeny Iakovlev wrote:
PL011 can be in either of 2 modes depending guest config: FIFO and
single register. The last mode could be viewed as a 1-element-deep FIFO.
Current code open-codes a bunch of depth-dependent logic. Refactor FIFO
depth handling code to isolate calculating
On 21/1/23 10:47, Volker Rümelin wrote:
Use a consistent friendly name for the HWVoiceOut and HWVoiceIn
structures.
Reviewed-by: Thomas Huth
Signed-off-by: Volker Rümelin
---
audio/audio_template.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
Reviewed-by: Philippe Mathieu-Dau
On 21/1/23 10:47, Volker Rümelin wrote:
The currently used default playback settings in the ALSA audio
backend are a bit unfortunate. With a few emulated audio devices,
audio playback does not work properly. Here is a short part of
the debug log while audio is playing (elapsed time in seconds).
On 21/1/23 10:47, Volker Rümelin wrote:
Audio recording with ALSA default settings currently doesn't
work. The debug log shows updates every 0.75s and 1.5s.
audio: Elapsed since last alsa run (running): 0.743030
audio: Elapsed since last alsa run (running): 1.486048
audio: Elapsed since last als
On 20/01/2023 20.44, Fabiano Rosas wrote:
These leaks can be avoided:
759 bytes in 61 blocks are still reachable in loss record 56 of 60
at 0x4034744: malloc (in
/usr/lib/valgrind/vgpreload_memcheck-amd64-linux.so)
by 0x4A88518: g_malloc (in /usr/lib64/libglib-2.0.so.0.7000.5)
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