CXL uses PCI AER Internal errors to signal to the host that an error has
occurred. The host can then read more detailed status from the CXL RAS
capability.
For uncorrectable errors: support multiple injection in one operation
as this is needed to reliably test multiple header logging support in an
On 1/16/23 19:24, Nina Schoetterl-Glausch wrote:
On Thu, 2023-01-05 at 15:53 +0100, Pierre Morel wrote:
When the host supports the CPU topology facility, the PTF
instruction with function code 2 is interpreted by the SIE,
provided that the userland hypervizor activates the interpretation
by u
Hi Alex,
Generally, this looks good, but I do have a comment below...
On Thursday, 2023-01-19 at 02:00:02 -05, Alexander Bulekov wrote:
> Add a flag to the DeviceState, when a device is engaged in PIO/MMIO/DMA.
> This flag is set/checked prior to calling a device's MemoryRegion
> handlers, and se
On Fri, 20 Jan 2023 at 14:42, Darren Kenny wrote:
> Generally, this looks good, but I do have a comment below...
>
> On Thursday, 2023-01-19 at 02:00:02 -05, Alexander Bulekov wrote:
> > Add a flag to the DeviceState, when a device is engaged in PIO/MMIO/DMA.
> > This flag is set/checked prior to
Here's my proposal for 8.0 cycle freeze and release dates:
https://wiki.qemu.org/Planning/8.0
2022-12-14 : Beginning of development phase
2022-03-07 : Soft feature freeze. Only bug fixes after this point.
All feature changes must be already in a sub maintainer
tree and a
On Fri, 13 Jan 2023 at 17:10, Alex Bennée wrote:
>
>
> Peter Maydell writes:
>
> > On Sat, 24 Dec 2022 at 15:19, Richard Henderson
> > wrote:
> >>
> >> From: Ilya Leoshkevich
> >>
> >> Add a test that locklessly changes and exercises page protection bits
> >> from various threads. This helps ca
On 1/19/23 18:24, Greg Kurz wrote:
This reverts commit db8a3772e300c1a656331a92da0785d81667dc81.
Motivation : this is breaking vhost-user with DPDK as reported in [0].
Received unexpected msg type. Expected 22 received 40
Fail to update device iotlb
Received unexpected msg type. Expected 40
On 1/20/23 12:45 PM, Peter Maydell wrote:
On Thu, 19 Jan 2023 at 21:57, Evgeny Iakovlev
wrote:
>
>
> On 1/19/2023 14:27, Peter Maydell wrote:
>> On Tue, 17 Jan 2023 at 22:05, Evgeny Iakovlev
>> wrote:
>>> PL011 currently lacks a reset method. Implement it.
>>>
>>> Signed-off-by: Evgeny Iako
On 1/19/23 18:24, Greg Kurz wrote:
This reverts commit a7f523c7d114d445c5d83aecdba3efc038e5a692.
The nested event loop is broken by design. It's only user was removed.
Drop the code as well so that nobody ever tries to use it again.
I had to fix a couple of trivial conflicts around return va
The decoding of the following instructions from Zb[abcs] currently
contains decoding/printing errors:
* xnor,orn,andn: the rs2 operand is not being printed
* slli.uw: decodes and prints the immediate shift-amount as a
register (e.g. 'shift-by-2' becomes 'sp') instead of
in
The Zicond standard extension implements the same instruction
semantics as XVentanaCondOps, although using different mnemonics and
opcodes.
Point XVentanaCondOps to the (newly implemented) Zicond implementation
to reduce the future maintenance burden.
Also updating MAINTAINERS as trans_xventanaco
This implements the Zicond (conditional integer operations) extension,
as of version 1.0-draft-20230120 as an experimental extension in QEMU
("x-zicond").
The Zicond extension acts as a building block for branchless sequences
including conditional-{arithmetic,logic,select,move}. Re
Hi Eric,
On Mon, Jan 16, 2023 at 07:47:09AM -0500, Eric Auger wrote:
[...]
> once we attempt to plug such devices downstream to the pcie-to-pci
> bridge, those devices are put in a singleton group. The pcie-to-pci
> bridge disappears from the radar (not attached to any group), and the
> pcie root
On Wed, Jan 18, 2023 at 11:28:32AM -0700, Alex Williamson wrote:
> The VT-d spec[2](8.3.1) has a more elegant solution using a path
> described in a device scope, based on a root bus number (not
> susceptible to OS renumbering) and a sequence of devfns to uniquely
> describe a hierarchy or endpoint
On 2023-01-20 15:28, Jean-Philippe Brucker wrote:
For some reason this came through as blank mail with a text attachment,
so apologies for the lack of quoting, but for reference this is a
long-standing known issue:
https://lore.kernel.org/linux-iommu/9625faf4-48ef-2dd3-d82f-931d9cf26...@huawe
On Tue, 17 Jan 2023 09:43:52 -0500
Chuck Zmudzinski wrote:
> On 1/17/2023 5:35 AM, Igor Mammedov wrote:
> > On Mon, 16 Jan 2023 13:00:53 -0500
> > Chuck Zmudzinski wrote:
> >
> > > On 1/16/23 10:33, Igor Mammedov wrote:
> > > > On Fri, 13 Jan 2023 16:31:26 -0500
> > > > Chuck Zmudzinski wro
v3:
* Introduced a post_load hook for PL011State migration for
backwards-compatibility due to some input state fragility.
* No longer touching irq lines in reset method
* Minor changes based on review feedback.
v2:
* Moved FIFO depth refactoring part of FIFO flags change into its own
commit.
*
Current FIFO handling code does not reset RXFE/RXFF flags when guest
resets FIFO by writing to UARTLCR register, although internal FIFO state
is reset to 0 read count. Actual guest-visible flag update will happen
only on next data read or write attempt. As a result of that any guest
that expects RX
UART should be enabled in general and have RX enabled specifically to be
able to receive data from peripheral device. Same goes for transmitting
data to peripheral device and a TXE flag.
Check if UART CR register has EN and RXE or TXE bits enabled before
trying to receive or transmit data.
Signed
PL011 currently lacks a reset method. Implement it.
Signed-off-by: Evgeny Iakovlev
---
hw/char/pl011.c | 26 +-
1 file changed, 21 insertions(+), 5 deletions(-)
diff --git a/hw/char/pl011.c b/hw/char/pl011.c
index 4df649a064..f9413f3703 100644
--- a/hw/char/pl011.c
+++ b
PL011 can be in either of 2 modes depending guest config: FIFO and
single register. The last mode could be viewed as a 1-element-deep FIFO.
Current code open-codes a bunch of depth-dependent logic. Refactor FIFO
depth handling code to isolate calculating current FIFO depth.
One functional (albeit
Previous change slightly modified the way we handle data writes when
FIFO is disabled. Previously we kept incrementing read_pos and were
storing data at that position, although we only have a
single-register-deep FIFO now. Then we changed it to always store data
at pos 0.
If guest disables FIFO an
Small series of changes to aarch64 emulation to better support running
Hyper-V as a TCG guest wtih EL3 firmware.
v3:
* Replaced raw_write fn with raw_write instead of a manual function
v2:
* DBGCLAIM now implements a (trivial) raw_write handler
* Added comments around ignored external debug regis
Qemu doesn't implement Debug Communication Channel, as well as the rest
of external debug interface. However, Microsoft Hyper-V in tries to
access some of those registers during an EL2 context switch.
Since there is no architectural way to not advertise support for external
debug, provide RAZ/WI s
The architecture does not define any functionality for the CLAIM tag bits.
So we will just keep the raw bits, as per spec.
Signed-off-by: Evgeny Iakovlev
Reviewed-by: Peter Maydell
Reviewed-by: Richard Henderson
---
target/arm/cpu.h | 1 +
target/arm/debug_helper.c | 33 +
On Tue, 17 Jan 2023 09:50:23 -0500
Chuck Zmudzinski wrote:
> On 1/17/2023 5:35 AM, Igor Mammedov wrote:
> > On Mon, 16 Jan 2023 13:00:53 -0500
> > Chuck Zmudzinski wrote:
> >
> > > On 1/16/23 10:33, Igor Mammedov wrote:
> > > > On Fri, 13 Jan 2023 16:31:26 -0500
> > > > Chuck Zmudzinski wro
On Fri, 20 Jan 2023 at 07:01, Markus Armbruster wrote:
>
> The following changes since commit 7ec8aeb6048018680c06fb9205c01ca6bda08846:
>
> Merge tag 'pull-tpm-2023-01-17-1' of
> https://github.com/stefanberger/qemu-tpm into staging (2023-01-17 15:47:53
> +)
>
> are available in the Git re
On Fri, Jan 20, 2023 at 03:50:18PM +, Robin Murphy wrote:
> On 2023-01-20 15:28, Jean-Philippe Brucker wrote:
>
> For some reason this came through as blank mail with a text attachment,
Ugh sorry about that, looks like I hit ^D in mutt before sending
> so apologies for the lack of quoting, b
Commit d9e474ea56 overlooked the case where the target psize is even larger
than the host psize. One example is Alpha has 8K page size and migration
will start to crash the source QEMU when running Alpha migration on x86.
Fix it by detecting that case and set host start/end just to cover the
sing
On Thu, 19 Jan 2023 14:47:41 +
Bernhard Beschow wrote:
> Am 18. Januar 2023 14:59:05 UTC schrieb Igor Mammedov :
> >On Tue, 17 Jan 2023 00:30:23 +
> >Bernhard Beschow wrote:
> >
> >> Am 16. Januar 2023 16:29:30 UTC schrieb Igor Mammedov
> >> :
> >> >On Mon, 16 Jan 2023 16:29:03 +010
Hi Jean, Robin,
On 1/20/23 17:23, Jean-Philippe Brucker wrote:
> On Fri, Jan 20, 2023 at 03:50:18PM +, Robin Murphy wrote:
>> On 2023-01-20 15:28, Jean-Philippe Brucker wrote:
>>
>> For some reason this came through as blank mail with a text attachment,
> Ugh sorry about that, looks like I hit
Thomas Huth writes:
> On 20/01/2023 11.53, Ilya Leoshkevich wrote:
>> On Fri, 2023-01-20 at 10:41 +0100, Thomas Huth wrote:
>>> On 16/01/2023 23.36, Richard Henderson wrote:
The following changes since commit
fb7e7990342e59cf67dbd895c1a1e3fb1741df7a:
tests/qtest/qom-test
On Tue, 17 Jan 2023, Chuck Zmudzinski wrote:
> On 1/17/2023 6:04 AM, Igor Mammedov wrote:
> > On Mon, 16 Jan 2023 13:00:53 -0500
> > Chuck Zmudzinski wrote:
> >
> > > On 1/16/23 10:33, Igor Mammedov wrote:
> > > > On Fri, 13 Jan 2023 16:31:26 -0500
> > > > Chuck Zmudzinski wrote:
> > > >
> > >
Commit 800d4deda0 "softmmu: move more files to softmmu/" (v5.2.0)
updated MAINTAINERS for all moved files but one. Fix that.
Fixes: 800d4deda04be016a95fbbf397c830a2d14ff9f6
Signed-off-by: Markus Armbruster
---
MAINTAINERS | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/MAINT
Peter Maydell writes:
> On Fri, 13 Jan 2023 at 13:39, Alex Bennée wrote:
>>
>> diff --git a/qemu-options.hx b/qemu-options.hx
>> index 3aa3a2f5a3..de3a368f58 100644
>> --- a/qemu-options.hx
>> +++ b/qemu-options.hx
>> @@ -4633,10 +4633,13 @@ DEF("semihosting", 0, QEMU_OPTION_semihosting,
>>
On Fri, 20 Jan 2023 at 08:40, Cédric Le Goater wrote:
>
> On 1/19/23 13:34, Cédric Le Goater wrote:
> > Cortex A7 CPUs with an FPU implementing VFPv4 without NEON support
> > have 16 64-bit FPU registers and not 32 registers. Let users set the
> > number of VFP registers with a CPU property.
> >
>
Jonathan Cameron wrote:
> On Thu, 19 Jan 2023 15:04:49 +
> Jonathan Cameron wrote:
>
> > On Thu, 19 Jan 2023 12:42:44 +
> > Jonathan Cameron via wrote:
> >
> > > On Wed, 18 Jan 2023 14:31:53 -0500
> > > Gregory Price wrote:
> > >
> > > > I apparently forgot an intro lol
> > > >
> >
On 20/01/2023 15:58, Michael S. Tsirkin wrote:
On Thu, Jan 19, 2023 at 03:45:06PM +0200, Anton Kuchin wrote:
On 19/01/2023 14:51, Michael S. Tsirkin wrote:
On Sun, Jan 15, 2023 at 07:09:03PM +0200, Anton Kuchin wrote:
Now any vhost-user-fs device makes VM unmigratable, that also prevents
qemu
Richard Henderson writes:
> Use of start_exclusive on this exit path leads to deadlock,
> in particular when called from dump_core_and_abort. There
> does not appear to be a need for it.
We don't want to be doing any translation while un-registering things
lest things get confused. You could
Gregory Price wrote:
> On Thu, Jan 19, 2023 at 03:04:49PM +, Jonathan Cameron wrote:
> > Gregory, would you mind checking if
> > cxl_nvb is NULL here...
> > https://elixir.bootlin.com/linux/v6.2-rc4/source/drivers/cxl/pmem.c#L67
> > (printk before it is used should work).
> >
> > Might also be
Richard Henderson writes:
> Rather than iterate over all plugins for all events,
> iterate over plugins that have registered a given event.
>
> Signed-off-by: Richard Henderson
Queued to plugins/next, thanks.
--
Alex Bennée
Virtualisation Tech Lead @ Linaro
On Mon, 16 Jan 2023 14:37:23 +
Jonathan Cameron via wrote:
> On Fri, 13 Jan 2023 17:10:51 +
> Fan Ni wrote:
>
> > On Fri, Jan 13, 2023 at 09:47:25AM +, Jonathan Cameron wrote:
> >
> > > On Fri, 13 Jan 2023 00:27:55 +
> > > Fan Ni wrote:
> > >
> > > > For passthrough dec
On Fri, 20 Jan 2023 at 15:54, Evgeny Iakovlev
wrote:
>
> Previous change slightly modified the way we handle data writes when
> FIFO is disabled. Previously we kept incrementing read_pos and were
> storing data at that position, although we only have a
> single-register-deep FIFO now. Then we chan
On Fri, 20 Jan 2023 at 15:54, Evgeny Iakovlev
wrote:
>
> PL011 can be in either of 2 modes depending guest config: FIFO and
> single register. The last mode could be viewed as a 1-element-deep FIFO.
>
> Current code open-codes a bunch of depth-dependent logic. Refactor FIFO
> depth handling code t
On Fri, 20 Jan 2023 at 15:54, Evgeny Iakovlev
wrote:
>
> PL011 currently lacks a reset method. Implement it.
>
> Signed-off-by: Evgeny Iakovlev
> ---
> hw/char/pl011.c | 26 +-
Reviewed-by: Peter Maydell
thanks
-- PMM
On Fri, 20 Jan 2023 at 15:54, Evgeny Iakovlev
wrote:
>
> Current FIFO handling code does not reset RXFE/RXFF flags when guest
> resets FIFO by writing to UARTLCR register, although internal FIFO state
> is reset to 0 read count. Actual guest-visible flag update will happen
> only on next data read
On Fri, 20 Jan 2023 at 15:59, Evgeny Iakovlev
wrote:
>
> Small series of changes to aarch64 emulation to better support running
> Hyper-V as a TCG guest wtih EL3 firmware.
Applied to target-arm.next, thanks.
-- PMM
Now that the cortex-a15 is under CONFIG_TCG, use as default CPU for a
KVM-only build the 'max' cpu.
Note that we cannot use 'host' here because the qtests can run without
any other accelerator (than qtest) and 'host' depends on KVM being
enabled.
Signed-off-by: Fabiano Rosas
Cc: Daniel P. Berran
Signed-off-by: Fabiano Rosas
Reviewed-by: Richard Henderson
Acked-by: Thomas Huth
---
tests/qtest/arm-cpu-features.c | 22 +++---
1 file changed, 15 insertions(+), 7 deletions(-)
diff --git a/tests/qtest/arm-cpu-features.c b/tests/qtest/arm-cpu-features.c
index 4ff2014bea..1555
We are about to enable the build without TCG, so CONFIG_SEMIHOSTING
and CONFIG_ARM_COMPATIBLE_SEMIHOSTING cannot be unconditionally set in
default.mak anymore. So reflect the change in a Kconfig.
Instead of using semihosting/Kconfig, use a target-specific file, so
that the change doesn't affect ot
The tests under tests/tcg depend on the TCG accelerator. Do not build
them if --disable-tcg was given in the configure line.
Signed-off-by: Fabiano Rosas
Reviewed-by: Richard Henderson
Reviewed-by: Philippe Mathieu-Daudé
---
configure | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
These tests set -accel tcg, so restrict them to when TCG is present.
Signed-off-by: Fabiano Rosas
Acked-by: Richard Henderson
Reviewed-by: Thomas Huth
---
Removed unneeded hunk restricting dependencies
Use config_all instead of config_devices_all to check for TCG
---
tests/qtest/meson.build |
From: Claudio Fontana
move the module containing cpu models definitions
for 32bit TCG-only CPUs to tcg/ and rename it for clarity.
Signed-off-by: Claudio Fontana
Signed-off-by: Fabiano Rosas
Reviewed-by: Richard Henderson
---
First and last hunks are new.
---
hw/arm/virt.c
Move the 64-bit CPUs that are TCG-only:
- cortex-a35
- cortex-a55
- cortex-a72
- cortex-a76
- a64fx
- neoverse-n1
Keep the CPUs that can be used with KVM:
- cortex-a57
- cortex-a53
- max
- host
For the special case "max" CPU, there's a nuance that while KVM/HVF
use the "host" model instead, we st
Move all the CONFIG_FOO=y from default.mak into "default y if TCG"
statements in Kconfig. That way they won't be selected when
CONFIG_TCG=n.
I'm leaving CONFIG_ARM_VIRT in default.mak because it allows us to
keep the two default.mak files not empty and keep aarch64-default.mak
including arm-defaul
This series makes the necessary changes to allow the use of
--disable-tcg for arm.
Based on "target/arm: CONFIG_TCG=n part 1":
https://lore.kernel.org/r/20230118193518.26433-1-faro...@suse.de
Since v4:
- Used "max" as the default CPU for KVM-only builds. This allows me to
drop all the clunky q
The migration tests are currently broken for an aarch64 host because
the tests pass no 'machine' and 'cpu' options on the QEMU command
line. Most other architectures define a default value in QEMU for
these options, but arm does not.
Add these options to the test class in case the test is being ex
On 1/20/2023 11:57 AM, Stefano Stabellini wrote:
> On Tue, 17 Jan 2023, Chuck Zmudzinski wrote:
> > On 1/17/2023 6:04 AM, Igor Mammedov wrote:
> > > On Mon, 16 Jan 2023 13:00:53 -0500
> > > Chuck Zmudzinski wrote:
> > >
> > > > On 1/16/23 10:33, Igor Mammedov wrote:
> > > > > On Fri, 13 Jan 2023 1
These leaks can be avoided:
759 bytes in 61 blocks are still reachable in loss record 56 of 60
at 0x4034744: malloc (in
/usr/lib/valgrind/vgpreload_memcheck-amd64-linux.so)
by 0x4A88518: g_malloc (in /usr/lib64/libglib-2.0.so.0.7000.5)
by 0x4AA313E: g_strdup (in /usr/lib64/libglib-2.
On 1/20/2023 11:01 AM, Igor Mammedov wrote:
> On Tue, 17 Jan 2023 09:50:23 -0500
> Chuck Zmudzinski wrote:
>
> > On 1/17/2023 5:35 AM, Igor Mammedov wrote:
> > > On Mon, 16 Jan 2023 13:00:53 -0500
> > > Chuck Zmudzinski wrote:
> > >
> > > > On 1/16/23 10:33, Igor Mammedov wrote:
> > > > > On
On 1/20/23 08:48, Fabiano Rosas wrote:
Now that the cortex-a15 is under CONFIG_TCG, use as default CPU for a
KVM-only build the 'max' cpu.
Note that we cannot use 'host' here because the qtests can run without
any other accelerator (than qtest) and 'host' depends on KVM being
enabled.
Signed-of
On Sat, 14 Jan 2023, Chuck Zmudzinski wrote:
> Intel specifies that the Intel IGD must occupy slot 2 on the PCI bus,
> as noted in docs/igd-assign.txt in the Qemu source code.
>
> Currently, when the xl toolstack is used to configure a Xen HVM guest with
> Intel IGD passthrough to the guest with t
There is a dependency in cpu_x86_update_cr0() to the current value of CR4
to enable or disable long-mode. This value is outdated when switching into
or out of SVM. This leads to invalid CPU state when returning from an unpaged
VM when EFER.LME is set.
Signed-off-by: Bernhard Kauer
diff
On Fri, Jan 20, 2023 at 09:38:13AM -0800, Dan Williams wrote:
> As it stands currently that dax device and the cxl device are not
> related since a default dax-device is loaded just based on the presence
> of an EFI_MEMORY_SP address range in the address map. With the new ram
> enabling that defaul
Guest to host page translation should be done even if the guest runs in unpaged
mode.
See last sentence in AMD SDM rev 3.40 section 15.25.5.
Signed-off-by: Bernhard Kauer
---
target/i386/tcg/sysemu/excp_helper.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/target/i386/tcg/sysemu/excp_
We currently never pass parameters to the avocado process via
Makefile. To start doing so we need to invert the precedence between
command line parameters and tags, otherwise a command line parameter
would override values for all the tests, which is unlikely to be a
common use-case.
A more likely
Add support for the 'avocado run' "-p" option, which allows us to pass
parameters in the form key=value to be applied to all tests selected
for a given run. This is useful to force generic tests to use a
specific machine, cpu or qemu-binary where otherwise the defaults
would be used.
E.g.:
$ make
This is intended to replace the last two patches of Daniel's series:
https://lore.kernel.org/r/20230118124348.364771-1-dbarb...@ventanamicro.com
Currently, the initialization code in setUp() infers properties of the
tests & host/target machine by looking at the avocado tags present in
the test. If
Guest to host page translation is missing if the guest runs in unpaged mode.
See last sentence in AMD SDM rev 3.40 section 15.25.5.
Signed-off-by: Bernhard Kauer
---
target/i386/tcg/sysemu/excp_helper.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/target/i386/tcg/sysemu/excp_helper.c
Gregory Price wrote:
> On Fri, Jan 20, 2023 at 09:38:13AM -0800, Dan Williams wrote:
> > As it stands currently that dax device and the cxl device are not
> > related since a default dax-device is loaded just based on the presence
> > of an EFI_MEMORY_SP address range in the address map. With the n
On Mon, 16 Jan 2023 16:11:26 +0200
Avihai Horon wrote:
> Currently, if IOMMU of a VFIO container doesn't support dirty page
> tracking, migration is blocked. This is because a DMA-able VFIO device
> can dirty RAM pages without updating QEMU about it, thus breaking the
> migration.
>
> However, t
On Mon, 16 Jan 2023 16:11:27 +0200
Avihai Horon wrote:
> Add new function qemu_file_get_to_fd() that allows reading data from
> QEMUFile and writing it straight into a given fd.
>
> This will be used later in VFIO migration code.
>
> Signed-off-by: Avihai Horon
> Reviewed-by: Vladimir Sementso
On Mon, 16 Jan 2023 16:11:31 +0200
Avihai Horon wrote:
> Implement the basic mandatory part of VFIO migration protocol v2.
> This includes all functionality that is necessary to support
> VFIO_MIGRATION_STOP_COPY part of the v2 protocol.
>
> The two protocols, v1 and v2, will co-exist and in the
On Mon, Jan 09, 2023 at 07:32:05PM +, Sean Christopherson wrote:
> On Fri, Jan 06, 2023, Chao Peng wrote:
> > On Thu, Jan 05, 2023 at 11:23:01AM +, Jarkko Sakkinen wrote:
> > > On Fri, Dec 02, 2022 at 02:13:41PM +0800, Chao Peng wrote:
> > > > To make future maintenance easy, internally use
On Tue, Jan 10, 2023 at 05:14:32PM +0800, Chao Peng wrote:
> On Mon, Jan 09, 2023 at 07:32:05PM +, Sean Christopherson wrote:
> > On Fri, Jan 06, 2023, Chao Peng wrote:
> > > On Thu, Jan 05, 2023 at 11:23:01AM +, Jarkko Sakkinen wrote:
> > > > On Fri, Dec 02, 2022 at 02:13:41PM +0800, Chao
On 1/20/23 4:34 PM, Stefano Stabellini wrote:
> On Sat, 14 Jan 2023, Chuck Zmudzinski wrote:
> > Intel specifies that the Intel IGD must occupy slot 2 on the PCI bus,
> > as noted in docs/igd-assign.txt in the Qemu source code.
> >
> > Currently, when the xl toolstack is used to configure a Xen HV
This implements the Zicond (conditional integer operations) extension,
as of version 1.0-draft-20230120 as an experimental extension in QEMU
("x-zicond").
The Zicond extension acts as a building block for branchless sequences
including conditional-{arithmetic,logic,select,move}. Re
The Zicond standard extension implements the same instruction
semantics as XVentanaCondOps, although using different mnemonics and
opcodes.
Point XVentanaCondOps to the (newly implemented) Zicond implementation
to reduce the future maintenance burden.
Also updating MAINTAINERS as trans_xventanaco
I e-mailed his business address and received a bounce back from Google
saying the account
does not exist.
On 1/18/2023 6:34 AM, Thomas Huth wrote:
When sending mail to Kamil's address, it's bouncing with a message
that the mailbox is full. This already happens since summer 2022,
and the last me
On 1/19/23 23:41, Thomas Huth wrote:
On 16/01/2023 23.36, Richard Henderson wrote:
The following changes since commit fb7e7990342e59cf67dbd895c1a1e3fb1741df7a:
tests/qtest/qom-test: Do not print tested properties by default (2023-01-16 15:00:57
+)
are available in the Git repository a
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