* Cornelia Huck (coh...@redhat.com) wrote:
> On Tue, Jan 17 2023, "Dr. David Alan Gilbert" wrote:
>
> > * Peter Maydell (peter.mayd...@linaro.org) wrote:
> >> On Wed, 11 Jan 2023 at 16:13, Cornelia Huck wrote:
> >> >
> >> > Introduce a new cpu feature flag to control MTE support. To preserve
> >
Am 17.01.2023 um 17:43 hat Warner Losh geschrieben:
> On Tue, Jan 17, 2023 at 9:25 AM Kevin Wolf wrote:
>
> > Am 17.01.2023 um 17:16 hat Warner Losh geschrieben:
> > > On Tue, Jan 17, 2023 at 6:52 AM Emanuele Giuseppe Esposito <
> > > eespo...@redhat.com> wrote:
> > >
> > > > QEMU does not compil
Am 17.01.2023 um 16:44 hat Kevin Wolf geschrieben:
> Am 15.12.2022 um 14:02 hat Paolo Bonzini geschrieben:
> > blkdebug events can be called from either non-coroutine or coroutine
> > contexts. However, suspend actions only make sense from within
> > a coroutine. Currently, using those action wou
On 1/17/23 17:45, Thomas Huth wrote:
On 17/01/2023 14.15, Laurent Vivier wrote:
Signed-off-by: Laurent Vivier
Acked-by: Michael S. Tsirkin
Acked-by: Thomas Huth
---
Notes:
v6:
- call socket_init() otherwise socket_check_protocol_support() fails
- if socket_check_protocol_s
On Tue, Jan 17, 2023, Chao Peng wrote:
> On Tue, Jan 17, 2023 at 11:21:10AM +0800, Binbin Wu wrote:
> >
> > On 12/2/2022 2:13 PM, Chao Peng wrote:
> > > In confidential computing usages, whether a page is private or shared is
> > > necessary information for KVM to perform operations like page faul
Richard Henderson writes:
> The INDEX_op_exit_tb opcode needs no register allocation.
> Split out a dedicated helper function for it.
>
> Reviewed-by: Philippe Mathieu-Daudé
> Signed-off-by: Richard Henderson
Reviewed-by: Alex Bennée
--
Alex Bennée
Virtualisation Tech Lead @ Linaro
On 1/11/23 09:57, Thomas Huth wrote:
On 05/01/2023 15.53, Pierre Morel wrote:
The maximum nested topology entries is used by the guest to know
how many nested topology are available on the machine.
Currently, SCLP READ SCP INFO reports MNEST = 0, which is the
equivalent of reporting the defa
On 1/11/23 18:52, Nina Schoetterl-Glausch wrote:
On Thu, 2023-01-05 at 15:53 +0100, Pierre Morel wrote:
The maximum nested topology entries is used by the guest to know
how many nested topology are available on the machine.
Currently, SCLP READ SCP INFO reports MNEST = 0, which is the
equiva
Richard Henderson writes:
> Signed-off-by: Richard Henderson
Reviewed-by: Alex Bennée
--
Alex Bennée
Virtualisation Tech Lead @ Linaro
Richard Henderson writes:
> Signed-off-by: Richard Henderson
Reviewed-by: Alex Bennée
--
Alex Bennée
Virtualisation Tech Lead @ Linaro
Richard Henderson writes:
> Signed-off-by: Richard Henderson
Reviewed-by: Alex Bennée
--
Alex Bennée
Virtualisation Tech Lead @ Linaro
Richard Henderson writes:
> Test TCG_TARGET_HAS_direct_jump instead of testing an
> implementation pointer.
>
> Reviewed-by: Philippe Mathieu-Daudé
> Signed-off-by: Richard Henderson
Reviewed-by: Alex Bennée
--
Alex Bennée
Virtualisation Tech Lead @ Linaro
Richard Henderson writes:
> Similar to the existing set_jmp_reset_offset. Move any assert for
> TCG_TARGET_HAS_direct_jump into the new function (which now cannot
> be build-time). Will be unused if TCG_TARGET_HAS_direct_jump is
> constant 0, but we can't test for constant in the preprocessor
On Tue, Jan 17, 2023 at 07:47:06AM +0100, Philippe Mathieu-Daudé wrote:
> On 16/1/23 18:23, Peter Delevoryas wrote:
> > On Mon, Jan 16, 2023 at 01:30:19PM +0100, Philippe Mathieu-Daudé wrote:
> > > On 14/1/23 18:01, Peter Delevoryas wrote:
> > > > Signed-off-by: Peter Delevoryas
> > > > ---
> > >
* Peter Maydell (peter.mayd...@linaro.org) wrote:
> On Tue, 17 Jan 2023 at 16:51, Dr. David Alan Gilbert
> wrote:
> >
> > * Peter Maydell (peter.mayd...@linaro.org) wrote:
> > > On Wed, 11 Jan 2023 at 16:13, Cornelia Huck wrote:
> > > > +MTE CPU Property
> > > > +
> > > > +
> > >
On Tue, 17 Jan 2023 16:07:00 +0100
Maxime Coquelin wrote:
>
>
> On 1/17/23 13:36, Greg Kurz wrote:
> > On Tue, 17 Jan 2023 13:12:57 +0100
> > Greg Kurz wrote:
> >
> >> Hi Maxime,
> >>
> >> On Tue, 17 Jan 2023 10:49:37 +0100
> >> Maxime Coquelin wrote:
> >>
> >>> Hi Yajun,
> >>>
> >>> On 1/16
Richard Henderson writes:
> The INDEX_op_goto_tb opcode needs no register allocation.
> Split out a dedicated helper function for it.
>
> Reviewed-by: Philippe Mathieu-Daudé
> Signed-off-by: Richard Henderson
Reviewed-by: Alex Bennée
--
Alex Bennée
Virtualisation Tech Lead @ Linaro
Richard Henderson writes:
> Similar to the existing set_jmp_reset_offset. Include the
> rw->rx address space conversion done by arm and s390x, and
> forgotten by mips and riscv.
>
> Reviewed-by: Philippe Mathieu-Daudé
> Signed-off-by: Richard Henderson
> ---
> tcg/tcg.c | 9
Richard Henderson writes:
> This will shortly be used for more than reset.
>
> Reviewed-by: Philippe Mathieu-Daudé
> Signed-off-by: Richard Henderson
Reviewed-by: Alex Bennée
--
Alex Bennée
Virtualisation Tech Lead @ Linaro
On Tue, Jan 17, 2023 at 08:35:44AM +0100, Cédric Le Goater wrote:
> On 1/17/23 00:56, Peter Delevoryas wrote:
> > Allows users to specify binary data to initialize an EEPROM, allowing users
> > to
> > emulate data programmed at manufacturing time.
> >
> > - Added init_rom and init_rom_size attrib
On 1/11/23 10:00, Thomas Huth wrote:
On 05/01/2023 15.53, Pierre Morel wrote:
During a subsystem reset the Topology-Change-Report is cleared
by the machine.
Let's ask KVM to clear the Modified Topology Change Report (MTCR)
bit of the SCA in the case of a subsystem reset.
Signed-off-by: Pierr
Richard Henderson writes:
> This can replace four other variables that are references
> into the TranslationBlock structure.
>
> Signed-off-by: Richard Henderson
Reviewed-by: Alex Bennée
--
Alex Bennée
Virtualisation Tech Lead @ Linaro
On Tue, Jan 17, 2023 at 08:39:06AM +0100, Cédric Le Goater wrote:
> On 1/17/23 00:56, Peter Delevoryas wrote:
> > - Create aspeed_eeprom.c and aspeed_eeprom.h
> > - Include aspeed_eeprom.c in CONFIG_ASPEED meson source files
> > - Include aspeed_eeprom.h in aspeed.c
> > - Add fby35_bmc_fruid data
>
Richard Henderson writes:
> Stop overloading jmp_target_arg for both offset and address,
> depending on TCG_TARGET_HAS_direct_jump. Instead, add a new
> field to hold the jump insn offset and always set the target
> address in jmp_target_addr[]. This will allow a tcg backend
> to use either d
Richard Henderson writes:
> Replace 'tc_ptr' and 'addr' with 'tb' and 'n'.
>
> Signed-off-by: Richard Henderson
> ---
> tcg/aarch64/tcg-target.h | 3 ++-
> tcg/arm/tcg-target.h | 3 ++-
> tcg/i386/tcg-target.h| 9 ++---
> tcg/loongarch64/tcg-target.h
Richard Henderson writes:
> Reviewed-by: Philippe Mathieu-Daudé
> Signed-off-by: Richard Henderson
Reviewed-by: Alex Bennée
--
Alex Bennée
Virtualisation Tech Lead @ Linaro
Richard Henderson writes:
> Install empty versions for !TCG_TARGET_HAS_direct_jump hosts.
>
> Reviewed-by: Philippe Mathieu-Daudé
> Signed-off-by: Richard Henderson
> ---
> tcg/arm/tcg-target.c.inc | 6 ++
> tcg/mips/tcg-target.c.inc | 6 ++
> tcg/riscv/tcg-target.c.inc | 6 ++
Dear Ben,
sorry for longer response times...
On Tuesday 17 of January 2023 14:32:29 Ben Dooks wrote:
> On 04/01/2023 12:22, Ben Dooks wrote:
> > From: Ben Dooks
> >
> > Add support for Microchip MCP25625 SPI based CAN controller which is
> > very similar to the MCP2515 (and covered by the same L
On Tue, 17 Jan 2023 18:55:24 +0100
Greg Kurz wrote:
> On Tue, 17 Jan 2023 16:07:00 +0100
> Maxime Coquelin wrote:
>
> >
> >
> > On 1/17/23 13:36, Greg Kurz wrote:
> > > On Tue, 17 Jan 2023 13:12:57 +0100
> > > Greg Kurz wrote:
> > >
> > >> Hi Maxime,
> > >>
> > >> On Tue, 17 Jan 2023 10:49:
Richard Henderson writes:
> We now have the option to generate direct or indirect
> goto_tb depending on the dynamic displacement, thus
> the define is no longer necessary or completely accurate.
>
> Signed-off-by: Richard Henderson
> ---
> tcg/aarch64/tcg-target.h | 1 -
> tcg/arm/tcg-t
Richard Henderson writes:
> The old implementation replaces two insns, swapping between
>
> b
> nop
> br x30
> and
> adrpx30,
> addix30, x30, lo12:
> br x30
>
> There is a race condition in which a thread could be stopped at
> the PC
On Tue, Jan 17, 2023 at 08:42:46AM +0100, Cédric Le Goater wrote:
> On 1/17/23 00:56, Peter Delevoryas wrote:
> > EEPROM's are a form of non-volatile memory. After power-cycling an EEPROM,
> > I would expect the I2C state machine to be reset to default values, but I
> > wouldn't really expect the m
Richard Henderson writes:
> The old ppc64 implementation replaces 2 or 4 insns, which leaves a race
> condition in which a thread could be stopped at a PC in the middle of
> the sequence, and when restarted does not see the complete address
> computation and branches to nowhere.
>
> The new imp
Richard Henderson writes:
> This is always true for sparc64, so this is dead since 3a5f6805c7ca.
>
> Reviewed-by: Philippe Mathieu-Daudé
> Signed-off-by: Richard Henderson
Reviewed-by: Alex Bennée
--
Alex Bennée
Virtualisation Tech Lead @ Linaro
On Tue, Jan 17, 2023 at 09:00:34AM +0100, Philippe Mathieu-Daudé wrote:
> On 17/1/23 00:56, Peter Delevoryas wrote:
> > This helper is useful in board initialization because lets users initialize
> > and
> > realize an EEPROM on an I2C bus with a single function call.
> >
> > Signed-off-by: Peter
Richard Henderson writes:
> The old sparc64 implementation may replace two insns, which leaves
> a race condition in which a thread could be stopped at a PC in the
> middle of the sequence, and when restarted does not see the complete
> address computation and branches to nowhere.
>
> The new i
On Tue, Jan 17, 2023 at 09:08:57AM +0100, Philippe Mathieu-Daudé wrote:
> On 17/1/23 08:39, Cédric Le Goater wrote:
> > On 1/17/23 00:56, Peter Delevoryas wrote:
> > > - Create aspeed_eeprom.c and aspeed_eeprom.h
> > > - Include aspeed_eeprom.c in CONFIG_ASPEED meson source files
> > > - Include as
Richard Henderson writes:
> Now that tcg can handle direct and indirect goto_tb
> simultaneously, we can optimistically leave space for
> a direct branch and fall back to loading the pointer
> from the TB for an indirect branch.
>
> Signed-off-by: Richard Henderson
> ---
> tcg/arm/tcg-target.
Richard Henderson writes:
> Reviewed-by: Philippe Mathieu-Daudé
> Signed-off-by: Richard Henderson
> ---
> tcg/riscv/tcg-target.c.inc | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc
> index 136fe54d4b..82ca864
Richard Henderson writes:
> Now that tcg can handle direct and indirect goto_tb simultaneously,
> we can optimistically leave space for a direct branch and fall back
> to loading the pointer from the TB for an indirect branch.
>
> Signed-off-by: Richard Henderson
Reviewed-by: Alex Bennée
--
Remove dead code:
- unused fields in CPUTriCoreState
- (unexisting) tricore_def_t structure
- forward declaration of tricore_boot_info structure
(declared in "hw/tricore/tricore.h", used once in
hw/tricore/tricore_testboard.c).
Signed-off-by: Philippe Mathieu-Daudé
---
target/tricore/cpu.h
Philippe Mathieu-Daudé writes:
> On 13/1/23 15:04, Fabiano Rosas wrote:
>> From: Claudio Fontana
>>
>> Signed-off-by: Claudio Fontana
>> Signed-off-by: Fabiano Rosas
>> Reviewed-by: Richard Henderson
>> ---
>
>> ---
>> target/arm/meson.build | 16 ++--
>> target/
Philippe Mathieu-Daudé writes:
> On 13/1/23 15:04, Fabiano Rosas wrote:
>> This is in preparation to moving the hflags code into its own file
>> under the tcg/ directory.
>>
>> Signed-off-by: Fabiano Rosas
>> ---
>> I extracted these into a separate patch so we can discuss. If I move
>> the tcg
Philippe Mathieu-Daudé writes:
> On 13/1/23 15:04, Fabiano Rosas wrote:
>> The cpu_tcg.c file about to be moved into the tcg directory. Move the
>> code that is needed for cpus that also work with KVM into cpu.c.
>>
>> Signed-off-by: Fabiano Rosas
>> ---
>> target/arm/cpu.c | 76 +
Cornelia Huck writes:
> On Fri, Jan 13 2023, Fabiano Rosas wrote:
>
>> Signed-off-by: Fabiano Rosas
>> ---
>> tests/qtest/arm-cpu-features.c | 24
>> 1 file changed, 24 insertions(+)
>>
>> diff --git a/tests/qtest/arm-cpu-features.c b/tests/qtest/arm-cpu-features.c
>>
On Tue, Jan 17, 2023 at 04:18:14PM +, Peter Maydell wrote:
> On Tue, 17 Jan 2023 at 16:10, Guenter Roeck wrote:
> >
> > On Mon, Jan 16, 2023 at 09:58:13PM -0700, Keith Busch wrote:
> > > On Mon, Jan 16, 2023 at 10:14:07PM +0100, Klaus Jensen wrote:
> > > > I noticed that the Linux driver does
Use the proper QOM type definition instead of magic string.
This also helps during eventual refactor while using git-grep.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/arm/smmu-common.c | 3 ++-
hw/virtio/virtio-iommu.c | 3 ++-
2 files changed, 4 insertions(+), 2 deletions(-)
diff --git a/
On Tue, Jan 17, 2023, Chao Peng wrote:
> On Sat, Jan 14, 2023 at 12:01:01AM +, Sean Christopherson wrote:
> > On Fri, Dec 02, 2022, Chao Peng wrote:
> > > @@ -10357,6 +10364,12 @@ static int vcpu_enter_guest(struct kvm_vcpu
> > > *vcpu)
> > >
> > > if (kvm_check_request(KVM_REQ_UPD
On 1/11/23 06:13, Cornelia Huck wrote:
@@ -2136,7 +2136,7 @@ static void machvirt_init(MachineState *machine)
if (vms->mte && (kvm_enabled() || hvf_enabled())) {
error_report("mach-virt: %s does not support providing "
- "MTE to the guest CPU",
+
Patch 1/3 was already accepted, but it seems is not in master yet.
Comments addressed in patches 2 and 3.
Let me know if you'd like me to split out a separate commit
for renaming arm_v7m_get_sp_ptr.
David Reiss (3):
target/arm: Unify checking for M Main Extension in MRS/MSR
target/arm/gdbstub
From: David Reiss
Follows a fairly similar pattern to the existing special register debug
support. Only reading is implemented, but it should be possible to
implement writes.
Signed-off-by: David Reiss
---
target/arm/cpu.h | 15 +-
target/arm/gdbstub.c | 116 +++
From: David Reiss
Follows a fairly similar pattern to the existing special register debug
support. Only reading is implemented, but it should be possible to
implement writes.
`v7m_mrs_control` was renamed `arm_v7m_mrs_control` and made
non-static so this logic could be shared between the MRS in
From: David Reiss
BASEPRI, FAULTMASK, and their _NS equivalents only exist on devices with
the Main Extension. However, the MRS instruction did not check this,
and the MSR instruction handled it inconsistently (warning BASEPRI, but
silently ignoring writes to BASEPRI_NS). Unify this behavior an
On 1/17/23 08:14, Alex Bennée wrote:
Richard Henderson writes:
Install empty versions for !TCG_TARGET_HAS_direct_jump hosts.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
tcg/arm/tcg-target.c.inc | 6 ++
tcg/mips/tcg-target.c.inc | 6 ++
tcg/riscv/
On Tue, 2023-01-17 at 18:36 +0100, Pierre Morel wrote:
>
> On 1/11/23 09:57, Thomas Huth wrote:
> > On 05/01/2023 15.53, Pierre Morel wrote:
> > > The maximum nested topology entries is used by the guest to know
> > > how many nested topology are available on the machine.
> > >
> > > Currently, S
Simplify a bit pegasos2_init() by extracting via_i2c_bus().
Signed-off-by: Philippe Mathieu-Daudé
---
hw/ppc/pegasos2.c | 13 +
1 file changed, 9 insertions(+), 4 deletions(-)
diff --git a/hw/ppc/pegasos2.c b/hw/ppc/pegasos2.c
index f46d4bf51d..ac69aee099 100644
--- a/hw/ppc/pegasos
Simple refactor to clarify a bit the southbridge device creation.
Philippe Mathieu-Daudé (2):
hw/ppc/pegasos2: Extract via_i2c_bus() helper
hw/ppc/pegasos2: Extract via_vt8231_create() helper
hw/ppc/pegasos2.c | 46 ++
1 file changed, 30 insertions
Simplify a bit pegasos2_init() by extracting the VIA southbridge
creation code into a new via_vt8231_create() helper.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/ppc/pegasos2.c | 33 +
1 file changed, 21 insertions(+), 12 deletions(-)
diff --git a/hw/ppc/pegasos
On Tue, 17 Jan 2023 at 12:17, Kevin Wolf wrote:
>
> Am 17.01.2023 um 17:43 hat Warner Losh geschrieben:
> > On Tue, Jan 17, 2023 at 9:25 AM Kevin Wolf wrote:
> >
> > > Am 17.01.2023 um 17:16 hat Warner Losh geschrieben:
> > > > On Tue, Jan 17, 2023 at 6:52 AM Emanuele Giuseppe Esposito <
> > > >
On 1/17/23 5:37 AM, Peter Maydell wrote:
> In patch 1 you skip the registers that don't exist without
> the main extension, but here you throw them all in regardless.
> Why the difference ?
Ah, yes. This was an oversight. I'm not sure if there are any
chips that support the security extension bu
On 1/17/23 08:42, Philippe Mathieu-Daudé wrote:
Remove dead code:
- unused fields in CPUTriCoreState
- (unexisting) tricore_def_t structure
- forward declaration of tricore_boot_info structure
(declared in "hw/tricore/tricore.h", used once in
hw/tricore/tricore_testboard.c).
Signed-off-by
On Tue, 17 Jan 2023, Philippe Mathieu-Daudé wrote:
Simplify a bit pegasos2_init() by extracting the VIA southbridge
creation code into a new via_vt8231_create() helper.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/ppc/pegasos2.c | 33 +
1 file changed, 21 insertio
On 1/9/23 13:05, ~dreiss-meta wrote:
From: David Reiss
Follows a fairly similar pattern to the existing special register debug
support. Only reading is implemented, but it should be possible to
implement writes.
`v7m_mrs_control` was renamed `arm_v7m_mrs_control` and made
non-static so this l
On 1/9/23 13:05, ~dreiss-meta wrote:
From: David Reiss
Follows a fairly similar pattern to the existing special register debug
support. Only reading is implemented, but it should be possible to
implement writes.
Signed-off-by: David Reiss
---
target/arm/cpu.h | 15 +-
target/arm
Slightly improve readability of creating the south btidge by cnamging
type of a local variable to avoid some casts within function arguments
which makes some lines shorter and easier to read.
Also remove an unneded line break.
Signed-off-by: BALATON Zoltan
---
hw/ppc/pegasos2.c | 14 +++-
On Tue, 17 Jan 2023, BALATON Zoltan wrote:
Slightly improve readability of creating the south btidge by cnamging
Still left a typo in "bridge" above...
This is alternative, inspired by Phil's patches, maybe I'd also need to
add Inspired-by: tag.
type of a local variable to avoid some casts
Current FIFO handling code does not reset RXFE/RXFF flags when guest
resets FIFO by writing to UARTLCR register, although internal FIFO state
is reset to 0 read count. Actual guest-visible flag update will happen
only on next data read or write attempt. As a result of that any guest
that expects RX
PL011 currently lacks a reset method. Implement it.
Signed-off-by: Evgeny Iakovlev
---
hw/char/pl011.c | 31 ++-
1 file changed, 26 insertions(+), 5 deletions(-)
diff --git a/hw/char/pl011.c b/hw/char/pl011.c
index 329cc6926d..404d52a3b8 100644
--- a/hw/char/pl011.c
v2:
* Moved FIFO depth refactoring part of FIFO flags change into its own
commit.
* Added a reset method for PL011
Evgeny Iakovlev (4):
hw/char/pl011: refactor FIFO depth handling code
hw/char/pl011: implement a reset method
hw/char/pl011: better handling of FIFO flags on LCR reset
hw/ch
UART should be enabled in general and have RX enabled specifically to be
able to receive data from peripheral device. Same goes for transmitting
data to peripheral device and a TXE flag.
Check if UART CR register has EN and RXE or TXE bits enabled before
trying to receive or transmit data.
Signed
PL011 can be in either of 2 modes depending guest config: FIFO and
single register. The last mode could be viewed as a 1-element-deep FIFO.
Current code open-codes a bunch of depth-dependent logic. Refactor FIFO
depth handling code to isolate calculating current FIFO depth.
One functional (albeit
On 1/17/23 5:02 PM, Peter Maydell wrote:
On Tue, 17 Jan 2023 at 15:54, Evgeny Iakovlev
wrote:
>
>
> On 1/17/2023 16:24, Peter Maydell wrote:
>> On Fri, 6 Jan 2023 at 17:28, Evgeny Iakovlev
>> wrote:
>>> Current FIFO handling code does not reset RXFE/RXFF flags when guest
>>> resets FIFO by
Based-on: <20221213213850.1481858-1-pet...@redhat.com>
[PATCH 0/5] migration: Fix disorder of channel creations
Trees for reference:
https://github.com/xzpeter/linux/releases/tag/doublemap-v0.1
https://github.com/xzpeter/qemu/releases/tag/doublemap-v0.1
This is an RFC series that only for e
We do proper page size alignment for file backed mmap()s for ramblocks.
Even if it's as simple as that, cache the value because it'll be used in
multiple places.
Since at it, drop size for file_ram_alloc() and just use max_length because
that's always true for file-backed ramblocks.
Signed-off-by
Without it, we never have CONFIG_LINUX defined even if on linux, so
linux/mman.h is never really included.
Signed-off-by: Peter Xu
---
util/mmap-alloc.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/util/mmap-alloc.c b/util/mmap-alloc.c
index 5ed7d29183..040599b0e3 100644
-
This will allow qemu/madvise.h to always include linux/mman.h under the
linux-headers/.
Signed-off-by: Peter Xu
---
include/qemu/madvise.h | 4
1 file changed, 4 insertions(+)
diff --git a/include/qemu/madvise.h b/include/qemu/madvise.h
index e155f59a0d..b6fa49553f 100644
--- a/include/qem
Returns true for a hugetlbfs mapping, false otherwise.
Signed-off-by: Peter Xu
---
include/exec/cpu-common.h | 1 +
softmmu/physmem.c | 5 +
2 files changed, 6 insertions(+)
diff --git a/include/exec/cpu-common.h b/include/exec/cpu-common.h
index 6feaa40ca7..94452aa17f 100644
--- a/
This allows us to have RAM_READONLY to be set in ram_flags to show that
this ramblock can only be read not write.
We used to pass in readonly boolean along the way for allocating the
ramblock, now let it be together with the rest ramblock flags.
The main purpose of this patch is not for clean up
Let it replace the old qemu_ram_pagesize_largest() just to fetch the page
sizes using migration_ram_pagesize(), because it'll start to consider
double mapping effect in migrations.
Also don't account the ignored ramblocks as they won't be migrated.
Signed-off-by: Peter Xu
---
include/exec/cpu-c
Add a helper to do mmap() for a ramblock based on the cached informations.
A trivial thing to mention is we need to move ramblock->fd setup to be
earlier, before the ramblock_file_map() call, because it'll need to
reference the fd being mapped. However that should not be a problem at
all, majorly
Migration may not want to recognize memory chunks in page size of the host
only, but sometimes we may want to recognize the memory in smaller chunks
if e.g. they're doubly mapped as both huge and small.
In those cases we'll prefer to assume the memory page size is always mapped
small (qemu_real_ho
When a ramblock is backed by hugetlbfs and the user specified using
double-map feature, we trap the faults on these regions using minor mode.
Teach QEMU about that.
Add some sanity check on the fault flags when receiving a uffd message.
For minor fault trapped ranges, we should always see the MINO
When hugetlb-doublemap enabled, the pages will be migrated in small page
sizes during postcopy. When the migration finishes, the pgtable needs to
be rebuilt explicitly for these ranges to have huge page being mapped again.
Signed-off-by: Peter Xu
---
migration/ram.c| 31
Let's fail double-map for vhost-user and any potential users that can have
a remote userfaultfd for now.
Signed-off-by: Peter Xu
---
hw/virtio/vhost-user.c | 9 -
migration/postcopy-ram.c | 9 +++--
migration/postcopy-ram.h | 4 ++--
3 files changed, 17 insertions(+), 5 deletions(-
MADV_SPLIT enables doublemap on hugetlb. Do that if doublemap=true
specified for the migration.
Signed-off-by: Peter Xu
---
migration/postcopy-ram.c | 16
migration/ram.c | 18 ++
2 files changed, 34 insertions(+)
diff --git a/migration/postcopy-ram.c
Hugetlb double map will make the ram discard logic different.
The whole idea will still be the same: we need to a bitmap sync between
src/dst before we switch to postcopy.
When discarding a range, we only erase the pgtables that were used to be
mapped for the guest leveraging the semantics of MAD
Add a RAMBlock.host_mirror for all the hugetlbfs backed guest memories.
It'll be used to remap the same region twice and it'll be used to service
page faults using UFFDIO_CONTINUE.
To make sure all accesses to these ranges will generate minor page faults
not missing page faults, we need to pre-all
Signed-off-by: Peter Xu
---
include/standard-headers/drm/drm_fourcc.h | 63 +++-
include/standard-headers/linux/ethtool.h | 81 -
include/standard-headers/linux/fuse.h | 20 +-
.../linux/input-event-codes.h | 4 +
include/standard-headers/linux/pci_regs.h
Add a new cap to allow mapping hugetlbfs backed RAMs in small page sizes.
Signed-off-by: Peter Xu
---
migration/migration.c | 48 ++-
migration/migration.h | 1 +
qapi/migration.json | 7 ++-
3 files changed, 54 insertions(+), 2 deletions(-)
diff
Teach QEMU to be able to handle page faults using UFFDIO_CONTINUE for
hugetlbfs double mapped ranges.
To copy the data, we need to use the mirror buffer created per ramblock by
a raw memcpy(), then we can kick the faulted threads using UFFDIO_CONTINUE
by installing the pgtables.
Move trace_postco
MADV_SPLIT is a new madvise() on Linux. Define QEMU_MADV_SPLIT.
Signed-off-by: Peter Xu
---
include/qemu/madvise.h | 7 +++
1 file changed, 7 insertions(+)
diff --git a/include/qemu/madvise.h b/include/qemu/madvise.h
index b6fa49553f..325065 100644
--- a/include/qemu/madvise.h
+++ b/in
This value was only used for mmap() when we want to map at a specific
offset of the file for memory. To be prepared that we might do another map
upon the same range for whatever reason, cache the offset so we know how to
map again on the same range.
Signed-off-by: Peter Xu
---
include/exec/ramb
We have a few maintainance work to do after we UFFDIO_[ZERO]COPY a page
before, e.g. on requested list of pages or when measuring page latencies.
Move those steps into a separate function so that it can be easily reused
when we're going to support UFFDIO_CONTINUE.
Signed-off-by: Peter Xu
---
mi
MADV_COLLAPSE is a new madvise() on Linux. Define it.
Signed-off-by: Peter Xu
---
include/qemu/madvise.h | 7 +++
1 file changed, 7 insertions(+)
diff --git a/include/qemu/madvise.h b/include/qemu/madvise.h
index 325065..794e5fb0a7 100644
--- a/include/qemu/madvise.h
+++ b/include/qemu
On Tue, Jan 17, 2023 at 10:32:15AM -0800, Peter Delevoryas wrote:
> On Tue, Jan 17, 2023 at 09:00:34AM +0100, Philippe Mathieu-Daudé wrote:
> > On 17/1/23 00:56, Peter Delevoryas wrote:
> > > This helper is useful in board initialization because lets users
> > > initialize and
> > > realize an EEP
On Wed, Jan 11, 2023 at 3:01 AM wrote:
>
> From: Marc-André Lureau
>
> When no monitor address is given, establish the QMP communication through
> a socketpair() (API is also supported on Windows since Python 3.5)
>
> Signed-off-by: Marc-André Lureau
> Reviewed-by: Daniel P. Berrangé
> ---
> p
On Thu, Jan 12, 2023 at 10:28 AM Maksim Davydov
wrote:
>
> Current 256KB is not enough for some real cases. As a possible solution
> limit can be chosen to be the same as libvirt (10MB)
>
> Signed-off-by: Maksim Davydov
> Reviewed-by: John Snow
> ---
> python/qemu/qmp/qmp_client.py | 4 ++--
>
On 1/17/23 1:40 PM, Richard Henderson wrote:
>> diff --git a/target/arm/cpu.h b/target/arm/cpu.h
>> index bf2bce046d..fdbb0d9107 100644
>> --- a/target/arm/cpu.h
>> +++ b/target/arm/cpu.h
>> @@ -856,6 +856,7 @@ struct ArchCPU {
>> DynamicGDBXMLInfo dyn_sysreg_xml;
>> DynamicGDBXMLI
On 1/17/23 1:42 PM, Richard Henderson wrote:
> Is there a reason why these are separate from m_systemreg?
GDB puts these in a separate file, and J-Link puts them in a separate feature
block.
In general, I think it's nice to separate stuff related to the secure extension
so folks not working with
Am 4. Januar 2023 14:44:31 UTC schrieb Bernhard Beschow :
>This series first renders TYPE_PIIX3_XEN_DEVICE redundant and finally removes
>
>it. The motivation is to 1/ decouple PIIX from Xen and 2/ to make Xen in the PC
>
>machine agnostic to the precise southbridge being used. 2/ will become
>
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