On Fri, Dec 02, 2022 at 04:12:04PM +0100, Pierre-Yves Ritschard wrote:
> Hi,
>
> The provided patch allows the VNC websocket server of a qemu process to
> be provided over AF_UNIX as it is already possible for standard TCP VNC
> servers.
>
> Now that many clients support websocket connections, so
Allowing websockets is fine, but just removing this check is not
> sufficient
>
> The 'websocket=' parameter for -vnc takes two formats
>
>websocket=on|off
>
> or
>
>websocket=portnum
>
> In the case of on|off, the code takes the original VNC display
> num and listens on 5700 + displa
On 17/01/2023 12:31, David Woodhouse wrote:
On Tue, 2023-01-17 at 11:11 +, Paul Durrant wrote:
Ick. Do we really want cross-block gotos? For me it would look a lot
nicer if you did a forward jump here and later and put the label+code
after the `return 0`.
How's this?
From my PoV, much b
On Tue, 17 Jan 2023 at 13:05, Pierre-Yves Ritschard wrote:
>> Allowing websockets is fine, but just removing this check is not
>> sufficient
> Thank you, these semantics weren't obvious to me, I will adapt accordingly
> and post a new patch
When you do, please make sure you include a Signed-of
Signed-off-by: Laurent Vivier
Acked-by: Michael S. Tsirkin
Acked-by: Thomas Huth
---
Notes:
v6:
- call socket_init() otherwise socket_check_protocol_support() fails
- if socket_check_protocol_support() fails then calls g_abort() to
report a problem.
v5:
-
On Sat, Jan 14, 2023 at 12:01:01AM +, Sean Christopherson wrote:
> On Fri, Dec 02, 2022, Chao Peng wrote:
> > @@ -10357,6 +10364,12 @@ static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
> >
> > if (kvm_check_request(KVM_REQ_UPDATE_CPU_DIRTY_LOGGING, vcpu))
> >
On Sat, Jan 14, 2023 at 12:37:59AM +, Sean Christopherson wrote:
> On Fri, Dec 02, 2022, Chao Peng wrote:
> > This patch series implements KVM guest private memory for confidential
> > computing scenarios like Intel TDX[1]. If a TDX host accesses
> > TDX-protected guest memory, machine check ca
Hi,
This patch fixes a regression introduced with 1c20d3ff6004 ("hw/riscv:
virt: Add a machine done notifier") that is preventing
qemu-system-riscv64 to use the ramfb device starting in QEMU 7.1.
Fix is based on top of Alistair's riscv-to-apply.next:
https://github.com/alistair23/qemu/tree/riscv
Commit 1c20d3ff6004 ("hw/riscv: virt: Add a machine done notifier")
moved the initialization of fw_cfg to the virt_machine_done() callback.
Problem is that the validation of fw_cfg by devices such as ramfb is
done before the machine done notifier is called. Moving create_fw_cfg()
to machine_done()
hi Philippe,
On Tue, 2023-01-17 at 08:04 +0100, Philippe Mathieu-Daudé wrote:
> If you create 2 devices with different properties, the
> first gets its properties overwritten with the second's
> ones.
The !initialized guard should prevent that.
In practize you would not create more usb-ccid device
On Tue, 2023-01-17 at 08:30 +0100, Thomas Huth wrote:
> On 16/01/2023 22.09, Nina Schoetterl-Glausch wrote:
> > On Thu, 2023-01-05 at 15:53 +0100, Pierre Morel wrote:
> > > The modification of the CPU attributes are done through a monitor
> > > commands.
> > >
> > > It allows to move the core insi
On Mon, 9 Jan 2023 at 23:18, ~dreiss-meta wrote:
>
> From: David Reiss
>
> Follows a fairly similar pattern to the existing special register debug
> support. Only reading is implemented, but it should be possible to
> implement writes.
>
> Signed-off-by: David Reiss
> +static struct v8m_stack_
On Tue, Jan 17, 2023 at 11:21:10AM +0800, Binbin Wu wrote:
>
> On 12/2/2022 2:13 PM, Chao Peng wrote:
> > In confidential computing usages, whether a page is private or shared is
> > necessary information for KVM to perform operations like page fault
> > handling, page zapping etc. There are other
On Mon, 9 Jan 2023 at 23:18, ~dreiss-meta wrote:
>
> From: David Reiss
>
> Follows a fairly similar pattern to the existing special register debug
> support. Only reading is implemented, but it should be possible to
> implement writes.
>
> `v7m_mrs_control` was renamed `arm_v7m_mrs_control` and
On Tue, 17 Jan 2023 at 11:35, Peter Maydell wrote:
>
> On Mon, 9 Jan 2023 at 23:18, ~dreiss-meta wrote:
> >
> > From: David Reiss
> >
> > BASEPRI, FAULTMASK, and their _NS equivalents only exist on devices with
> > the Main Extension. However, the MRS instruction did not check this,
> > and the
On Mon, 16 Jan 2023 at 17:30, Laurent Vivier wrote:
>
> Le 11/01/2023 à 09:50, Philippe Mathieu-Daudé a écrit :
> > Series fully reviewed.
> >
> > Since v2:
> > - Use array of const pointers to const (Richard)
> >
> > Since v1:
> > - Fixed overwritten RECEIVING_BIT7 entry (Richard)
> > - Picked R-
On Mon, 2022-12-12 at 18:30 +0100, Paolo Bonzini wrote:
> On 12/9/22 10:55, David Woodhouse wrote:
> > - m->default_machine_opts = "accel=xen,suppress-vmdesc=on";
> > + if (xen_enabled())
> > + m->default_machine_opts = "accel=xen,suppress-vmdesc=on";
> > + else
> > +
On Tue, 10 Jan 2023 at 08:25, Philippe Mathieu-Daudé wrote:
>
> Series fully reviewed.
>
> Since v1:
> - Updated MAINTAINERS
> - Picked R-b tags
>
Applied to target-arm.next, thanks.
-- PMM
QEMU does not compile when enabling clang's thread safety analysis
(TSA),
because some functions create wrappers for pthread mutexes but do
not use any TSA macro. Therefore the compiler fails.
In order to make the compiler happy and avoid adding all the
necessary macros to all callers (lock functi
This serie aims to enable clang Thread Safety Analysis (TSA) in QEMU.
The goal is to use it for our multiqueue project aiming to replace the
block layer AioContext lock with a rwlock and make sure the lock is taken
correctly everywhere [1].
By default, TSA covers pthread mutexes, therefore when ad
QEMU does not compile when enabling clang's thread safety analysis
(TSA),
because some functions create wrappers for pthread mutexes but do
not use any TSA macro. Therefore the compiler fails.
In order to make the compiler happy and avoid adding all the
necessary macros to all callers (lock functi
From: Kevin Wolf
This enables clang's thread safety analysis (TSA), which we'll use to
statically check the block graph locking.
Signed-off-by: Kevin Wolf
Message-Id: <20221207131838.239125-9-kw...@redhat.com>
Reviewed-by: Emanuele Giuseppe Esposito
Signed-off-by: Kevin Wolf
---
configure |
On Fri, 13 Jan 2023 at 13:39, Alex Bennée wrote:
>
> Make it easier to navigate the documentation.
>
> Signed-off-by: Alex Bennée
> ---
> docs/about/index.rst | 16
> docs/system/index.rst | 2 ++
> docs/tools/index.rst | 2 ++
> docs/user/index.rst | 2 ++
> 4 files chan
On 04/01/2023 12:22, Ben Dooks wrote:
From: Ben Dooks
Add support for Microchip MCP25625 SPI based CAN controller which is
very similar to the MCP2515 (and covered by the same Linux driver).
This can be added to any machine with SPI support in the machine
model file.
Example for using this wh
On 1/13/23 19:15, Nina Schoetterl-Glausch wrote:
On Thu, 2023-01-05 at 15:53 +0100, Pierre Morel wrote:
The topology information are attributes of the CPU and are
specified during the CPU device creation.
On hot plug, we gather the topology information on the core,
creates a list of topology
On Fri, 13 Jan 2023 at 13:39, Alex Bennée wrote:
>
> Drop the frankly misleading quickstart section for a more rounded
> introduction section. This new section gives an overview of the
> accelerators and high level introduction to some of the key features
> of the emulator. We also expand on a gen
On Tue, Jan 17, 2023 at 08:52:03AM -0500, Emanuele Giuseppe Esposito wrote:
> From: Kevin Wolf
>
> This enables clang's thread safety analysis (TSA), which we'll use to
> statically check the block graph locking.
>
> Signed-off-by: Kevin Wolf
> Message-Id: <20221207131838.239125-9-kw...@redhat.
On Fri, 13 Jan 2023 at 13:39, Alex Bennée wrote:
>
> This affects both system and user mode emulation so we should probably
> list it up front.
I'm not super-enthusiastic about this simply because it
breaks the current arrangement we have where everything
in about/ is relatively brief meta-inform
On Fri, Jan 13, 2023 at 11:34:52AM +0100, Alexandre Ghiti wrote:
> One can extract the DeviceState pointer from the Object pointer, so pass
> the Object for future commits to access other fields of Object.
>
> No functional changes intended.
>
> Signed-off-by: Alexandre Ghiti
> ---
> target/ris
On Fri, 13 Jan 2023 at 13:39, Alex Bennée wrote:
>
> The main reason to do this is to document our O_BINARY implementation
> decision somewhere. However I've also moved some of the implementation
> details out of qemu-options and added links between the two. As a
> bonus I've highlighted the scary
Hi Klaus,
On 17/1/23 13:30, Klaus Jensen wrote:
Hi Philippe,
Commit 145e2198d749 ("hw/mips/gt64xxx_pci: Endian-swap using
PCI_HOST_BRIDGE MemoryRegionOps") broke my mips64 nvme boot test
(little-endian host, mips64 and nvme boot device).
The pci device doesn't show up and the kernel panics.
Hi Sean,
On Sat, Jan 14, 2023 at 12:38 AM Sean Christopherson wrote:
>
> On Fri, Dec 02, 2022, Chao Peng wrote:
> > This patch series implements KVM guest private memory for confidential
> > computing scenarios like Intel TDX[1]. If a TDX host accesses
> > TDX-protected guest memory, machine chec
On Fri, Jan 13 2023, Fabiano Rosas wrote:
> Signed-off-by: Fabiano Rosas
> ---
> tests/qtest/arm-cpu-features.c | 24
> 1 file changed, 24 insertions(+)
>
> diff --git a/tests/qtest/arm-cpu-features.c b/tests/qtest/arm-cpu-features.c
> index 4be1415823..9a052e41fc 10064
On 17/1/23 14:52, Emanuele Giuseppe Esposito wrote:
QEMU does not compile when enabling clang's thread safety analysis
(TSA),
because some functions create wrappers for pthread mutexes but do
not use any TSA macro. Therefore the compiler fails.
In order to make the compiler happy and avoid addin
Am 17/01/2023 um 15:02 schrieb Daniel P. Berrangé:
> On Tue, Jan 17, 2023 at 08:52:03AM -0500, Emanuele Giuseppe Esposito wrote:
>> From: Kevin Wolf
>>
>> This enables clang's thread safety analysis (TSA), which we'll use to
>> statically check the block graph locking.
>>
>> Signed-off-by: Kevi
Am 17/01/2023 um 15:33 schrieb Philippe Mathieu-Daudé:
> On 17/1/23 14:52, Emanuele Giuseppe Esposito wrote:
>> QEMU does not compile when enabling clang's thread safety analysis
>> (TSA),
>> because some functions create wrappers for pthread mutexes but do
>> not use any TSA macro. Therefore th
On 1/17/2023 5:35 AM, Igor Mammedov wrote:
> On Mon, 16 Jan 2023 13:00:53 -0500
> Chuck Zmudzinski wrote:
>
> > On 1/16/23 10:33, Igor Mammedov wrote:
> > > On Fri, 13 Jan 2023 16:31:26 -0500
> > > Chuck Zmudzinski wrote:
> > >
> > >> On 1/13/23 4:33 AM, Igor Mammedov wrote:
> > >> > On Thu,
On Tue, Jan 17, 2023 at 1:30 AM Bernhard Beschow wrote:
>
>
> Am 16. Januar 2023 16:29:30 UTC schrieb Igor Mammedov >:
> >On Mon, 16 Jan 2023 16:29:03 +0100
> >Bernhard Beschow wrote:
> >
> >> This class attribute was always set to pc_madt_cpu_entry().
> >> pc_madt_cpu_entry() is architecture d
On 1/17/2023 5:35 AM, Igor Mammedov wrote:
> On Mon, 16 Jan 2023 13:00:53 -0500
> Chuck Zmudzinski wrote:
>
> > On 1/16/23 10:33, Igor Mammedov wrote:
> > > On Fri, 13 Jan 2023 16:31:26 -0500
> > > Chuck Zmudzinski wrote:
> > >
> > >> On 1/13/23 4:33 AM, Igor Mammedov wrote:
> > >> > On Thu,
I’m confused by this “one time request” path.
MST - why do we classify SET_MEM_TABLE as a one time request if we send it on
every hot-add/hot-remove.
In particular I’m tripping over the following in vhost_user_write:
/*
* For non-vring specific requests, like VHOST_USER_SET_MEM_TABLE,
* we j
The architecture does not define any functionality for the CLAIM tag bits.
So we will just keep the raw bits, as per spec.
Signed-off-by: Evgeny Iakovlev
Reviewed-by: Peter Maydell
---
target/arm/cpu.h | 1 +
target/arm/debug_helper.c | 38 ++
2 fil
Small series of changes to aarch64 emulation to better support running
Hyper-V as a TCG guest wtih EL3 firmware.
v2:
* DBGCLAIM now implements a (trivial) raw_write handler
* Added comments around ignored external debug registers
* Patch 3 is dropped because it was manually picked into target-arm.
Qemu doesn't implement Debug Communication Channel, as well as the rest
of external debug interface. However, Microsoft Hyper-V tries to access
some of these registers during an EL2 context switch.
Since there is no architectural way to not advertise support for external
debug, provide RAZ/WI stub
On 1/17/23 13:36, Greg Kurz wrote:
On Tue, 17 Jan 2023 13:12:57 +0100
Greg Kurz wrote:
Hi Maxime,
On Tue, 17 Jan 2023 10:49:37 +0100
Maxime Coquelin wrote:
Hi Yajun,
On 1/16/23 08:14, Yajun Wu wrote:
Not quite sure about the whole picture.
Seems while qemu waiting response of vhost_u
On Tue, Jan 17, 2023 at 03:41:29PM +0100, Emanuele Giuseppe Esposito wrote:
>
>
> Am 17/01/2023 um 15:02 schrieb Daniel P. Berrangé:
> > On Tue, Jan 17, 2023 at 08:52:03AM -0500, Emanuele Giuseppe Esposito wrote:
> >> From: Kevin Wolf
> >>
> >> This enables clang's thread safety analysis (TSA),
Hi Eugenio,
On 1/13/23 11:03, Eugenio Perez Martin wrote:
On Fri, Jan 13, 2023 at 10:51 AM Stefano Garzarella wrote:
On Fri, Jan 13, 2023 at 09:19:00AM +0100, Eugenio Perez Martin wrote:
On Fri, Jan 13, 2023 at 5:36 AM Jason Wang wrote:
On Fri, Jan 13, 2023 at 1:25 AM Eugenio Pérez wrote
On 1/17/23 00:28, Peter Maydell wrote:
On Mon, 16 Jan 2023 at 20:16, Richard Henderson
wrote:
Ping.
What did you think of my suggestion in the other thread of hashing
the info we need to determine the cpreg set (ID regs, feature flags,
etc) and using that to look up whether we've already cre
On Fri, 6 Jan 2023 at 17:28, Evgeny Iakovlev
wrote:
>
> Current FIFO handling code does not reset RXFE/RXFF flags when guest
> resets FIFO by writing to UARTLCR register, although internal FIFO state
> is reset to 0 read count. Actual flag update will happen only on next
> read or write to UART. A
On 1/16/23 23:36, Alex Bennée wrote:
Richard Henderson writes:
There are some tests for which SIGTERM appears insufficient.
Signed-off-by: Richard Henderson
---
tests/tcg/Makefile.target | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/tests/tcg/Makefile.target b/t
On Fri, 6 Jan 2023 at 17:29, Evgeny Iakovlev
wrote:
>
> UART should be enabled in general and have RX enabled specifically to be
> able to receive data from peripheral device. Same goes for transmitting
> data to peripheral device and a TXE flag.
>
> Check if UART CR register has EN and RXE or TXE
On Tue, Jan 17, 2023 at 12:22:41PM +0100, David Hildenbrand wrote:
> While playing with migration of virtio-mem with an ordinary file backing,
> I realized that migration and prealloc doesn't currently work as expected
> for virtio-mem. Further, Jing Qi reported that setup issues (insufficient
> hu
On Tue, Jan 17, 2023 at 07:55:08PM +0800, Chuang Xu wrote:
> In this version:
>
> - rename rcu_read_locked() to rcu_read_is_locked().
> - adjust the sanity check in address_space_to_flatview().
> - improve some comments.
Acked-by: Peter Xu
--
Peter Xu
Richard Henderson writes:
> Move the ri == NULL case to the top of the function and return.
> This allows the else to be removed and the code unindented.
>
> Signed-off-by: Richard Henderson
Reviewed-by: Alex Bennée
--
Alex Bennée
Virtualisation Tech Lead @ Linaro
Am 16.12.2022 um 12:07 hat Paolo Bonzini geschrieben:
> Clang has a generic __annotate__ attribute that can be used by
> static analyzers to understand properties of functions and
> analyze the control flow.
>
> Unlike TSA annotations, the __annotate__ attribute applies to function
> pointers as w
Am 15.12.2022 um 14:02 hat Paolo Bonzini geschrieben:
> blkdebug events can be called from either non-coroutine or coroutine
> contexts. However, suspend actions only make sense from within
> a coroutine. Currently, using those action would lead to an abort() in
> qemu_coroutine_yield() ("Co-rout
On Mon, 16 Jan 2023 at 22:36, Richard Henderson
wrote:
>
> The following changes since commit fb7e7990342e59cf67dbd895c1a1e3fb1741df7a:
>
> tests/qtest/qom-test: Do not print tested properties by default (2023-01-16
> 15:00:57 +)
>
> are available in the Git repository at:
>
> https://git
Am 15.12.2022 um 14:02 hat Paolo Bonzini geschrieben:
> qemu-io's do_co_pwrite_zeroes is reinventing the coroutine wrapper
> blk_pwrite_zeroes. Just use the real thing directly.
>
> Signed-off-by: Paolo Bonzini
Thanks, applied to the block branch.
Kevin
On 1/17/23 05:04, Evgeny Iakovlev wrote:
+{ .name = "DBGCLAIMCLR_EL1", .state = ARM_CP_STATE_BOTH,
+ .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 7, .crm = 9, .opc2 = 6,
+ .access = PL1_RW, .accessfn = access_tda,
+ .writefn = dbgclaimclr_write, .raw_writefn = dbgclaimclr_raw_write,
On 17/1/23 15:43, Emanuele Giuseppe Esposito wrote:
Am 17/01/2023 um 15:33 schrieb Philippe Mathieu-Daudé:
On 17/1/23 14:52, Emanuele Giuseppe Esposito wrote:
QEMU does not compile when enabling clang's thread safety analysis
(TSA),
because some functions create wrappers for pthread mutexes b
Am 15.12.2022 um 14:02 hat Paolo Bonzini geschrieben:
> It has only one caller---inline it and remove the function.
>
> Signed-off-by: Paolo Bonzini
Thanks, applied to the block branch.
Kevin
On 1/17/2023 16:24, Peter Maydell wrote:
On Fri, 6 Jan 2023 at 17:28, Evgeny Iakovlev
wrote:
Current FIFO handling code does not reset RXFE/RXFF flags when guest
resets FIFO by writing to UARTLCR register, although internal FIFO state
is reset to 0 read count. Actual flag update will happen o
From: David Woodhouse
It isn't strictly mandatory but Linux guests at least will only map their
grant tables over the dummy BAR that it provides, and don't sufficient wit
to map them in any other unused part of their guest address space. So
include it by default for minimal surprise factor.
As I
From: David Woodhouse
Signed-off-by: David Woodhouse
---
docs/system/i386/xen.rst| 50 +
docs/system/target-i386.rst | 1 +
2 files changed, 51 insertions(+)
create mode 100644 docs/system/i386/xen.rst
diff --git a/docs/system/i386/xen.rst b/docs/syste
On Tue, 17 Jan 2023 at 15:54, Evgeny Iakovlev
wrote:
>
>
> On 1/17/2023 16:24, Peter Maydell wrote:
> > On Fri, 6 Jan 2023 at 17:28, Evgeny Iakovlev
> > wrote:
> >> Current FIFO handling code does not reset RXFE/RXFF flags when guest
> >> resets FIFO by writing to UARTLCR register, although inter
On Mon, Jan 16, 2023 at 10:14:07PM +0100, Klaus Jensen wrote:
[ ... ]
>
> I noticed that the Linux driver does not use the INTMS/INTMC registers
> to mask interrupts on the controller while processing CQEs. While not
> required by the spec, it is *recommended* in setups not using MSI-X to
> reduce
On Mon, Jan 16, 2023 at 09:58:13PM -0700, Keith Busch wrote:
> On Mon, Jan 16, 2023 at 10:14:07PM +0100, Klaus Jensen wrote:
> > I noticed that the Linux driver does not use the INTMS/INTMC registers
> > to mask interrupts on the controller while processing CQEs. While not
> > required by the spec,
On 13/1/23 15:03, Fabiano Rosas wrote:
Move this earlier to make the next patch diff cleaner. While here
update the comment slightly to not give the impression that the
misalignment affects only TCG.
Reviewed-by: Richard Henderson
Signed-off-by: Fabiano Rosas
---
target/arm/machine.c | 18 ++
On 13/1/23 15:03, Fabiano Rosas wrote:
Since commit cf7c6d1004 ("target/arm: Split out cpregs.h") we now have
a cpregs.h header which is more suitable for this code.
Code moved verbatim.
Signed-off-by: Fabiano Rosas
---
target/arm/cpregs.h | 98 +
On Tue, Jan 17, 2023 at 6:52 AM Emanuele Giuseppe Esposito <
eespo...@redhat.com> wrote:
> QEMU does not compile when enabling clang's thread safety analysis
> (TSA),
> because some functions create wrappers for pthread mutexes but do
> not use any TSA macro. Therefore the compiler fails.
>
> In o
On Wed, 11 Jan 2023 at 16:13, Cornelia Huck wrote:
>
> Introduce a new cpu feature flag to control MTE support. To preserve
> backwards compatibility for tcg, MTE will continue to be enabled as
> long as tag memory has been provided.
>
> If MTE has been enabled, we need to disable migration, as we
On 13/1/23 15:03, Fabiano Rosas wrote:
Code moved verbatim.
Signed-off-by: Fabiano Rosas
Reviewed-by: Richard Henderson
---
target/arm/cpregs.c | 9087 +++
target/arm/helper.c | 9063 --
Nice diffstat...
ta
On Fri, Jan 13, 2023 at 09:01:34PM +0100, Philippe Mathieu-Daudé wrote:
> - remove unused code
> - use recent QOM macros
> - use CamelCase typedef
>
> Philippe Mathieu-Daudé (4):
> iothread: Remove unused IOThreadClass / IOTHREAD_CLASS
> hw/irq: Declare QOM macros using OBJECT_DECLARE_SIMPLE_T
On Tue, 17 Jan 2023 at 16:10, Guenter Roeck wrote:
>
> On Mon, Jan 16, 2023 at 09:58:13PM -0700, Keith Busch wrote:
> > On Mon, Jan 16, 2023 at 10:14:07PM +0100, Klaus Jensen wrote:
> > > I noticed that the Linux driver does not use the INTMS/INTMC registers
> > > to mask interrupts on the control
Am 17.01.2023 um 16:01 hat Daniel P. Berrangé geschrieben:
> On Tue, Jan 17, 2023 at 03:41:29PM +0100, Emanuele Giuseppe Esposito wrote:
> >
> >
> > Am 17/01/2023 um 15:02 schrieb Daniel P. Berrangé:
> > > On Tue, Jan 17, 2023 at 08:52:03AM -0500, Emanuele Giuseppe Esposito
> > > wrote:
> > >> F
Am 17/01/2023 um 17:16 schrieb Warner Losh:
>
>
> On Tue, Jan 17, 2023 at 6:52 AM Emanuele Giuseppe Esposito
> mailto:eespo...@redhat.com>> wrote:
>
> QEMU does not compile when enabling clang's thread safety analysis
> (TSA),
> because some functions create wrappers for pthread m
On 13/1/23 15:04, Fabiano Rosas wrote:
From: Claudio Fontana
Signed-off-by: Claudio Fontana
Signed-off-by: Fabiano Rosas
Reviewed-by: Richard Henderson
---
---
target/arm/meson.build | 16 ++--
target/arm/tcg-stubs.c | 23 +++
On Tue, Jan 17, 2023 at 08:52:00AM -0500, Emanuele Giuseppe Esposito wrote:
> This serie aims to enable clang Thread Safety Analysis (TSA) in QEMU.
It's worth covering what TSA is and why it's useful:
Thread Safety Analysis "warns about potential race conditions in code.
The analysis is completel
Am 17.01.2023 um 17:16 hat Warner Losh geschrieben:
> On Tue, Jan 17, 2023 at 6:52 AM Emanuele Giuseppe Esposito <
> eespo...@redhat.com> wrote:
>
> > QEMU does not compile when enabling clang's thread safety analysis
> > (TSA),
> > because some functions create wrappers for pthread mutexes but do
On 13/1/23 15:04, Fabiano Rosas wrote:
This is in preparation to moving the hflags code into its own file
under the tcg/ directory.
Signed-off-by: Fabiano Rosas
---
I extracted these into a separate patch so we can discuss. If I move
the tcg_enabled check to a header that would add overhead for
On 13/1/23 15:04, Fabiano Rosas wrote:
This struct has no dependencies on TCG code and it is being used in
target/arm/ptw.c to simplify the passing around of page table walk
results. Those routines can be reached by KVM code via the gdbstub
breakpoint code, so take the structure out of CONFIG_TCG
On Fri, Jan 13, 2023 at 11:34:53AM +0100, Alexandre Ghiti wrote:
> RISC-V specifies multiple sizes for addressable memory and Linux probes for
> the machine's support at startup via the satp CSR register (done in
> csr.c:validate_vm).
>
> As per the specification, sv64 must support sv57, which in
On Tue, Jan 17, 2023 at 08:52:02AM -0500, Emanuele Giuseppe Esposito wrote:
> QEMU does not compile when enabling clang's thread safety analysis
> (TSA),
> because some functions create wrappers for pthread mutexes but do
> not use any TSA macro. Therefore the compiler fails.
>
> In order to make
On Thu, 12 Jan 2023 at 10:24, Philippe Mathieu-Daudé wrote:
>
> This is a respin of Richard's patch
> https://lore.kernel.org/qemu-devel/20230112004322.161330-1-richard.hender...@linaro.org/
> but split in multiple trivial changes, as I was having hard
> time to understand all changes at once whil
On Tue, Jan 17, 2023, Chao Peng wrote:
> On Fri, Jan 13, 2023 at 09:54:41PM +, Sean Christopherson wrote:
> > > + list_for_each_entry(notifier, &data->notifiers, list) {
> > > + notifier->ops->invalidate_start(notifier, start, end);
> >
> > Two major design issues that we overlooked lo
On Sat, 14 Jan 2023 at 03:12, Richard Henderson
wrote:
>
> Conversion to probe_access_full missed applying the page offset.
>
> Fixes: b8967ddf ("target/arm: Use probe_access_full for MTE")
> Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1416
> Signed-off-by: Richard Henderson
> ---
>
On Sat, 14 Jan 2023 at 05:47, Richard Henderson
wrote:
>
> During the conversion, the test against get_phys_addr_lpae got inverted,
> meaning that successful translations went to the 'failed' label.
>
> Cc: qemu-sta...@nongnu.org
> Fixes: f3639a64f60 ("target/arm: Use softmmu tlbs for page table w
On 13/1/23 15:04, Fabiano Rosas wrote:
The cpu_tcg.c file about to be moved into the tcg directory. Move the
code that is needed for cpus that also work with KVM into cpu.c.
Signed-off-by: Fabiano Rosas
---
target/arm/cpu.c | 76 +++
target/arm/cpu
On Tue, Jan 17, 2023 at 9:25 AM Kevin Wolf wrote:
> Am 17.01.2023 um 17:16 hat Warner Losh geschrieben:
> > On Tue, Jan 17, 2023 at 6:52 AM Emanuele Giuseppe Esposito <
> > eespo...@redhat.com> wrote:
> >
> > > QEMU does not compile when enabling clang's thread safety analysis
> > > (TSA),
> > >
On 17/01/2023 14.15, Laurent Vivier wrote:
Signed-off-by: Laurent Vivier
Acked-by: Michael S. Tsirkin
Acked-by: Thomas Huth
---
Notes:
v6:
- call socket_init() otherwise socket_check_protocol_support() fails
- if socket_check_protocol_support() fails then calls g_abort() to
Migrate from aarch64 host with PAGE_SIZE 64k to 4k failed with following errors:
qmp_cmd_name: migrate-incoming, arguments: {"uri": "tcp:[::]:49152"}
{"timestamp": {"seconds": 1673922775, "microseconds": 534702}, "event":
"MIGRATION", "data": {"status": "setup"}}
{"timestamp": {"seconds": 1673922
On 12/2/2022 2:13 PM, Chao Peng wrote:
In confidential computing usages, whether a page is private or shared is
necessary information for KVM to perform operations like page fault
handling, page zapping etc. There are other potential use cases for
per-page memory attributes, e.g. to make memory
On Tue, 2023-01-17 at 14:55 +0100, Pierre Morel wrote:
>
> On 1/13/23 19:15, Nina Schoetterl-Glausch wrote:
> >
[...]
> > > +/**
> > > + * s390_topology_set_entry:
> > > + * @entry: Topology entry to setup
> > > + * @id: topology id to use for the setup
> > > + *
> > > + * Set the core bit insid
* Peter Maydell (peter.mayd...@linaro.org) wrote:
> On Wed, 11 Jan 2023 at 16:13, Cornelia Huck wrote:
> >
> > Introduce a new cpu feature flag to control MTE support. To preserve
> > backwards compatibility for tcg, MTE will continue to be enabled as
> > long as tag memory has been provided.
> >
On Tue, Jan 17 2023, Peter Maydell wrote:
> On Wed, 11 Jan 2023 at 16:13, Cornelia Huck wrote:
>>
>> Introduce a new cpu feature flag to control MTE support. To preserve
>> backwards compatibility for tcg, MTE will continue to be enabled as
>> long as tag memory has been provided.
>>
>> If MTE h
On 1/10/23 15:29, Thomas Huth wrote:
On 05/01/2023 15.53, Pierre Morel wrote:
On interception of STSI(15.1.x) the System Information Block
(SYSIB) is built from the list of pre-ordered topology entries.
Signed-off-by: Pierre Morel
---
...
diff --git a/target/s390x/cpu.h b/target/s390x/cpu
On 1/11/23 18:14, Nina Schoetterl-Glausch wrote:
On Tue, 2023-01-10 at 15:29 +0100, Thomas Huth wrote:
On 05/01/2023 15.53, Pierre Morel wrote:
On interception of STSI(15.1.x) the System Information Block
(SYSIB) is built from the list of pre-ordered topology entries.
Signed-off-by: Pierre
On Tue, 17 Jan 2023 at 16:51, Dr. David Alan Gilbert
wrote:
>
> * Peter Maydell (peter.mayd...@linaro.org) wrote:
> > On Wed, 11 Jan 2023 at 16:13, Cornelia Huck wrote:
> > > +MTE CPU Property
> > > +
> > > +
> > > +The ``mte`` property controls the Memory Tagging Extension. For T
Hi Evgeny,
On 1/16/23 16:37, Evgeny Iakovlev wrote:
> Hi!
>
>
> We are using qemu-tcg-aarch64 to run Hyper-V test and debug builds for
> arm. Besides some minor fixes that i have submitted over the last
> couple of weeks, one big compatibility item for us is SMMUv3 2-stage
> translations support. W
Apologies for the late response, I was traveling most of yesterday.
On 1/16/23 4:22 AM, Daniel P. Berrangé wrote:
When we introduce a new QAPI format for migration args though, I've
suggested we drop support for passing exec via shell, and require an
explicit argv[] array:
https://lists.gnu.
On Tue, Jan 17 2023, "Dr. David Alan Gilbert" wrote:
> * Peter Maydell (peter.mayd...@linaro.org) wrote:
>> On Wed, 11 Jan 2023 at 16:13, Cornelia Huck wrote:
>> >
>> > Introduce a new cpu feature flag to control MTE support. To preserve
>> > backwards compatibility for tcg, MTE will continue to
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